A server monitoring chip replacement card system

Abstract

The application relates to a server monitoring chip replacement card system, which comprises a first function module and a second function module; the first function module and the second function module are connected through an inter-chip communication interface; the first function module verifies the function of a main system of a chip; the second function module verifies the function of a communication interface of the chip; the second function module comprises a first communication verification unit, a second communication verification unit and a plurality of types of communication interfaces; the first communication verification unit and the second communication verification unit share the communication interfaces; the first communication verification unit is used for verifying the function of the communication interfaces; the second communication verification unit is used for verifying the function of a low-voltage differential signal tunnel protocol interface; and switching is performed between the first communication verification unit and the second communication verification unit through a switch. In this way, the verification of a serial general-purpose input / output interface and a low-voltage differential signal tunnel protocol interface can be compatible, and the low-voltage differential signal tunnel protocol interface does not need to be additionally arranged, so that cost is saved.

Description

Technical Field

[0001] This invention relates to the field of server monitoring, and more specifically to a server monitoring chip replacement card system. Background Technology

[0002] A replacement card system is a system that simulates some functions of a chip, enabling the verification of certain chip functionalities before chip fabrication, ensuring the correctness and usability of the chip's structural and code design. Currently, most mainstream server monitoring chips, namely Baseboard Management Controller (BMC) chips, use Serial General Purpose Input / Output (SGPIO) interfaces to connect to the server motherboard for information transmission, and corresponding replacement card systems also use serial input / output interfaces. However, using Low-Voltage Differential Signaling Tunneling Protocol (LTPI) for information transmission between server monitoring chips and server boards is becoming a growing trend. Current replacement card systems lack an LTPI interface, making its verification impossible, necessitating a redesign of the replacement card system. Summary of the Invention

[0003] In view of this, the present invention provides a server monitoring chip replacement card system to solve the problem that the current server monitoring chip replacement card system can only verify serial general-purpose input / output interfaces, but cannot verify low-voltage differential signal tunneling protocol interfaces.

[0004] This invention provides a server monitoring chip replacement card system, comprising a first functional module and a second functional module;

[0005] The first functional module and the second functional module are connected through an inter-chip communication interface;

[0006] The first functional module is used to verify the functionality of the chip's main system.

[0007] The second functional module is used to verify the functionality of the chip's communication interface;

[0008] The second functional module includes a first communication verification unit, a second communication verification unit, and multiple types of communication interfaces; the first and second communication verification units share multiple types of communication interfaces; the first communication verification unit is used to verify the functionality of the multiple types of communication interfaces; the second communication verification unit is used to verify the functionality of the low-voltage differential signal tunneling protocol interface;

[0009] Switching between the first and second communication verification units is achieved by using a toggle switch.

[0010] In this way, the verification of both the serial universal input / output interface and the low-voltage differential signal tunneling protocol interface can be compatible in the server monitoring chip replacement card system. The verification can be performed on either the serial universal input / output interface or the low-voltage differential signal tunneling protocol interface according to the verification requirements. At the same time, there is no need to set up the low-voltage differential signal tunneling protocol interface separately, saving costs.

[0011] In one optional implementation, the first functional module includes a processor unit, a communication unit, and a functional verification unit.

[0012] The processor unit, communication unit, and functional verification unit transmit information via a network interconnect bus;

[0013] The communication interface in the communication unit connects to the server to establish a connection between the system and the server in order to obtain monitoring information from the server.

[0014] The processor unit runs the verification program and processes the monitoring information to obtain verification data;

[0015] The functional verification unit determines the functional verification status based on the verification data.

[0016] This allows us to verify whether the corresponding chip in the server monitoring chip replacement card system can function properly.

[0017] In one alternative implementation, the processor unit comprises a first processor and a second processor;

[0018] The first processor is used to run the verification program;

[0019] The second processor is used to process monitoring information;

[0020] The first processor and the second processor are respectively connected to the memory controller, and obtain data from the memory through the memory controller, and / or store data into the memory through the memory controller.

[0021] By using the first processor as the main processor and the second processor as a coprocessor, the processing speed of the server monitoring chip replacement card system can be improved.

[0022] In one alternative implementation, the first processor and the second processor share memory through a shared memory mechanism;

[0023] When the shared memory mechanism is interrupted, the second processor interacts with the first processor through the first processor's system bus.

[0024] In one optional implementation, the communication unit further includes a secure digital card controller, an embedded multimedia card controller, a secure digital card interface, and an embedded multimedia card.

[0025] The secure digital card controller is connected to the secure digital card interface, which is used to connect secure digital cards.

[0026] The embedded multimedia card controller connects to the embedded multimedia card;

[0027] Secure digital cards and embedded multimedia cards are used to store authentication programs.

[0028] In one alternative implementation, the communication unit further includes a flash memory programmer for programming a verification program.

[0029] In this way, the verification program can be provided through a variety of boot media, and verification can be performed on a variety of boot media.

[0030] In one optional implementation, the functional verification unit includes a reset subunit, a function selection subunit, and a display subunit;

[0031] The reset subunit is used to reset the processor unit when an abnormality occurs in the processor unit;

[0032] The function selection subunit is used to select the function that needs to be verified;

[0033] The display subunit is used to display the running position of the verification program.

[0034] In this way, the running position of the verification program can be displayed intuitively, and when the verification program encounters an error, the error location of the verification program can be clearly determined based on the displayed running position.

[0035] In one optional implementation, the first communication verification unit and the second communication verification unit interact with the first functional module through an advanced scalable interface and an inter-chip communication interface, transmitting interactive information from multiple types of communication interfaces to the first functional module.

[0036] In one optional implementation, the first communication verification unit includes multiple communication verification subunits; the multiple communication verification subunits correspond one-to-one with multiple types of communication interfaces, and respectively transmit the interactive information in the corresponding communication interface.

[0037] In one optional implementation, the second communication verification unit obtains multiple types of interaction information from multiple types of communication interfaces, and packages the multiple types of interaction information according to the low-voltage differential signal tunneling protocol to obtain packaged interaction information; the packaged interaction information is parsed back into multiple types of interaction information in the first functional module.

[0038] In this way, parallel to serial output of multiple types of interactive information can be achieved, enabling the interactive information to be transmitted in accordance with the Low Voltage Differential Signal Tunneling Protocol (LDS), thereby completing the verification of the LDS interface.

[0039] In one optional implementation, the second functional module further includes a security verification unit and a universal serial bus expansion unit;

[0040] The security verification unit and the universal serial bus expansion unit interact with the first functional module through advanced scalable interfaces and inter-chip communication interfaces.

[0041] The security verification unit is used to verify the encryption function of the chip;

[0042] The Universal Serial Bus (USB) expansion unit is used to verify the functionality of the chip's extended USB interface.

[0043] In one alternative implementation, the system further includes a power supply and a corresponding power supply device; the power supply and the power supply device are used to provide independent power to the system.

[0044] In this way, the server monitoring chip replacement card system can be debugged and verified separately, achieving chip-level verification. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0049] Figure 4 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0050] Figure 5 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention.

[0053] The following is supplementary explanation of the attached figures:

[0054] 110 - First functional module; 111 - Processor unit; 112 - Communication unit; 113 - Functional verification unit; 114 - Network interconnection bus; 120 - Second functional module; 121 - First communication verification unit; 122 - Second communication verification unit; 1211 - Communication verification subunit; 123 - Communication interface; 124 - Advanced scalable interface; 130 - Inter-chip communication interface. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0057] Please see Figure 1 , Figure 1 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the system includes a first functional module 110 and a second functional module 120; the first functional module 110 and the second functional module 120 are connected through an inter-chip communication interface 130. The first functional module 110 is used to verify the functionality of the chip's main system, and the second functional module 120 is used to verify the functionality of the chip's communication interface.

[0058] Specifically, the second functional module 120 includes a first communication verification unit 121, a second communication verification unit 122, and multiple types of communication interfaces 123, wherein the first communication verification unit 121 and the second communication verification unit 122 share the multiple types of communication interfaces 123. The first communication verification unit 121 is used to verify the functions of the multiple types of communication interfaces; the second communication verification unit 122 is used to verify the functions of the low-voltage differential signal tunneling protocol interface; switching between the first communication verification unit 121 and the second communication verification unit 122 is achieved via a switch.

[0059] In this way, the verification of both the serial universal input / output interface and the low-voltage differential signal tunneling protocol interface can be compatible in the server monitoring chip replacement card system. The verification can be performed on either the serial universal input / output interface or the low-voltage differential signal tunneling protocol interface according to the verification requirements. At the same time, there is no need to set up the low-voltage differential signal tunneling protocol interface separately, saving costs.

[0060] In one alternative implementation, Figures 2-4 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention. Specifically, Figure 2 This diagram illustrates the structure of the first functional module 110 of a server monitoring chip replacement card system according to an embodiment of the present invention. Figure 3 This diagram illustrates the architecture of a server monitoring chip replacement card system according to an embodiment of the present invention. Figure 4 This diagram illustrates the architecture of the first functional module 110 of a server monitoring chip replacement card system according to an embodiment of the present invention. Figures 2-4 As shown, the first functional module 110 includes a processor unit 111, a communication unit 112, and a function verification unit 113. The processor unit 111, communication unit 112, and function verification unit 113 transmit information via a network interconnection bus 114. The communication interface in the communication unit 112 connects to the server, establishing a connection between the system and the server to obtain monitoring information from the server. The processor unit 111 runs a verification program and processes the monitoring information to obtain verification data. Based on the verification data, the function verification unit 113 determines the function verification status. In this way, it is possible to verify whether the function of the chip corresponding to the server monitoring chip replacement card system can be used normally.

[0061] In one optional implementation, the processor unit 111 comprises a first processor and a second processor. The first processor runs the verification program, and the second processor processes monitoring information; that is, the first processor acts as the main processor, and the second processor acts as a coprocessor. Through the collaborative processing and division of labor between the first and second processors, the processing speed of the server monitoring chip replacement card system is improved. Figure 3 As shown, the first processor can be an ARM Cortex-A55 processor, and the second processor can be an ARM Cortex-M33 processor.

[0062] In one alternative implementation, Figure 5 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention. Specifically, Figure 5 This diagram illustrates the architecture of a processor unit 111 in a server monitoring chip replacement card system according to an embodiment of the present invention. Figure 3 and Figure 4 As shown, the ARM Cortex-A55 processor, i.e. the first processor, and the ARM Cortex-M33 processor, i.e. the second processor, are respectively connected to the memory controller. The memory controller obtains data from the memory and / or stores data into the memory, thereby completing the data reading and writing.

[0063] In one alternative implementation, the first processor and the second processor can share memory through a shared memory mechanism. (See reference...) Figure 5 When the shared memory mechanism is not interrupted, both the first processor and the second processor interact with the memory controller. When the shared memory mechanism is interrupted, the second processor no longer interacts with the memory controller, but interacts with the first processor through the system bus of the first processor, namely the A55 system bus, thereby realizing the information interaction between the first processor and the second processor, namely the main coprocessor.

[0064] In one alternative implementation, such as Figure 3 and Figure 5As shown, the interfaces for information interaction with the first processor include an Ethernet Media Access Controller (EMAC) interface, a Serial Peripheral Interface (SPI), a Joint Test Action Group (JTAG) interface, and a Universal Asynchronous Receiver / Transmitter (UART) interface. The EMAC interface is used for network access, while the SPI, JTAG, and UART interfaces are all high-speed communication interfaces. Specifically, the SPI interface is a synchronous peripheral interface that allows the system to communicate serially with various peripheral devices; in this embodiment, it is used to access the flash memory of the server monitoring chip replacement card. The JTAG interface is an international standard testing protocol, primarily used for internal chip testing; in this embodiment, it is used to burn verification programs. The UART interface is a universal serial data bus for asynchronous communication, used to communicate with the server; in this embodiment, it is used to debug the server monitoring chip replacement card.

[0065] In one alternative implementation, the joint test workgroup interface can also be used to debug processor unit 111 and to verify functionality, so as to locate the problem when the server monitoring chip replacement card is functionally verified.

[0066] In one alternative implementation, such as Figure 3 and Figure 5 As shown, the devices that interact with the second processor include Read-Only Memory (ROM), Synchronous Dynamic Random-access Memory (SDRAM), and Queued Serial Peripheral Interface (QSPI). The QSPI is used to communicate with the server's processor when the server monitoring chip replacement card is powered on.

[0067] In one alternative implementation, such as Figure 3As shown, the communication unit 112 also includes a Secure Digital Card (SD) controller, an Embedded Multimedia Card (eMMC) controller, a Secure Digital Card (SD) interface, and an Embedded Multimedia Card (eMMC). Specifically, the SD interface can connect to the SD card in a slot to read the verification program stored in the SD card; the embedded multimedia card and the embedded multimedia card controller can be integrated into a single chip in a Ball Grid Array (BGA) package, with the verification program stored in the embedded multimedia card. Both the SD card and the embedded multimedia card can be used to store the verification program, serving as the boot medium for the server monitoring chip replacement card system.

[0068] In an optional implementation, the communication unit 112 further includes a flash memory programmer. Flash memory serves as one of the boot media for the server monitoring chip replacement card system, and the corresponding flash memory programmer is used to program the verification program. Flash memory, also known as flash storage, is a type of erasable programmable read-only memory that can be erased and rewritten multiple times. Therefore, for different verification schemes or when the verification program has problems and needs modification, the data in the flash memory can be reprogrammed to complete the modification of the verification program. This achieves the repeatability and modifiability of the verification program and verification scheme of the server monitoring chip replacement card system.

[0069] In one alternative implementation, when a problem occurs with the flash memory or flash programmer, a verification program can be programmed through the joint testing working group interface to achieve redundancy of the boot media and improve the reliability of the server monitoring chip replacement card system.

[0070] As can be seen from the above, the boot media of the server monitoring chip replacement card system includes at least a secure digital card, an embedded multimedia card, and flash memory. Therefore, the verification program can be provided through multiple boot media, and the server monitoring chip replacement card system can also verify multiple boot media.

[0071] In one alternative implementation, refer to Figure 3 The communication unit 112 may also include multiple high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interfaces, all of which are in slave (End Point, EP) mode. In this mode, the high-speed serial computer expansion bus standard interface receives read and write operations for the local memory space, i.e., the memory space of the server monitoring chip replacement card system.

[0072] In one alternative implementation, refer to Figure 3 The PCIe EP1 interface, one of the multiple high-speed serial computer expansion bus standard interfaces, directly connects to the server motherboard to enable KVM remote access and H2B (Host to BMC) functions. This allows the server monitoring chip replacement card system to verify the KVM remote access and H2B functions. Specifically, as shown in the figure, the KVM remote access function enables remote transmission and display of the keyboard, mouse, and video, allowing for remote video playback (playing video on the server host) and remote interaction between the keyboard / mouse and the server host. The H2B function facilitates information exchange between the server host and the server monitoring chip, i.e., the server monitoring chip replacement card system. Furthermore, this high-speed serial computer expansion bus standard interface can also enable remote access to virtual media (Vmedia).

[0073] In one alternative implementation, refer to Figure 3 The PCIe EP2 interface is one of the multiple high-speed serial computer expansion bus standard interfaces. One of these high-speed serial computer expansion bus standard interfaces is used to expand the gold fingers of the high-speed serial computer expansion bus standard interface to implement the Management Component Transport Protocol (MCTP) function.

[0074] In an alternative implementation, the communication unit 112 further includes a network connector, such as... Figure 3 As shown, the network connector can be an RJ45 port, which connects to an Ethernet interface to access the Ethernet media access controller. The Ethernet media access controller communicates with the first processor via the network interconnect bus 114, thereby connecting the network to the server monitoring chip replacement card system. The Ethernet interface can be either a Reduced Media Independent Interface (RMII) or a Reduced Gigabit Media Independent Interface (RGMII), supporting bus interface speeds of 10M and 100M respectively.

[0075] In one alternative implementation, refer to Figure 3The communication unit 112 also includes multiple communication interfaces for acquiring monitoring information. These interfaces are connected to an Advanced Peripheral Bus (APB) matrix in the server monitoring chip replacement card system, and the acquired monitoring information is transmitted to the processor unit 111 via the APB matrix. Specifically, these communication interfaces include a Platform Environment Control Interface (PECI), a Universal Asynchronous Receiver / Transmitter (UART) interface, and an Inter-Integrated Circuit (I2C) interface. The PECI is a bus used to monitor the temperature of the processor and chipset; in this embodiment, it is used to monitor the temperature information of the server processor. The I2C interface receives I2C bus signals, which are used to monitor server temperature and device information. The UART is a serial data bus interface; in this embodiment, it is used to view status information via a cable.

[0076] In an alternative implementation, a timer and a watchdog (WTG) can also be configured to monitor relevant information about the server monitoring chip replacement card system itself.

[0077] In one alternative implementation, refer to Figure 3 The functional verification unit 113 includes a reset subunit, a function selection subunit, and a display subunit. The reset subunit is used to reset the processor unit 111 when an abnormality occurs in the processor unit; the function selection subunit is used to select the function to be verified; and the display subunit is used to display the running position of the verification program.

[0078] Specifically, with Figure 3 For example, Figure 3 The button corresponds to the reset subunit in this embodiment of the invention. When the first processor or the second processor crashes or malfunctions, it can be reset using the button. Accordingly, the first processor and the second processor each have corresponding buttons. When the first processor or the second processor needs to be reset, pressing the corresponding button will reset it. This achieves rapid reset when the processor unit 111 malfunctions.

[0079] Figure 3 In this embodiment of the invention, the DIP switch corresponds to the function selection subunit. Each DIP switch corresponds to a function. By adjusting the open or closed state of the DIP switch, the corresponding function can be selected.

[0080] Figure 3 In this embodiment, the 80-port digital tube corresponds to the display subunit. The 80-port digital tube can display hexadecimal values ​​from 00 to FF. When writing the verification program, each segment requiring a specific number is numbered using any non-repeating hexadecimal value from 00 to FF. When the processor unit 111 runs the verification program, the 80-port digital tube can display the number of the specific segment in the currently running verification program in real time, thus showing the program's running position and enabling location tracking. This allows for a direct and intuitive display of the verification program's running position. If an error occurs, the displayed running position can be used to clearly pinpoint the error location. When the 80-port digital tube displays FF, it indicates that the verification program has completed its execution and is functioning correctly.

[0081] In one alternative implementation, the display subunit may further include an LED light, which is used to indicate whether the server monitoring chip replacement card system is powered on. When the LED light is on, it indicates that the server monitoring chip replacement card system has been powered on.

[0082] In one alternative implementation, Figures 6-7 This is a schematic diagram of a server monitoring chip replacement card system provided in an embodiment of the present invention. Specifically, Figure 6 This diagram illustrates the structure of a second functional module 120 of a server monitoring chip replacement card system according to an embodiment of the present invention. Figure 7 This diagram illustrates the architecture of a second functional module 120 of a server monitoring chip replacement card system according to an embodiment of the present invention. Figures 6-7 As shown, the first communication verification unit 121 and the second communication verification unit 122 interact with the first functional module 110 through the advanced scalable interface 124 and the inter-chip communication interface 130, and transmit the interactive information in multiple types of communication interfaces 123 to the first functional module 110.

[0083] In one optional implementation, the first communication verification unit 121 includes multiple communication verification subunits 1211, each corresponding to a different type of communication interface 123, and each subunit transmits interactive information from its corresponding communication interface 123. For example... Figure 7As shown, the communication interface 123 may include a general-purpose input / output (GPIO) port, a general-purpose asynchronous transceiver (GPIO) interface, and an integrated circuit bus interface; correspondingly, the communication verification subunit 1211 may include a GPIO transmission channel, a GPIO transmission channel, and an integrated circuit bus transmission channel. Interactive information obtained from the GPIO port is sequentially transmitted to the first functional module 110 through the GPIO transmission channel, the advanced scalability interface 124, and the inter-chip communication interface 130; interactive information obtained from the GPIO transmission interface is sequentially transmitted to the first functional module 110 through the GPIO transmission channel, the advanced scalability interface 124, and the inter-chip communication interface 130; interactive information obtained from the integrated circuit bus transmission interface is sequentially transmitted to the first functional module 110 through the integrated circuit bus transmission channel, the advanced scalability interface 124, and the inter-chip communication interface 130.

[0084] In one optional implementation, the second communication verification unit 122 obtains corresponding type of interaction information from multiple types of communication interfaces 123, and packages these interaction information according to the Low Voltage Differential Signal Tunneling Protocol (LDPT) to obtain packaged interaction information. This enables the parallel-to-serial conversion of these interaction information for transmission according to the LDPT. Thus, without adding a LDPT interface, communication transmission according to the LDPT can be achieved, thereby verifying the LDPT.

[0085] In one alternative implementation, the packaged interactive information is transmitted to the first functional module 110 through the tier scalable interface 123 and the inter-chip communication interface 130, and then parsed in the first functional module 110 according to the low-voltage differential signal tunneling protocol to obtain multiple types of interactive information.

[0086] In one optional implementation, each communication verification subunit 1211 in the first communication verification unit 121 is equipped with a switch. When the switch is in a first state, the channel for transmitting the interaction information corresponding to that communication verification subunit 1211 to the second communication verification unit 122 is closed; when the switch is in a second state, the channel for transmitting the interaction information corresponding to that communication verification subunit 1211 to the second communication verification unit 122 is open, while the transmission channel of the communication verification subunit 1211 is closed, or both the transmission channels of the communication verification subunit 1211 and the second communication verification unit 122 are open. This avoids the low-voltage differential signal tunneling protocol interface being open and affecting the verification of the communication interface in the first communication verification unit 121 when verification of the low-voltage differential signal tunneling protocol interface is not required.

[0087] In one optional implementation, the first state of the switch can be on and the second state can be off; alternatively, the first state of the switch can also be off and the second state can also be on. The setting of the first and second states of the switch is related to its specific design. For example, when the switch is connected in series in the information transmission channel of the second communication verification unit 122, the first state of the switch is on and the second state is off; when the switch is connected in parallel in the information transmission channel of the second communication verification unit 122, the first state of the switch is off and the second state is on.

[0088] In one alternative implementation, refer to Figure 7 The second functional module 120 also includes a security verification unit and a universal serial bus (USB) expansion unit. The security verification unit and the USB expansion unit interact with the first functional module 110 via an advanced scalable interface 124 and an inter-chip communication interface 130. Specifically, the security verification unit verifies the chip's encryption functions, including a secure boot subunit and an encryption / decryption engine subunit, and encrypts the modules of the server monitoring chip replacement card system using an encryption algorithm. The USB expansion unit verifies the functionality of the chip's extended USB interface.

[0089] In one alternative implementation, refer to Figure 7 The second functional module 120 can also be equipped with DIP switches and buttons to select the module for secure startup in the security verification unit or to select the encryption algorithm. It can also be used to select the input and output levels of the low-voltage differential signal tunnel protocol interface.

[0090] In one alternative implementation, refer to Figure 7 By using a high-speed serial computer expansion bus standard interface and three communication serial bus devices, three universal serial bus interfaces are expanded. Combined with the existing two universal serial bus controllers' corresponding universal serial bus interfaces, a total of five universal serial bus interfaces are obtained. The type of these five universal serial bus interfaces can be set to type-A or type-C according to actual needs, such as... Figure 7 In the illustrated scheme, the final five Universal Serial Buses include four Type-A interfaces and one Type-C interface. Those skilled in the art will understand that the number of Universal Serial Bus interfaces extended in this embodiment is not limited to the aforementioned three, but may include more or fewer, depending on actual needs.

[0091] In an alternative implementation, the second functional module 120 further includes a network connector, such as... Figure 7As shown, the network connector can be an RJ45 port, which connects to an Ethernet interface to access the Ethernet Media Access Controller. The Ethernet Media Access Controller connects to the second functional module 120 via an Advanced Extensible Interface 124, thereby connecting the network to the server monitoring chip replacement card system. The Ethernet interface can be either a Reduced Media Independent Interface (RMII) or a Reduced Gigabit Media Independent Interface (RGMII), supporting bus interface speeds of 10M and 100M respectively.

[0092] In one optional implementation, the server monitoring chip replacement card system further includes a power supply and a corresponding power supply device, which provide independent power to the system. When using the power supply on the server monitoring chip replacement card system, the system can be debugged and verified independently, achieving chip-level verification. When the server monitoring chip replacement card system is connected to a server, system-wide verification can be achieved.

[0093] The server monitoring chip replacement card system provided by the present invention includes a first functional module and a second functional module. The first and second functional modules are connected via an inter-chip communication interface. The first functional module is used to verify the functionality of the chip's main system. The second functional module is used to verify the functionality of the chip's communication interface. The second functional module includes a first communication verification unit, a second communication verification unit, and multiple types of communication interfaces. The first and second communication verification units share multiple types of communication interfaces. The first communication verification unit is used to verify the functionality of the multiple types of communication interfaces. The second communication verification unit is used to verify the functionality of the low-voltage differential signal tunneling protocol interface. Switching between the first and second communication verification units is achieved via a switch. Thus, the server monitoring chip replacement card system can be compatible with the verification of both serial universal input / output interfaces and low-voltage differential signal tunneling protocol interfaces. Verification can be performed on either the serial universal input / output interface or the low-voltage differential signal tunneling protocol interface according to verification requirements. Furthermore, no additional low-voltage differential signal tunneling protocol interface is required, saving costs.

[0094] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0095] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0096] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0097] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A server monitoring chip replacement card system, characterized in that, The system includes: a first functional module (110) and a second functional module (120); The first functional module (110) and the second functional module (120) are connected through an inter-chip communication interface (130); The first functional module (110) is used to verify the functionality of the chip's main system; The second functional module (120) is used to verify the functionality of the chip's communication interface; The second functional module (120) includes a first communication verification unit (121), a second communication verification unit (122), and multiple types of communication interfaces (123); the first communication verification unit (121) and the second communication verification unit (122) share the multiple types of communication interfaces (123); the first communication verification unit (121) is used to verify the functions of the multiple types of communication interfaces (123); the second communication verification unit (122) is used to verify the functions of the low-voltage differential signal tunneling protocol interface; The switching between the first communication verification unit (121) and the second communication verification unit (122) is performed by a switch; The first functional module (110) includes a processor unit (111), a communication unit (112), and a functional verification unit (113). The processor unit (111), the communication unit (112), and the functional verification unit (113) transmit information through a network interconnection bus (114); The communication interface in the communication unit (112) is connected to the server to establish a connection between the system and the server in order to obtain the monitoring information of the server; The processor unit (111) runs the verification program and processes the monitoring information to obtain verification data; The functional verification unit (113) determines the functional verification status based on the verification data.

2. The server monitoring chip replacement card system according to claim 1, characterized in that, The processor unit (111) consists of a first processor and a second processor; The first processor is used to run the verification program; The second processor is used to process the monitoring information; The first processor and the second processor are respectively connected to the memory controller, and obtain data in the memory through the memory controller, and / or store data in the memory through the memory controller.

3. The server monitoring chip replacement card system according to claim 2, characterized in that, The first processor and the second processor share the memory through a shared memory mechanism; When the shared memory mechanism is interrupted, the second processor interacts with the first processor through the system bus of the first processor.

4. The server monitoring chip replacement card system according to claim 1, characterized in that, The communication unit (112) also includes a secure digital card controller, an embedded multimedia card controller, a secure digital card interface, and an embedded multimedia card; The secure digital card controller is connected to the secure digital card interface, and the secure digital card interface is used to access the secure digital card. The embedded multimedia card controller is connected to the embedded multimedia card; The secure digital card and the embedded multimedia card are used to store the verification program.

5. The server monitoring chip replacement card system according to claim 1, characterized in that, The communication unit (112) also includes a flash memory programmer for programming the verification program.

6. The server monitoring chip replacement card system according to claim 1, characterized in that, The function verification unit (113) includes a reset subunit, a function selection subunit, and a display subunit; The reset subunit is used to reset the processor unit (111) when an abnormality occurs in the processor unit (111). The function selection subunit is used to select the function that needs to be verified. The display subunit is used to display the running position of the verification program.

7. The server monitoring chip replacement card system according to claim 1, characterized in that, The first communication verification unit (121) and the second communication verification unit (122) interact with the first functional module (110) through the advanced extensible interface (124) and the inter-chip communication interface (130), and transmit the interaction information in the multiple types of communication interfaces (123) to the first functional module (110).

8. The server monitoring chip replacement card system according to claim 1, characterized in that, The first communication verification unit (121) includes multiple communication verification subunits (1211); the multiple communication verification subunits (1211) correspond one-to-one with the multiple types of communication interfaces (123), and respectively transmit the interactive information in the corresponding communication interface (123).

9. The server monitoring chip replacement card system according to claim 1, characterized in that, The second communication verification unit (122) obtains multiple types of interaction information from the multiple types of communication interfaces (123), and packages the multiple types of interaction information according to the low-voltage differential signal tunneling protocol to obtain packaged interaction information; the packaged interaction information is parsed back to the multiple types of interaction information in the first functional module (110).

10. The server monitoring chip replacement card system according to claim 1, characterized in that, The second functional module (120) also includes a security verification unit and a universal serial bus expansion unit; The security verification unit and the universal serial bus extension unit interact with the first functional module (110) through the advanced scalable interface (124) and the inter-chip communication interface (130); The security verification unit is used to verify the encryption function of the chip; The Universal Serial Bus (USB) expansion unit is used to verify the functionality of the chip's extended USB interface.

11. The server monitoring chip replacement card system according to any one of claims 1 to 10, characterized in that, The system also includes a power supply and a corresponding power supply device; the power supply and the power supply device are used to provide independent power to the system.

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