Method and system for data synchronization between slow clock domain and fast clock domain

Abstract

The application provides a slow clock domain to fast clock domain data synchronization method and a data synchronization system, which comprises the following steps: S1, sampling the slow clock signal in the first clock cycle to the Mth clock cycle of the fast clock signal in sequence, and recording the first sampling signal to the Mth sampling signal respectively; S2, judging whether the jump edge of the slow clock signal triggers in any clock cycle of the first clock cycle to the Mth clock cycle; if not, synchronizing the slow clock domain data to the fast clock domain in any clock cycle of the first clock cycle to the Mth clock cycle; if yes, further judging the fast clock cycle corresponding to the jump edge triggering, and synchronizing the slow clock domain data to the fast clock domain in the next fast clock cycle. The application does not need to use the data buffer FIFO to synchronize the cross clock domain data signal, greatly shortens the slow clock domain to fast clock domain data synchronization time, saves the resource, improves the data synchronization efficiency and prevents the metastability.

Description

Technical Field

[0001] This invention relates to the field of cross-clock domain data processing, and in particular to a method and system for synchronizing data from a slow clock domain to a fast clock domain. Background Technology

[0002] With the rapid development of the chip industry, there are more and more modules with different clock domains in the same chip. If the data between different clock domains is not synchronized when they interact, the data will become metastable and propagate inside the chip, causing unpredictable damage to the overall chip architecture.

[0003] To address the issue of data synchronization across different clock domains, a data buffer 10 (First Input First Output, FIFO) is commonly used to read and store data across clock domains. The operation of the data buffer 10 is as follows: Figure 1 As shown, the first module 11 outputs a write command W_REQ to the data buffer 10 and outputs the first data signal DATA_A under the first clock CLK_A. The data buffer 10 receives the write command W_REQ and writes the first data signal DATA_A. The second module 12 outputs a read command R_REQ. The data buffer 10 receives the read command from the second module 12 and outputs the internally stored first data signal DATA_A as the second data signal DATA_B to the second module 12. After the above process is completed, the data is transferred from the first module 11 to the second module 12 without the metastability problem caused by direct switching across clock cycles.

[0004] However, when the clock speed difference between the slow and fast clock domains is significant, such as more than 10 times, there will be a large delay when using data buffer 10 to synchronize data between different modules, resulting in low data synchronization efficiency. In addition, data buffer 10 consumes a lot of resources, which is not conducive to further reducing power consumption and resources.

[0005] Based on the above reasons, this invention provides a method for data synchronization from a slow clock domain to a fast clock domain, in order to solve the problems of large latency and low synchronization efficiency when using data buffers from a slow clock domain to a fast clock domain.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method and system for data synchronization from a slow clock domain to a fast clock domain, which solves the problems of large latency and low synchronization efficiency when using data buffers to synchronize data from a slow clock domain to a fast clock domain in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for data synchronization from a slow clock domain to a fast clock domain, comprising:

[0009] S1. The slow clock signal is sampled sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal, and recorded as the first sampling signal to the Mth sampling signal respectively; M is a natural number greater than or equal to 2 and M is less than or equal to the ratio of the period of the slow clock signal to the period of the fast clock signal; wherein, there is at most one transition edge of the slow clock signal in the first clock cycle to the Mth clock cycle.

[0010] S2. Based on the first sampling signal to the Mth sampling signal, determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle; if it is not triggered, synchronize the slow clock domain data to the fast clock domain in any clock cycle from the first clock cycle to the Mth clock cycle; if it is triggered, further determine the fast clock cycle corresponding to the transition edge trigger, and synchronize the slow clock domain data to the fast clock domain in the next fast clock cycle.

[0011] Optionally, the fast clock signal is triggered by either a rising edge or a falling edge.

[0012] Optionally, a pre-synchronization step is set before step S2, including: when M=2, in the first clock cycle, the slow clock domain data is synchronized to the fast clock domain as fast clock domain data; when M=3, in the second clock cycle, the slow clock domain data is synchronized to the fast clock domain as fast clock domain data.

[0013] Optionally, when M=2 and the slow clock signal is triggered by a rising edge, if a falling edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain; if a rising edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data in the third clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously high during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously low during the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained.

[0014] Optionally, in S20a, during the first clock cycle, the slow clock domain data is synchronized to the fast clock domain; in S21a, during the second clock cycle, the level of the sampled first sampling signal is determined; when the first sampling signal is high, the slow clock domain data of the second clock cycle is synchronized to the fast clock domain; when the first sampling signal is low, the fast clock domain data of step S20a is retained; in S22a, during the third clock cycle, the levels of the sampled first sampling signal and the second sampling signal are determined; if the sampled first sampling signal is low and the second sampling signal is high, the slow clock domain data is synchronized to the fast clock domain; if the sampled first sampling signal is low and the second sampling signal is low, the fast clock domain data of step S20a is retained.

[0015] Optionally, when M equals 2 and the slow clock signal is triggered by a falling edge, if a rising edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain; if a falling edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data in the third clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously at a low level during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously at a high level during the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained.

[0016] Optionally, in S20b, during the first clock cycle, the slow clock domain data is synchronized to the fast clock domain; in S21b, during the second clock cycle, the level of the sampled first sampling signal is determined; when the first sampling signal is low, the slow clock domain data of the second clock cycle is synchronized to the fast clock domain; when the first sampling signal is high, the fast clock domain data of step S20b is retained; in S22b, during the third clock cycle, the levels of the sampled first and second sampling signals are determined; if the sampled first sampling signal is high and the second sampling signal is low, the slow clock domain data is synchronized to the fast clock domain; if the sampled first sampling signal is high and the second sampling signal is high, the fast clock domain data of step S20b is retained.

[0017] Optionally, in S20c, during the first clock cycle, a slow clock signal is sampled as a first sample signal; in S21c, during the second clock cycle, a slow clock signal is sampled as a second sample signal; the slow clock domain data is synchronized to the fast clock domain; in S22c, during the third clock cycle, the levels of the sampled first and second sample signals are determined; if the levels of the first and second sample signals are not equal, the slow clock domain data in the third clock cycle is synchronized to the fast clock domain; if the levels of the first and second sample signals are equal, the fast clock domain data in step S21c is retained; in S23c, during the fourth clock cycle, the levels of the sampled first, second, and third sample signals are determined; if the levels of the first and second sample signals are equal and the levels of the second and third sample signals are not equal, the slow clock domain data in the fourth clock cycle is synchronized to the fast clock domain; if the levels of the first, second, and third sample signals are all equal, the fast clock domain data in step S21c is retained.

[0018] Optionally, the period of the slow clock signal is greater than or equal to 10 times the period of the fast clock signal.

[0019] To achieve the above and other related objectives, the present invention provides a slow clock domain to fast clock domain data synchronization system, which includes a fast clock domain module, a slow clock domain module, a clock signal sampling module, and a data synchronization module for implementing the slow clock domain to fast clock domain data synchronization method.

[0020] Fast clock domain module, slow clock domain module, clock signal sampling module, and data synchronization module;

[0021] The clock signal sampling module receives the fast clock signal from the fast clock domain module and the slow clock signal from the slow clock domain module, and samples the slow clock signal sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal.

[0022] The input terminal of the data synchronization module is connected to the output signal of the clock signal sampling module, and is used to determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle, and control the data of the slow clock domain module to be synchronized to the fast clock domain module based on the determination result.

[0023] Optionally, the clock signal sampling module includes a counter and a sampling unit; the counter receives the fast clock signal from the fast clock domain module, and its output is connected to the control terminal of the sampling unit to control the sampling number of the sampling unit; wherein the counting period of the counter is equal to the period of the clock signal of the fast clock domain module; the input terminal of the sampling unit is connected to the clock signal output terminal of the slow clock domain module, and the clock signal of the slow clock domain module is sampled sequentially based on the output signal of the counter and the result is output to the input terminal of the determination unit.

[0024] Optionally, the clock signal sampling module further includes a counting trigger; the input of the counting trigger is connected to the fast clock domain module, and the output is connected to the control terminal of the counter, for providing a counting trigger signal for the counter.

[0025] Optionally, the data synchronization module is configured as a state machine.

[0026] Optionally, the data synchronization module includes a determination unit and a synchronization unit; the input terminal of the determination unit is connected to the output signal of the clock signal sampling module, and is used to determine whether the transition edge of the slow clock signal is triggered within any clock cycle from the first clock cycle to the Mth clock cycle; the control terminal of the synchronization unit is connected to the output signal of the determination unit, the input terminal is connected to the data output terminal of the slow clock domain module, and the output terminal is connected to the data input terminal of the fast clock domain module, and controls the data of the slow clock domain module to be synchronized to the fast clock domain module based on the determination result of the determination unit.

[0027] As described above, the slow-clock-domain to fast-clock-domain data synchronization method and data synchronization system of the present invention have the following beneficial effects:

[0028] 1. The slow-clock-domain to fast-clock-domain data synchronization method and data synchronization system of the present invention do not require the use of a data buffer FIFO for cross-clock-domain data signal synchronization, which greatly shortens the data synchronization time from slow clock domain to fast clock domain, saves resources, improves the efficiency of data synchronization, and prevents metastability.

[0029] 2. The slow-clock-domain to fast-clock-domain data synchronization method and data synchronization system of the present invention have a simple structure and are easy to use. They can achieve cross-clock-domain data synchronization in as little as three fast clock cycles and can be widely promoted and applied in cross-clock-domain application fields. Attached Figure Description

[0030] Figure 1 This is a diagram illustrating how a data cache works.

[0031] Figure 2The diagram illustrates the steps of the slow clock domain to fast clock domain data synchronization method of the present invention.

[0032] Figure 3 The diagram shown is an overall algorithm block diagram of a slow clock domain to fast clock domain data synchronization method according to the present invention.

[0033] Figure 4 Displayed as Figure 3 A schematic diagram of the sampled signal.

[0034] Figure 5 Displayed as Figure 3 A schematic diagram of a data synchronization state machine.

[0035] Figure 6 The diagram shown is a structural schematic of a slow clock domain to fast clock domain data synchronization system according to the present invention.

[0036] Figure 7 Displayed as Figure 3 The waveform diagram of the working process.

[0037] Figure 8 The diagram shows the overall algorithm block diagram of another slow clock domain to fast clock domain data synchronization method of the present invention.

[0038] Figure 9 Displayed as Figure 8 A schematic diagram of the sampled signal.

[0039] Figure 10 Displayed as Figure 8 A schematic diagram of a data synchronization state machine.

[0040] Figure 11 Displayed as Figure 8 The waveform diagram of the working process.

[0041] Component designation explanation

[0042] 10 Data Cache

[0043] 11 Module 1

[0044] 12 Module Two

[0045] 2. Data synchronization system from slow clock domain to fast clock domain

[0046] 21 Fast Clock Domain Module

[0047] 22 Slow Clock Domain Module

[0048] 23 Clock signal sampling module

[0049] 231 Counter

[0050] 232 sampling units

[0051] 233 Counting Flip-Flops

[0052] 24 Data Synchronization Module

[0053] 241 Decision Unit

[0054] 242 Synchronization Unit Detailed Implementation

[0055] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] Please refer to 2~ Figure 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Example 1

[0058] like Figure 2 As shown, this embodiment provides a method for data synchronization from a slow clock domain to a fast clock domain, including:

[0059] S1. Sampling the slow clock signal clk_b sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal clk_a, and recording them as the first sampling signal to the Mth sampling signal respectively; where M is a natural number greater than or equal to 2, meaning that at least two cycles of the slow clock signal clk_b must be sampled to facilitate subsequent determination of the clock cycle of the transition edge of the slow clock signal clk_b. In order to achieve the operation of synchronizing the slow clock domain signal within a few cycles of the fast clock domain, M is less than or equal to the ratio between the period of the slow clock signal clk_b and the period of the fast clock signal clk_a. For example, if the period of the slow clock signal clk_b is 10 times the period of the fast clock signal clk_a, then M can be selected from, but is not limited to, 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0060] Specifically, there is at most one rising or falling edge of the slow clock signal in the first to the Mth clock cycles. This avoids the metastability of the slow clock domain during data synchronization after two rising edges are acquired in the first to the Mth clock cycles. In this embodiment, when M is 2 and the slow clock signal is triggered by a rising edge (single edge), the period of the slow clock signal must be greater than four fast clock signal periods to avoid two rising edges in the first and second clock cycles, which would lead to inaccurate synchronization of the slow clock domain data to the fast clock domain. Preferably, the period of the slow clock signal is greater than or equal to 10 times the period of the fast clock signal. The multiple between the period of the slow clock signal and the fast clock signal can be selected, including but not limited to 15 times, 20 times, and 50 times. In fact, the greater the difference between the period of the slow clock signal and the period of the fast clock signal, the shorter the time taken by the data synchronization method in this embodiment compared to the time taken by the data synchronizer FIFO, and the higher the efficiency of data synchronization.

[0061] Specifically, the fast clock signal clk_a is set to be either rising-edge triggered or falling-edge triggered. In this embodiment, the fast clock signal clk_a is set to be rising-edge triggered, meaning that the slow clock signal is acquired at the moment the rising edge of each cycle of the fast clock signal occurs. Meanwhile, in this embodiment, the slow clock signal clk_b is set to be rising-edge triggered, meaning that data in the slow clock domain is triggered at the rising edge.

[0062] More specifically, such as Figure 3 and Figure 4 As shown, in this embodiment, M is set to 2. The first sample signal `first` of the slow clock signal `clk_b` is sampled starting at the rising edge of the first clock cycle of the fast clock signal `clk_a` (i.e., `cnt` is 1), and the second sample signal `second` of the slow clock signal `clk_b` is sampled starting at the rising edge of the second clock cycle of the fast clock signal `clk_a` (i.e., `cnt` is 2). If the first sample signal `first` is low and the second sample signal `second` is low, the slow clock signal `clk_b` remains low throughout the first and second clock cycles. If the first sample signal `first` is high and the second sample signal `second` is high, the slow clock signal remains high throughout the first and second clock cycles. If the first sample signal `first` is high and the second sample signal `second` is low, the slow clock signal is in a falling edge state throughout the first and second clock cycles. If the first sample signal `first` is low and the second sample signal `second` is high, the slow clock signal is in a rising edge state throughout the first and second clock cycles.

[0063] S2. Based on the first sampling signal to the Mth sampling signal, determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle; if it is not triggered, synchronize the slow clock domain data to the fast clock domain in any clock cycle from the first clock cycle to the Mth clock cycle; if it is triggered, further determine the fast clock cycle corresponding to the transition edge trigger, and synchronize the slow clock domain data to the fast clock domain in the next fast clock cycle.

[0064] Specifically, a pre-synchronization step is set before step S2. In this embodiment (M=2), this includes: synchronizing the slow clock domain data to the fast clock domain data during the first clock cycle. In actual use, the slow clock domain data is temporarily synchronized to the fast clock domain directly through the pre-synchronization step, and then a subsequent judgment is made to determine whether to discard the temporarily stored slow clock domain data. By setting the pre-synchronization step, when the slow clock domain data is synchronized to the fast clock domain data, it can be directly stored through the storage bit corresponding to the fast clock domain without introducing other storage modules. At the same time, since it is directly stored in the fast clock domain without going through other storage modules, the data synchronization efficiency can be further improved. It should be noted that, as another implementation method, a separate synchronization storage module (not shown in the figure) can be set up to collect slow clock domain data values ​​multiple times during the first clock cycle to the Mth clock cycle. By judging the collected clock signals, the period corresponding to the transition edge of the slow clock signal is excluded, and the data collected in other periods is retained. In this embodiment, M is set to 2. Based on the first sampling signal first and the second sampling signal second, it is determined whether the slow clock signal clk_b has changed during these two clock cycles. This ensures that when synchronizing the slow clock domain data to the fast clock domain, data during the metastable time period will not be collected (i.e., the data signal at the changing edge of the slow clock signal will not be collected).

[0065] Specifically, in this embodiment, M=2 and the slow clock signal is triggered by a rising edge (i.e., metastability occurs at the rising edge of the slow clock signal). If a falling edge of the slow clock signal is detected in the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain. If a rising edge of the slow clock signal is detected in the first and second clock cycles of the fast clock signal (i.e., the period when metastability occurs), the slow clock domain data in the third clock cycle is synchronized to the fast clock domain. If the slow clock signal is continuously high in the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle is synchronized to the fast clock domain. If the slow clock signal is continuously low in the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained. It should be noted that, in practice, when the falling edge of the slow clock signal is acquired in the first and second clock cycles of the fast clock signal, or when the signal remains at a high level or a low level, since the rising edge of the slow clock signal is not involved, any clock cycle in the first and second clock cycles can be stored in these three cases, and this embodiment is not the only one that can be used.

[0066] As an example, such as Figure 5 As shown, step S2 includes:

[0067] Step S20a: In the first clock cycle, synchronize the slow clock domain data to the fast clock domain, that is: perform the pre-synchronization step.

[0068] Step S21a: In the second clock cycle, determine the level of the first sampled signal. When the first sampled signal is high (represented by 1 in this embodiment), synchronize the slow clock domain data to the fast clock domain. In this embodiment, the synchronization of slow clock domain data to fast clock domain data is achieved through a D flip-flop. Therefore, the synchronization of slow clock domain data in the second clock cycle to the fast clock domain is not completed directly in the second clock cycle, but only in the third clock cycle of the fast clock signal. That is, the slow clock domain data of the previous clock cycle can only be synchronized to the fast clock domain in the later clock cycle. In other words, in state S1 of this embodiment, if the first sampled signal is high, it is determined that the rising edge trigger of the slow clock signal will not occur in the first and second clock cycles. The slow clock domain data in the second clock cycle is synchronized to the fast clock domain (at this time, the slow clock domain data corresponding to the second clock cycle is synchronized, and the synchronization process is performed in the third clock cycle), thus avoiding the acquisition of slow clock domain data in a metastable state. When the first sampled signal is low, the fast clock domain data from step S20a is retained.

[0069] Step S22a: In the third clock cycle, determine whether the first sampled signal is low and the second sampled signal is high. When the first sampled signal is low (represented by 0 in this embodiment) and the second sampled signal is high, synchronize the slow clock domain data to the fast clock domain. That is, in state S2 of this embodiment, if the first sampled signal is low and the second sampled signal is high, it is determined that the rising edge of the slow clock signal is triggered in the first and second clock cycles, and synchronize the slow clock domain data in the third clock cycle to the fast clock domain (similarly, the synchronization process is completed in the fourth clock cycle). If the first sampled signal is low and the second sampled signal is low, retain the fast clock domain data from step S20a.

[0070] It should be noted that in this embodiment, if the first sampled signal (first) is high (represented by 1), then the rising edge of the slow clock signal is determined to be within the first clock cycle. Alternatively, the acquired clock signal can be inverted before determining the position of the transition edge. For example, if the first sampled signal (first) is high and inverted to "0", then the rising edge of the slow clock signal is determined to be within the first clock cycle.

[0071] like Figure 6 As shown, this embodiment also provides a slow clock domain to fast clock domain data synchronization system 2, including: a fast clock domain module 21, a slow clock domain module 22, a clock signal sampling module 23, and a data synchronization module 24;

[0072] Specifically, the control terminal of the clock signal sampling module 23 is connected to the clock signal output terminal of the fast clock domain module 21, and the input terminal is connected to the clock signal output terminal of the slow clock domain module 22. Based on the first clock cycle to the Mth clock cycle of the fast clock signal in the fast clock domain module 21, the slow clock signal is sampled sequentially and recorded as the first sampling signal to the Mth sampling signal respectively; where M is a natural number greater than or equal to 2.

[0073] As an example, the clock signal sampling module 23 includes a counter 231 and a sampling unit 232. The input terminal of the counter 231 is connected to the clock signal output terminal of the fast clock domain module 21, and the output terminal is connected to the control terminal of the sampling unit 232, used to control the sampling number of the sampling unit 232. The counting period of the counter 231 is equal to the period of the clock signal of the fast clock domain module 21. The fast clock domain module 21 controls the sampling unit 232 to sample the clock signal of the slow clock domain module 22 in each period of the fast clock signal through the counter 231. In this embodiment, the fast clock domain module 21 controls the sampling unit 232 to sample the clock signal of the slow clock domain module 22 at the rising edge of the first clock cycle and the rising edge of the second clock cycle of the fast clock signal, and these are respectively denoted as the first sampling signal "first" and the second sampling signal "second".

[0074] As an example, the input terminal of the sampling unit 232 is connected to the clock signal output terminal of the slow clock domain module 22. Based on the output signal of the counter 231, the sampling unit 232 samples the clock signal of the slow clock domain module 22 and outputs the result to the input terminal of the determination unit 241. After sampling the first sampling signal "first" and the second sampling signal "second", the sampling unit 232 transmits them to the determination unit 241 to facilitate subsequent determination of whether the transition edge of the slow clock signal occurs within the first clock cycle and the second clock cycle.

[0075] In another example, the clock signal sampling module further includes a counting trigger 233; the input of the counting trigger 233 is connected to the fast clock domain module 21, and the output is connected to the control terminal of the counter 231, used to provide a counting trigger signal for the counter 231. The trigger signal start can be provided by the counting trigger. After the trigger signal start ends, the counter starts counting from 0. For each clock cycle of the fast clock signal clk_a, the count of counter 233 increments by 1, that is, the value of cnt increments by 1. In this embodiment, counting stops after the count value reaches 4, and continues counting from 0 again after the next trigger signal start ends. Figure 4 As shown, when the counter 233 counts cnt = 1, 2, and 3, the clock signal of the slow clock domain when cnt = 1 is recorded as the first sampling signal first, and the clock signal of the slow clock domain when cnt = 2 is recorded as the second sampling signal second.

[0076] It should be noted that in this embodiment, the trigger signal start is set to a high-level signal. The counter 231 may have a built-in trigger signal start; the period of the trigger signal start is the same as the clock period of the fast clock domain module 21, and counting begins after the trigger signal start ends. The trigger signal start can also be connected to the control terminal of the counter 231, and the counter can be triggered directly by external input (e.g., manual control), thereby starting the counter 231 to count. Any trigger signal setting that enables the sampling unit 232 to start collecting sampling signals in a preset manner after the trigger signal start ends is within the protection scope of this embodiment.

[0077] Specifically, the input terminal of the data synchronization module 24 is connected to the output signal of the clock signal sampling module 23, and is used to determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle, and control the data of the slow clock domain module 22 to be synchronized to the fast clock domain module 21 based on the determination result.

[0078] More specifically, the data synchronization module 24 includes a determination unit 241 and a synchronization unit 242. The input terminal of the determination unit 241 is connected to the output signal of the clock signal sampling module 23, and is used to determine whether the transition edge (rising edge or falling edge) of the slow clock signal is triggered within any clock cycle from the first clock cycle to the Mth clock cycle. The control terminal of the synchronization unit 242 is connected to the output signal of the determination unit 241, the input terminal is connected to the data output terminal of the slow clock domain module 22, and the output terminal is connected to the data input terminal of the fast clock domain module 21. Based on the determination result of the determination unit 241, the data of the slow clock domain module 22 is controlled to be synchronized to the fast clock domain module 21.

[0079] As an example, the data synchronization module 24 is configured as a state machine, and the specific state machine principle is as follows: Figure 5 As shown. When the count value cnt is 1, the state machine transitions from IDLE to S0; when the count value cnt is 2, the state machine transitions from S0 to S1; when the count value cnt is 3, the state machine transitions from S1 to S2; and when cnt is 4, the state machine transitions from S2 to IDLE.

[0080] As an example, in state S0, the synchronization unit 242 caches the value of data_b from the slow clock domain module 22 once into the stored data data_a in the fast clock domain module 21. Then, it further determines whether the stored data from the slow clock domain module 22 should be retained or discarded. In state S1, if the first sampling signal first is 1, the synchronization unit 242 will cache the value of data_b from the slow clock domain module 22 into the stored data_a from the fast clock domain module 21 to overwrite the previous value. Then, in state S2, if the first sampling signal first is 0 and the second sampling signal second is 1, the synchronization unit 242 will cache the value of data_b from the slow clock domain module 22 into the stored data_a from the fast clock domain module 21 to overwrite the previous value. When the count value cnt becomes 4, the state changes from S2 to IDLE, and a pulse signal done under the fast clock signal clk_a will be generated. done is the synchronization completion flag. When done is high, the value of data_a from the fast clock domain module 21 is the correct value after synchronization.

[0081] The following is combined with Figure 7 The working process of this embodiment will be described, wherein M=2 and the fast clock signal is triggered by the rising edge, and the slow clock signal is triggered by the falling edge. Each rising edge of the fast clock signal is used as a marker time, then the first rising edge time is time t1, the second rising edge time is time t2, and so on, which will not be elaborated here.

[0082] At time t1, the trigger signal start is 0, and the slow clock signal is not sampled. At time t2, the trigger signal start is set to 1, and the trigger signal is activated in the fast clock domain.

[0083] At time t3, the trigger signal start ends, and counter 231 starts counting. The count value increases by 1 from 0 with each rising edge of the fast clock signal.

[0084] At time t4, when the count value cnt equals 1, which is the first clock cycle, the first sampled signal of the slow clock domain module 22 is sampled and denoted as first during this clock cycle. Simultaneously, the state machine is in state S0, and a pre-synchronization is performed at this time, that is, the value of data_b from the slow clock domain module 22 is cached once in the stored data data_a of the fast clock domain module 21 (the slow clock domain data in the first clock cycle is synchronized to the fast clock domain, and the synchronization process is completed in the second clock cycle). In this embodiment, since the rising edge of the slow clock signal does not occur within the first clock cycle, the first sampled signal first = 0 is sampled at this time.

[0085] At time t5, when the count value cnt equals 2, which is the second clock cycle, the second sampled signal of the clock domain module 22 is sampled and denoted as second. The state machine state is S1 at this time. The determination unit 241 determines whether the first sampled signal first equals 1: if the first sampled signal first = 1, it means that the rising edge from the previous clock cycle (i.e., the first clock cycle) to the current clock cycle (i.e., the second clock cycle) is impossible, and the data data_b of the slow clock domain module 22 in the current clock cycle (the second clock cycle) is buffered; if the first sampled signal first = 0, the slow clock signal may have transitioned from the previous clock cycle (i.e., the first clock cycle) to the current clock cycle (i.e., the second clock cycle), requiring further determination of the current clock cycle's level state to determine whether the slow clock cycle's transition edge occurs within the current clock cycle (the second clock cycle), and this determination needs to be made in the next clock cycle. In this embodiment, since the rising edge of the slow clock signal occurs within the second clock cycle, the sampled second signal second = 1 is obtained at this time.

[0086] At time t6, when the count value cnt equals 3, which is the third clock cycle, the state machine is in state S2. The decision unit 241 determines whether the slow clock signal transitioned within the previous clock cycle. Specifically, assuming the first sample signal first equals 0, it determines whether the second sample signal second equals 1. If the second sample signal second = 1, it indicates a transition occurred between the first and second clock cycles, and the data data_b of the slow clock domain module 22 for the current clock cycle (the third clock cycle) is buffered. If the second sample signal second = 0, it indicates that the data remained low from the first to the second clock cycle. Therefore, the data data_b of the slow clock domain module 22 under both the first and second clock cycles is not metastable, and can be temporarily stored in either the first or second clock cycle. However, since the slow clock domain data from the first clock cycle has already been stored, this data can be used directly. In this embodiment, since the second sampling signal second=1 is obtained by sampling, it can be determined in the third clock cycle that the transition edge of the slow clock signal occurs in the first clock cycle and the second clock cycle. At this time, the data data_b of the slow clock domain module 22 of the current clock cycle (the slow clock domain data of the third clock cycle is synchronized to the fast clock domain and executed in the fourth clock cycle) is cached.

[0087] At time t7, when the count value equals 4, which is the fourth clock cycle, the state machine returns to IDLE and generates a pulse signal "done" to indicate that synchronization is complete.

[0088] At time t8, the pulse signal done ends, and the data stored in the fast clock domain module 21 is read.

[0089] As can be seen from the above process, data signal synchronization from the slow clock domain to the fast clock domain can be achieved within three fast clock cycles.

[0090] Example 2

[0091] This embodiment provides a method for synchronizing data from a slow clock domain to a fast clock domain. The method and principle are basically the same as those in Embodiment 1. The difference from Embodiment 1 is that the slow clock signal is triggered by the falling edge (the slow clock domain data becomes metastable at the falling edge of the slow clock signal).

[0092] Specifically, if the rising edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data during the second clock cycle is synchronized to the fast clock domain; if the falling edge of the slow clock signal is acquired during the first and second clock cycles of the fast clock signal, the slow clock domain data during the third clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously at a low level during the first and second clock cycles of the fast clock signal, the slow clock domain data during the second clock cycle is synchronized to the fast clock domain; if the slow clock signal is continuously at a high level during the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained.

[0093] As an example, in step S1, the clock signals corresponding to the falling edge triggering time of the slow clock signal are sampled sequentially during the first clock cycle and the second clock cycle of the fast clock signal, and are respectively denoted as the first sampling signal first and the second sampling signal second.

[0094] Step S20b: In the first clock cycle, synchronize the slow clock domain data to the fast clock domain and perform the pre-synchronization step.

[0095] Step S21b: In the second clock cycle, determine the level of the first sampled signal. When the first sampled signal is low, synchronize the slow clock domain data to the fast clock domain (similarly, the slow clock domain data corresponding to the second clock cycle is synchronized at this time, and the synchronization process is performed in the third clock cycle). When the first sampled signal is high, retain the fast clock domain data from step S20b (that is, the slow clock domain data corresponding to the first clock cycle).

[0096] Step S22b: In the third clock cycle, determine the levels of the first and second sampled signals. If the first sampled signal is high and the second sampled signal is low, determine that the falling edge of the slow clock signal is triggered within either the first or second clock cycle, and synchronize the slow clock domain data of the third clock cycle to the fast clock domain (similarly, the synchronization process is completed in the fourth clock cycle). If the first sampled signal is high and the second sampled signal is low, synchronize the slow clock domain data to the fast clock domain; if the first sampled signal is high and the second sampled signal is high, retain the fast clock domain data from step S20b.

[0097] It should be noted that when M equals 2 and the slow clock signal is triggered by a falling edge, the clock signal collected in this embodiment can be directly inverted and judged by the logic judgment criteria of embodiment one to finally obtain the triggering state of the slow clock signal.

[0098] The slow clock domain to fast clock domain data synchronization system provided in this embodiment is basically the same in structure and principle as that in Embodiment 1, and will not be described in detail here.

[0099] Example 3

[0100] like Figure 8 As shown, this embodiment provides a method for data synchronization from a slow clock domain to a fast clock domain, which is basically the same as Embodiment 1. The difference from Embodiment 1 is that the slow clock signal can be set to dual-edge triggering or single-edge triggering. In this embodiment, dual-edge triggering is used as an example. In fact, since this embodiment only determines the transition edge signal of the slow clock signal without distinguishing whether the transition occurs on a rising edge or a falling edge, this embodiment can also be used for the case of single-edge triggering of the slow clock signal. That is, this embodiment can be used to synchronize both single-edge triggered and dual-edge triggered slow clock domains. At this time, at least three clock cycles of the fast clock signal are required, i.e., when M equals 3.

[0101] Specifically, such as Figure 9 As shown, when M equals 3, in step S1, the clock signals corresponding to the transition edge triggering time of the slow clock signal are sampled sequentially in the first clock cycle, the second clock cycle, and the third clock cycle of the fast clock signal, and are respectively denoted as the first sampling signal first, the second sampling signal second, and the third sampling signal third.

[0102] It should be noted that there is at most one slow clock signal transition edge (rising or falling edge) in the first clock cycle to the Mth clock cycle. This avoids the possibility of acquiring a metastable state in the slow clock domain during data synchronization after acquiring two transition edges in the first to Mth clock cycles. In this embodiment, M is 3 and the slow clock signal is double-edge triggered. The period of the slow clock signal is greater than 6 fast clock signal cycles to avoid two transition edges occurring in the first, second, and third clock cycles, which would lead to inaccurate synchronization of the slow clock domain data to the fast clock domain.

[0103] Specifically, step S2 includes:

[0104] In step S20c, during the first clock cycle, the slow clock signal is sampled as the first sampling signal and recorded as the first sampling signal first;

[0105] Step S21c: In the second clock cycle, the slow clock domain data is synchronized to the fast clock domain, which is to perform a pre-synchronization step. A pre-synchronization step is also set before step S2: When M=3, in the second clock cycle, the slow clock domain data is synchronized to the fast clock domain (similarly, since the slow clock domain data of the previous clock cycle can only be synchronized to the fast clock domain in the next clock cycle, the slow clock domain data corresponding to the second clock cycle is saved at this time, and the synchronization step is performed in the third clock cycle).

[0106] Step S22c: In the third clock cycle, determine whether the levels of the first sampled signal and the second sampled signal are equal. If the levels of the first sampled signal and the second sampled signal are not equal, determine that the transition edge of the slow clock signal is triggered within either the first or second clock cycle, and synchronize the slow clock domain data to the fast clock domain. If the levels of the first sampled signal (first) and the second sampled signal (second) are not equal (in this embodiment, that is, when the first sampled signal (first) is low and the second sampled signal is high, or when the first sampled signal (first) is high and the second sampled signal is low), determine that the transition edge of the slow clock signal is triggered within either the first or second clock cycle, and synchronize the slow clock domain data in the third clock cycle to the fast clock domain (similarly, the synchronization process is performed in the fourth clock cycle). If the levels of the first sampled signal and the second sampled signal are equal, retain the fast clock domain data in step S21c.

[0107] Step S23c: In the fourth clock cycle, determine the levels of the sampled first, second, and third sampling signals. If the level of the sampled first signal (first) is equal to the level of the sampled second signal (second) (i.e., when both the first and second sampling signals are high or low), and the level of the second and third sampling signals (third) are not equal (i.e., when the second sampling signal is low and the third sampling signal is high, or when the second sampling signal is high and the third sampling signal is low), then it is determined that the transition edge of the slow clock signal is triggered within the third clock cycle, and the slow clock domain data in the fourth clock cycle is synchronized to the fast clock domain (the slow clock domain data of the fourth clock cycle is saved, and this synchronization step is performed in the fifth clock cycle). If the levels of the first, second, and third sampling signals are all equal, then the fast clock domain data in step S21c is retained.

[0108] This embodiment also provides a slow clock domain to fast clock domain data synchronization system 2, which is basically the same as the first embodiment, except that the data synchronization module 24 is set differently.

[0109] Specifically, the data synchronization module 24 is configured as a state machine, and the specific state machine settings are as follows: Figure 10 As shown. When the count value cnt is 2, the state machine state changes from IDLE to S0; when the count value cnt is 3, the state machine state changes from S0 to S1; when the count value cnt is 4, the state machine state changes from S1 to S2; when the count value cnt is 5, the state machine state changes from S2 to IDLE.

[0110] As an example, in state S0, the synchronization unit 242 caches the value of data_b from the slow clock domain module 22 once into the stored data_a in the fast clock domain module 21. Then, it further determines whether the stored data from the slow clock domain module 22 should be retained or discarded. In state S1, if the first sampling signal first and the second sampling signal second are not equal, the synchronization unit 242 caches the value of data_b from the slow clock domain module 22 once more into the stored data_a in the fast clock domain module 21 to overwrite the previous value. Then, in state S2, if the first sampling signal (first) and the second sampling signal (second) are equal, and if the second sampling signal (second) and the third sampling signal (third) are not equal, the synchronization unit 242 will cache the value of the data_b of the slow clock domain module 22 into the stored data_a of the fast clock domain module 21 to overwrite the previous value. When the count value cnt becomes 5, the state changes from S2 to IDLE, and a pulse signal done under the fast clock signal clk_a clock domain will be generated. done is the synchronization completion flag. When done is high, the value of the data_a of the fast clock domain module 21 is the correct value after synchronization.

[0111] The following is combined with Figure 11 The working process of this embodiment will be explained. In this embodiment, M=3 and the slow clock signal is triggered by two edges. Each rising edge of the fast clock signal is used as a marked time. The first rising edge time is time t1', the second rising edge time is time t2', and so on. It will not be described in detail here.

[0112] At time t1', the trigger signal start is 0, and the slow clock signal is not sampled. At time t2', the trigger signal start is 1, and the trigger signal is activated in the fast clock domain.

[0113] At time t3', the trigger signal start ends, and counter 231 starts counting. The count value increases by 1 from 0 with each rising edge of the fast clock signal.

[0114] At time t4', when the count value cnt equals 1, which is the first clock cycle, the first sampled signal of the slow clock domain module 22 is obtained during this clock cycle and denoted as first. In this embodiment, since the rising edge of the slow clock signal does not occur within the first clock cycle, the sampled first signal first = 0 is obtained at this time.

[0115] At time t5', when the count value cnt equals 2, which is the second clock cycle, the third sampled signal of clock domain module 22 is obtained during this clock cycle and denoted as second. Simultaneously, the state machine is in state S0. At this time, a pre-synchronization is performed; that is, at this moment, the value of data_b from the slow clock domain module 22 corresponding to the second clock cycle is cached once into the stored data data_a of the fast clock domain module 21 (similarly, this step is synchronized during the third clock cycle). In this embodiment, since the rising edge of the slow clock signal occurs within the second clock cycle, the second sampled signal second = 1 is sampled at this time.

[0116] At time t6', when the count value cnt equals 3, which is the third clock cycle, the third sampled signal of the clock domain module 22 is obtained in this clock cycle and denoted as third. At this time, the state machine is in state S1. The determination unit 241 determines whether the slow clock signal has changed during either the first clock cycle or the second clock cycle, that is, whether the first sample signal first is equal to the second sample signal second. If the first sample signal first is not equal to the second sample signal second, it means that the change edge of the slow clock domain occurred during either the first clock cycle or the second clock cycle. In this case, the data data_b of the slow clock domain module 22 cached during the second clock cycle may be metastable and needs to be discarded. At this time, the data data_b of the slow clock domain module 22 cached during the current clock cycle (the third clock cycle) overwrites the data temporarily stored last time (similarly, a synchronization step is performed in the fourth clock cycle to retain the slow clock domain data corresponding to the third clock cycle). If the first sample signal first is equal to the second sample signal second, it means that the change edge of the slow clock domain did not occur during either the first clock cycle or the second clock cycle. In this case, the data data_b of the slow clock domain module 22 in the previous clock cycle is not metastable and can be temporarily stored. In this embodiment, since the first sampling signal first = 0 and the second sampling signal second = 1, it is determined that the two are not equal. Therefore, the data stored in the previous clock cycle is discarded, and the data data_b of the slow clock domain module 22 corresponding to the current clock cycle (i.e., the third clock cycle) is cached. At this time, the third sampling signal third = 0.

[0117] At time t7', when the count value cnt equals 4, which is the fourth clock cycle, the state machine is in state S2. The decision unit 241 determines whether a transition occurred in the third clock cycle, provided that the slow clock signal did not change in either the first or second clock cycle. In other words, it determines whether the first two sampled signals, first and second, are equal to the third sampled signal, third. In this embodiment, under the premise that the first sampling signal first and the second sampling signal second are equal, it can be determined whether the second sampling signal second is equal to the third sampling signal third, thereby determining whether a change has occurred in the third clock cycle: If, under the premise that the first sampling signal first and the second sampling signal second are equal, the second sampling signal second is not equal to the third sampling signal third, then the slow clock signal has changed in the third clock cycle. At this time, the data_b of the slow clock domain module 22 in the current clock cycle (the fourth clock cycle) overwrites the previously temporarily stored data (saves the slow clock domain data corresponding to the fourth clock cycle, and performs this saving step in the fifth clock cycle); if, under the premise that the first sampling signal first and the second sampling signal second are equal, the second sampling signal second is equal to the third sampling signal third, then the data_b of the slow clock domain module 22 in the first clock cycle, the second clock cycle, and the third clock cycle are not metastable, and any clock cycle of the first clock cycle, the second clock cycle, and the third clock cycle can be temporarily stored. However, since the slow clock domain data corresponding to the second clock cycle has already been stored once, the data can be used directly.

[0118] At time t8', when the count value equals 5, which is the fifth clock cycle, the state machine returns to IDLE and generates a pulse signal "done" to indicate that synchronization is complete.

[0119] At time t9', the pulse signal done ends, and the data stored in the fast clock domain module 21 is read.

[0120] As can be seen from the above process, data signal synchronization from the slow clock domain to the fast clock domain can be achieved within four fast clock cycles.

[0121] In summary, this invention provides a method and system for synchronizing data from a slow clock domain to a fast clock domain, comprising: S1, sequentially sampling the slow clock signal during the first to Mth clock cycles of the fast clock signal, and denoting them as the first sampling signal to the Mth sampling signal, respectively; S2, determining whether a transition edge of the slow clock signal is triggered within any clock cycle from the first to the Mth clock cycle; if no trigger occurs, synchronizing the slow clock domain data to the fast clock domain during any clock cycle from the first to the Mth clock cycle; if a trigger occurs, further determining the fast clock cycle corresponding to the transition edge trigger, and synchronizing the slow clock domain data to the fast clock domain in the next fast clock cycle. This invention eliminates the need for a FIFO data buffer for cross-clock domain data signal synchronization, significantly shortening the data synchronization time from the slow clock domain to the fast clock domain, saving resources, improving data synchronization efficiency, and preventing metastability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for data synchronization from a slow clock domain to a fast clock domain, characterized in that, The slow clock domain to fast clock domain data synchronization method includes at least the following: S1. The slow clock signal is sampled sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal, and recorded as the first sampling signal to the Mth sampling signal respectively; M is a natural number greater than or equal to 2 and M is less than or equal to the ratio of the period of the slow clock signal to the period of the fast clock signal; wherein, there is at most one transition edge of the slow clock signal in the first clock cycle to the Mth clock cycle. S2. Based on the first sampling signal to the Mth sampling signal, determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle; if it is not triggered, synchronize the slow clock domain data to the fast clock domain in any clock cycle from the first clock cycle to the Mth clock cycle; if it is triggered, further determine the fast clock cycle corresponding to the transition edge trigger, and synchronize the slow clock domain data to the fast clock domain in the next fast clock cycle.

2. The method for data synchronization from slow clock domain to fast clock domain according to claim 1, characterized in that: The fast clock signal is triggered by either the rising edge or the falling edge.

3. The method for data synchronization from slow clock domain to fast clock domain according to claim 1, characterized in that: A pre-synchronization step is set before step S2, including: when M=2, in the first clock cycle, the slow clock domain data is synchronized to the fast clock domain as fast clock domain data; when M=3, in the second clock cycle, the slow clock domain data is synchronized to the fast clock domain as fast clock domain data.

4. The method for data synchronization from slow clock domain to fast clock domain according to claim 3, characterized in that: When M=2 and the slow clock signal is triggered by a rising edge. If the falling edge of the slow clock signal is acquired in the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle will be synchronized to the fast clock domain. If the rising edge of the slow clock signal is acquired in the first and second clock cycles of the fast clock signal, the slow clock domain data in the third clock cycle will be synchronized to the fast clock domain. If a slow clock signal is continuously at a high level during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle will be synchronized to the fast clock domain. If a slow clock signal is continuously at a low level during the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained.

5. The method for data synchronization from slow clock domain to fast clock domain according to claim 4, characterized in that: S20a: In the first clock cycle, synchronize the slow clock domain data to the fast clock domain; S21a. In the second clock cycle, determine the level of the first sampled signal obtained by sampling; when the first sampled signal is high, synchronize the slow clock domain data of the second clock cycle to the fast clock domain; when the first sampled signal is low, retain the fast clock domain data of step S20a. S22a. In the third clock cycle, determine the levels of the first sampled signal and the second sampled signal obtained by sampling; if the first sampled signal obtained by sampling is low and the second sampled signal is high, then synchronize the slow clock domain data to the fast clock domain; if the first sampled signal obtained by sampling is low and the second sampled signal is low, then retain the fast clock domain data of step S20a.

6. The method for data synchronization from slow clock domain to fast clock domain according to claim 3, characterized in that: When M equals 2 and the slow clock signal is triggered by a falling edge. If the rising edge of the slow clock signal is acquired in the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle will be synchronized to the fast clock domain. If the falling edge of the slow clock signal is acquired in the first and second clock cycles of the fast clock signal, the slow clock domain data in the third clock cycle will be synchronized to the fast clock domain. If a slow clock signal is continuously at a low level during the first and second clock cycles of the fast clock signal, the slow clock domain data in the second clock cycle will be synchronized to the fast clock domain. If a slow clock signal is continuously at a high level during the first and second clock cycles of the fast clock signal, the fast clock domain data from the pre-synchronization step is retained.

7. The method for data synchronization from slow clock domain to fast clock domain according to claim 6, characterized in that: S20b: In the first clock cycle, synchronize the slow clock domain data to the fast clock domain; S21b: In the second clock cycle, determine the level of the first sampled signal obtained by sampling; when the first sampled signal is low, synchronize the slow clock domain data of the second clock cycle to the fast clock domain; when the first sampled signal is high, retain the fast clock domain data of step S20b. S22b: In the third clock cycle, determine whether the levels of the first and second sampled signals have been sampled; if the first sampled signal is high and the second sampled signal is low, then synchronize the slow clock domain data to the fast clock domain; if the first sampled signal is high and the second sampled signal is high, then retain the fast clock domain data from step S20b.

8. The method for data synchronization from slow clock domain to fast clock domain according to claim 3, characterized in that: When M equals 3 S20c, in the first clock cycle, samples the slow clock signal as the first sampling signal; S21c, In the second clock cycle, the slow clock signal is sampled as the second sampling signal; Synchronize data from the slow clock domain to the fast clock domain; S22c. In the third clock cycle, determine the levels of the first sampled signal and the second sampled signal obtained by sampling; if the levels of the first sampled signal and the second sampled signal are not equal, then synchronize the slow clock domain data in the third clock cycle to the fast clock domain. If the level of the first sampling signal and the level of the second sampling signal are equal, then the fast clock domain data in step S21c is retained; S23c. In the fourth clock cycle, determine the levels of the first sampled signal, the second sampled signal, and the third sampled signal; if the levels of the first sampled signal and the second sampled signal are equal and the levels of the second sampled signal and the third sampled signal are not equal, then synchronize the slow clock domain data in the fourth clock cycle to the fast clock domain. If the levels of the first sampled signal, the second sampled signal, and the third sampled signal are all equal, then the fast clock domain data in step S21c is retained.

9. The method for data synchronization from slow clock domain to fast clock domain according to any one of claims 1 to 8, characterized in that: The period of the slow clock signal is greater than or equal to 10 times the period of the fast clock signal.

10. A slow clock domain to fast clock domain data synchronization system, used to implement the slow clock domain to fast clock domain data synchronization method as described in any one of claims 1 to 9, characterized in that, The slow clock domain to fast clock domain data synchronization system includes at least: a fast clock domain module, a slow clock domain module, a clock signal sampling module, and a data synchronization module; The clock signal sampling module receives the fast clock signal from the fast clock domain module and the slow clock signal from the slow clock domain module, and samples the slow clock signal sequentially from the first clock cycle to the Mth clock cycle of the fast clock signal. The input terminal of the data synchronization module is connected to the output signal of the clock signal sampling module, and is used to determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle, and control the data of the slow clock domain module to be synchronized to the fast clock domain module based on the determination result.

11. The slow-clock-domain to fast-clock-domain data synchronization system according to claim 10, characterized in that: The data synchronization module is configured as a state machine.

12. The slow-clock-domain to fast-clock-domain data synchronization system according to claim 10 or 11, characterized in that: The data synchronization module includes a determination unit and a synchronization unit; The input terminal of the determination unit is connected to the output signal of the clock signal sampling module, and is used to determine whether the transition edge of the slow clock signal is triggered in any clock cycle from the first clock cycle to the Mth clock cycle. The control terminal of the synchronization unit is connected to the output signal of the determination unit, the input terminal is connected to the data output terminal of the slow clock domain module, and the output terminal is connected to the data input terminal of the fast clock domain module. Based on the determination result of the determination unit, the data of the slow clock domain module is controlled to be synchronized to the fast clock domain module.

13. The slow-clock-domain to fast-clock-domain data synchronization system according to claim 12, characterized in that: The clock signal sampling module includes a counter and a sampling unit; The counter receives the fast clock signal from the fast clock domain module, and its output is connected to the control terminal of the sampling unit to control the sampling number of the sampling unit; wherein the counting period of the counter is equal to the period of the clock signal of the fast clock domain module. The input terminal of the sampling unit is connected to the clock signal output terminal of the slow clock domain module. Based on the output signal of the counter, the clock signal of the slow clock domain module is sampled sequentially and the result is output to the input terminal of the determination unit.

14. The slow-clock-domain to fast-clock-domain data synchronization system according to claim 13, characterized in that: The clock signal sampling module also includes a counter trigger; The input of the counting trigger is connected to the fast clock domain module, and the output is connected to the control terminal of the counter, which is used to provide a counting trigger signal for the counter.

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