A method, system, device, and medium for verilog multi-instance interconnection

Abstract

Embodiments of the present application provide a verilog multi-instance interconnection method, system, device and medium to solve the technical problem that the existing front-end design automation tool cannot realize automatic interconnection between multiple instances. It includes: generating interface description files and registries between multiple instances; generating a blank interface interconnection table based on the interface description files and the registries; filling and updating the blank interface interconnection table; parsing the updated blank interface interconnection table to obtain the interface interconnection relationship between the multiple instances and the top layer; generating a verilog integrated top layer based on the interface interconnection relationship and executing instance interconnection. This greatly improves the speed of multi-instance interconnection integration, frees the design integration personnel from tedious port interconnection and connection declaration; in addition, due to the existence of the self-checking function, the accuracy of multi-instance interconnection integration is also guaranteed; finally, since the interface interconnection table that needs to be edited by humans is relatively simple, the structure modification of the integrated top layer also becomes easier.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, system, device and medium for interconnecting multiple Verilog instances. Background Technology

[0002] Digital circuit design utilizes a hierarchical modeling design concept. The Verilog hardware language uses modules to represent a basic functional block. Modules are called by higher-level modules through ports, and multiple instances of lower-level modules can be interconnected using wires within higher-level modules.

[0003] As design complexity increases, the number of ports in low-level modules increases, and the number of interconnected instances also increases, making interconnection work cumbersome. This creates a demand for interconnection automation. As the design of low-level modules pays more attention to versatility, their port types also become more universal and standardized. For example, up to 38 ports can be standardized into a single AMBA AXI4 interface, which provides the conditions for interconnection automation.

[0004] The most common IC front-end design automation tool is Verilog Mode, but it can only automatically declare, automatically populate the sensitive list and automatically instantiate, but it cannot automatically interconnect multiple instances. Summary of the Invention

[0005] This application provides a method, system, device, and medium for interconnecting multiple Verilog instances, in order to solve the technical problem that existing front-end design automation tools cannot achieve automatic interconnection between multiple instances.

[0006] The purpose of this application is primarily to provide users with an empty interface interconnection table, expand the interface interconnection relationships described by users in the table into port interconnection relationships between instances, and generate top-level ports, connection declarations, and other content that may appear at the integration top level.

[0007] On one hand, embodiments of this application provide a method for interconnecting multiple Verilog instances. The method includes: generating an interface description file and a registry between several instances; generating a blank interface interconnection table based on the interface description file and the registry; filling and updating the blank interface interconnection table; parsing the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; generating a Verilog integration top layer based on the interface interconnection relationship, and performing instance interconnection.

[0008] In one implementation of this application, the interface description file is used to describe the interface information of each instantiated module. The interface information includes: the module interface contained in the module, the type of the module interface, the direction of the module interface, the port type of the module interface, the port direction, and the upper and lower limits of the vector.

[0009] In one implementation of this application, the interface information is saved as a JSON file.

[0010] In one implementation of this application, the step of filling and updating the blank interface interconnect table specifically includes: finding a first target interconnect position for a specified output port based on the interconnect program; and filling the first target interconnect position into the blank interface interconnect table.

[0011] In one implementation of this application, the method further includes: obtaining a second target interconnect location for the specified output port; updating the second target interconnect location to the blank interface interconnect table to replace the first target interconnect location. After the interface interconnect table is populated and updated, the interconnect program analyzes and understands the file to obtain the interface interconnection relationships between instances and between instances and the top layer; simultaneously, due to the existence of the complete module interface description file, the interconnect program can expand the interface into multiple ports, thus obtaining the port interconnection relationships between instances and between instances and the top layer.

[0012] In one implementation of this application, before generating the Verilog integration top layer based on the interface interconnection relationship, the method further includes: generating connections based on the interface interconnection relationship; checking whether the directions and bit widths of both sides of the connection match; and integrating the top-level ports to be connected to all instances.

[0013] In one implementation of this application, after parsing the updated blank interface interconnection table to obtain the interface interconnection relationship between the plurality of instances and the top layer, the method further includes: expanding the interface of each instance into multiple ports based on the interconnection program to obtain the port interconnection relationship between the plurality of instances.

[0014] This application also provides a Verilog multi-instance interconnection system, the system comprising: a file generation unit for generating interface description files and a registry between several instances; and generating a blank interface interconnection table based on the interface description files and the registry; an update unit for filling and updating the blank interface interconnection table; a parsing unit for parsing the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; and an execution unit for generating a Verilog integration top layer based on the interface interconnection relationship and performing instance interconnection.

[0015] This application also provides a Verilog multi-instance interconnection device, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to: generate an interface description file and a registry between several instances; generate a blank interface interconnection table based on the interface description file and the registry; populate and update the blank interface interconnection table; parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; generate a Verilog integration top layer based on the interface interconnection relationship, and perform instance interconnection.

[0016] This application also provides a non-volatile computer storage medium for Verilog multi-instance interconnection, storing computer-executable instructions. The computer-executable instructions are configured to: generate an interface description file and a registry between several instances; generate a blank interface interconnection table based on the interface description file and the registry; populate and update the blank interface interconnection table; parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; generate a Verilog integration top layer based on the interface interconnection relationship, and perform instance interconnection.

[0017] This application provides a method, system, device, and medium for interconnecting multiple Verilog instances, which automatically expands user-specified interface interconnection information between multiple instances into port interconnections and generates a complete Verilog top-level structure. A program written using this method first provides the user with an empty multi-instance interface interconnection table, which the user then fills in. The interconnection program parses the user-filled interface interconnection table and translates it into a complete Verilog integration top-level structure. This method offers the following advantages:

[0018] (1) First, it can greatly improve the speed of multi-instance interconnection and integration, freeing designers and integrators from tedious port interconnection and wiring declarations.

[0019] (2) Secondly, due to the existence of the self-test function, the accuracy of multi-instance interconnection and integration is also guaranteed.

[0020] (3) Finally, since the interface interconnection table that requires manual editing is relatively simple, it is easier to integrate the top-level structure modification. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0022] Figure 1 A flowchart illustrating a method for interconnecting multiple Verilog instances, provided in an embodiment of this application;

[0023] Figure 2 A system composition diagram of Verilog multi-instance interconnection provided in the embodiments of this application;

[0024] Figure 3 This is a schematic diagram of a Verilog multi-instance interconnection device provided in an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Digital circuit design utilizes a hierarchical modeling design concept. The Verilog hardware language uses modules to represent a basic functional block. Modules are called by higher-level modules through ports, and multiple instances of lower-level modules can be interconnected using wires within higher-level modules.

[0027] As design complexity increases, the number of ports in low-level modules increases, and the number of interconnected instances also increases, making interconnection work cumbersome. This creates a demand for interconnection automation. As the design of low-level modules pays more attention to versatility, their port types also become more universal and standardized. For example, up to 38 ports can be standardized into a single AMBA AXI4 interface, which provides the conditions for interconnection automation.

[0028] The most common IC front-end design automation tool is Verilog Mode, but it can only automatically declare, automatically populate the sensitive list and automatically instantiate, but it cannot automatically interconnect multiple instances.

[0029] This application provides a method for automatically expanding user-specified interface interconnection information between multiple instances into port interconnections and generating a complete Verilog top-level structure. A program written using this method first provides the user with an empty multi-instance interface interconnection table, which the user then fills in. The interconnection program parses the user-filled interface interconnection table and translates it into a complete Verilog integration top-level structure.

[0030] The purpose of this application is primarily to provide users with an empty interface interconnection table, expanding the interface interconnection relationships described by the user in the table into port interconnection relationships between instances, and simultaneously generating top-level ports and connection declarations, which may appear at the integration top level. The technical solutions proposed in the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This document provides a flowchart of a method for interconnecting multiple Verilog instances, as illustrated in an embodiment of this application. Figure 1 As shown, the method mainly includes the following steps:

[0032] Step 101: Generate interface description files and registry entries between several instances.

[0033] In the implementation of this application, the interface description file and registry of each instance specified by the user must first be generated. The interface description file is mainly used to describe the interface information of each instantiated module. The interface information includes: the module interface contained in the module, the type of the module interface, the direction of the module interface, the port type of the module interface, the port direction and the upper and lower limits of the vector.

[0034] In this implementation, the interface information is saved as a JSON file. The descriptions of the interface information for each instantiated module can also be saved using other file formats. Since JSON is compressed, consumes little bandwidth, and is easy to parse, this embodiment chooses to save the information in JSON format.

[0035] In this implementation, the registry is used to describe the total number of instances of the integrated top-level module and which modules these instances are instantiated from.

[0036] Step 102: Generate a blank interface interconnection table based on the interface description file and the registry.

[0037] In this implementation, the interconnect program uses the complete module interface description file and the integrated instance registry provided to generate a blank interface interconnect table.

[0038] In this implementation, the interface interconnection table is not in the traditional tabular form, but rather in the form of a "socket-connection" text paragraph, as shown in the table below.

[0039]

[0040] Table 1 Blank Interface Interconnection Table

[0041] In the interface interconnection table, each instance is represented as such a text paragraph. The beginning of the paragraph is the module name, instantiation name and short name of the instance, and the body of the paragraph consists of multiple "socket-connection" lines, each line consisting of (1) the location of the instance's own interface or port, (2) the direction of the interface or port, and (3) the target interconnection location to be connected.

[0042] The target interconnect location in the "Socket-Connection" row can be an interconnect location on a specific instance, an interface or port at the top level of integration, or a forced string. These can all be marked with special symbols when filling in the target location so that the interconnect table processor can recognize it. The table below shows the filled-in interface connection table.

[0043]

[0044] Table 2 Filled Interface Interconnection Table

[0045] Step 103: Fill and update the blank interface interconnection table.

[0046] In this application, filling and updating the blank interface interconnect table specifically includes: first, finding the first target interconnect position of the specified output port based on the interconnect program; then, filling the first target interconnect position into the blank interface interconnect table.

[0047] Furthermore, updating the blank interface interconnect table specifically includes: first, obtaining the second target interconnect position of the specified output port; then, updating the second target interconnect position into the blank interface interconnect table to replace the first target interconnect position.

[0048] It should be noted that during top-level integration, the unit used for interconnection can be an instance's interface, port, or a portion of the port's bits. Combining the position indices at each level in a certain form to precisely express the position of the interconnection unit is called the interconnection position. For example, connecting the position indices with dots is called a position chain, where inst1.intf3.port4[3:0] represents bits 0 to 3 of instance inst1, interface Intf3, and port4.

[0049] Specifically, at this stage, the interconnection program can also provide interconnection assistance. Input and output ports are mutually target interconnection locations. When the user specifies a target interconnection location B (an input port) for an output port A, the program can automatically find the target input port B and use the current output port A as the target interconnection location for the target input port B. For example, if the user edits Inst1.Intf2.out3>>(Inst5.Intf2.in3), the program will automatically edit Inst5.Intf2.in3<<(Inst1.Intf2.out3). On the other hand, when the user specifies a target interconnection location A (an output port) for an input port B, since there is a possibility that one output drives multiple input ports, the interconnection status of the output ports cannot be reversed based on the interconnection status of the input ports.

[0050] Step 104: Parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer.

[0051] In this application implementation, the interconnection program parses the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer.

[0052] Furthermore, based on the interconnection procedure, the interface of each instance is expanded into multiple ports to obtain the port interconnection relationship between the instances.

[0053] Specifically, after the interface interconnection table is populated and updated, the interconnection program analyzes and understands the file to obtain the interface interconnection relationships between each instance and between the instance and the top layer. At the same time, due to the existence of the complete module interface description file, the interconnection program can expand the interface into multiple ports, thus obtaining the port interconnection relationships between each instance and between the instance and the top layer.

[0054] Step 105: Based on the interface interconnection relationship, generate the Verilog integration top layer and perform instance interconnection.

[0055] In this application, the process before generating the Verilog integration top layer is as follows: First, based on the interface interconnection relationship, a connection is generated; then, the direction and bit width of the specified output ports and target interconnection positions of both sides of the connection are checked to see if they match; finally, the top-level ports to be connected to all instances are integrated.

[0056] Furthermore, everything required for the integrated top-level Verilog is prepared, formatted and written to a file, and then the interconnection can be performed.

[0057] This application provides a method for interconnecting multiple Verilog instances. It offers users an empty interface interconnection table, expanding the interface interconnection relationships described in the table into port interconnection relationships between instances. Simultaneously, it generates top-level ports and connection declarations, which may appear at the integration top level. This semi-automatic interconnection method significantly improves the speed of multi-instance interconnection integration, freeing integrators from tedious port interconnection and connection declaration tasks. Furthermore, the self-checking function ensures the accuracy of multi-instance interconnection integration. Finally, the relatively simple interface interconnection table, which previously required manual editing, makes modifying the integration top-level structure easier.

[0058] The above describes a method for interconnecting multiple Verilog instances according to embodiments of this application. Based on the same inventive concept, embodiments of this application also provide a system for interconnecting multiple Verilog instances. The main purpose of the system for interconnecting multiple Verilog instances in this application is to provide users with an empty interface interconnection table, expand the interface interconnection relationships described by users in the table into port interconnection relationships between instances, and generate top-level ports, connection declarations, and other content that may appear at the integration top level.

[0059] Figure 2 A system composition diagram of Verilog multi-instance interconnection provided for embodiments of this application is shown below. Figure 2 As shown, the system mainly includes: a file generation unit 201, used to generate interface description files and a registry between several instances; and to generate a blank interface interconnection table based on the interface description files and the registry; an update unit 202, used to fill and update the blank interface interconnection table; a parsing unit 203, used to parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; and an execution unit 204, used to generate a Verilog integration top layer based on the interface interconnection relationship and execute instance interconnection.

[0060] In this application implementation, the file generation unit 201 is specifically used to perform the following: using the provided complete module interface description file and the integration instance registry, the interconnect program uses this information to generate a blank interface interconnect table.

[0061] In this implementation, the update unit 202 is specifically used to perform the following: finding the first target interconnect location of the specified output port based on the interconnect procedure. Then, the first target interconnect location is filled into the blank interface interconnect table.

[0062] The update unit 202 is further configured to: obtain the second target interconnect location of the specified output port; and then update the second target interconnect location into the blank interface interconnect table to replace the first target interconnect location.

[0063] In this implementation, the parsing unit 203 is specifically used to: parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the plurality of instances and the top layer. The parsing unit 203 is also used to: expand the interface of each instance into multiple ports based on the interconnection procedure to obtain the port interconnection relationship between the plurality of instances.

[0064] While parsing and understanding the interface interconnection table file, and obtaining the interface interconnection relationships between each instance and between the instance and the top layer, the parsing unit 203, due to the existence of the complete module interface description file, can expand the interface into multiple ports, thus obtaining the port interconnection relationships between each instance and between the instance and the top layer.

[0065] In this implementation, the execution unit 204 is further configured to: generate connections based on the interface interconnection relationship; then check whether the direction and bit width of the specified output ports and target interconnection positions of both sides of the connection match; finally, integrate the top-level ports to be connected for all instances, format and write them to a file, and then perform the interconnection.

[0066] This application provides a Verilog multi-instance interconnection system that offers users an empty interface interconnection table. The user-described interface interconnection relationships in the table are then expanded into port interconnection relationships between instances. Simultaneously, top-level ports and connection declarations, which may appear at the integration top level, are generated. This semi-automatic interconnection method significantly improves the speed of multi-instance interconnection integration, freeing integrators from tedious port interconnection and connection declaration tasks. Furthermore, the self-checking function ensures the accuracy of multi-instance interconnection integration. Finally, the relatively simple interface interconnection table, which previously required manual editing, makes modifications to the integration top-level structure easier.

[0067] The above describes a Verilog multi-instance interconnection system provided by embodiments of this application. Based on the same inventive concept, embodiments of this application also provide a Verilog multi-instance interconnection device. Figure 3 A schematic diagram of a Verilog multi-instance interconnection device is provided for an embodiment of this application, as shown below. Figure 3As shown, the device mainly includes: at least one processor 301; and a memory 302 communicatively connected to the at least one processor; wherein the memory 302 stores instructions executable by the at least one processor 301, which, when executed by the at least one processor 301, enable the at least one processor 301 to: generate an interface description file and a registry between several instances; generate a blank interface interconnection table based on the interface description file and the registry; populate and update the blank interface interconnection table; parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; and generate a Verilog integration top layer based on the interface interconnection relationship and perform instance interconnection.

[0068] In addition, this application embodiment also provides a non-volatile computer storage medium for Verilog multi-instance interconnection, storing computer-executable instructions, wherein the computer-executable instructions are configured to: generate an interface description file and a registry between several instances; generate a blank interface interconnection table based on the interface description file and the registry; populate and update the blank interface interconnection table; parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; generate a Verilog integration top layer based on the interface interconnection relationship, and perform instance interconnection.

[0069] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0070] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0071] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0072] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0073] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0074] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0075] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method of verilog multi-instance interconnection, characterized in that, The method includes: Generate an interface description file and a registry for several instances; the interface description file is used to describe the interface information of each instantiated module, and the interface information includes: the module interface contained in the module, the type of the module interface, the direction of the module interface, the port type of the module interface, the port direction and the upper and lower limits of the vector. Based on the interface description file and the registry, a blank interface interconnection table is generated; The blank interface interconnect table is populated and updated; specifically, this includes: finding a first target interconnect position for a specified output port based on the interconnect program; filling the first target interconnect position into the blank interface interconnect table; obtaining a second target interconnect position for the specified output port; and updating the second target interconnect position into the blank interface interconnect table to replace the first target interconnect position. Parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; Based on the interface interconnection relationship, a Verilog integration top-level is generated, and instance interconnection is performed.

2. The method of claim 1, wherein, The interface information is saved in a JSON format file.

3. The method of claim 1, wherein, Before generating the Verilog integration top layer based on the interface interconnection relationship and performing instance interconnection, the method further includes: Based on the aforementioned interface interconnection relationship, connections are generated; Check if the direction and bit width of the two connected components match; Unify the top-level port that all instances need to connect to.

4. The method for interconnecting multiple Verilog instances according to claim 1, characterized in that, After parsing and updating the blank interface interconnection table to obtain the interface interconnection relationships between the plurality of instances and the top layer, the method further includes: The interconnection process expands the interface of each instance into multiple ports to obtain the port interconnection relationship between the instances.

5. A Verilog multi-instance interconnection system, employing the Verilog multi-instance interconnection method of claim 1, characterized in that, The system includes: The file generation unit is used to generate interface description files and registry entries between several instances; and to generate a blank interface interconnection table based on the interface description files and the registry entries. An update unit is used to fill and update the blank interface interconnection table; The parsing unit is used to parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the plurality of instances and the top layer. An execution unit is used to generate a Verilog integration top layer based on the interface interconnection relationship and to perform instance interconnection.

6. A Verilog multi-instance interconnection device, employing the Verilog multi-instance interconnection method of claim 1, characterized in that, The device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enable the at least one processor to: Generate interface description files and a registry for several instances; Based on the interface description file and the registry, a blank interface interconnection table is generated; The blank interface interconnection table is populated and updated; Parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; Based on the interface interconnection relationship, a Verilog integration top-level is generated, and instance interconnection is performed.

7. A non-volatile computer storage medium for Verilog multi-instance interconnection, employing the Verilog multi-instance interconnection method of claim 1, storing computer-executable instructions, characterized in that, The computer-executable instructions are set as follows: Generate interface description files and a registry for several instances; Based on the interface description file and the registry, a blank interface interconnection table is generated; The blank interface interconnection table is populated and updated; Parse the updated blank interface interconnection table to obtain the interface interconnection relationship between the several instances and the top layer; Based on the interface interconnection relationship, a Verilog integration top-level is generated, and instance interconnection is performed.

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