A clock circuit

Abstract

The application provides a clock circuit, comprising a clock source selection module, a system clock generation module, a peripheral clock generation module and a cross-clock-domain synchronization module; wherein the clock source selection module is used for selecting a clock as a source clock from a low-frequency external clock, a low-frequency crystal clock, a high-frequency external clock and a high-frequency crystal clock according to a final selection control signal; the system clock generation module is connected to the output end of the clock source selection module and is used for dividing the source clock and generating a system clock; the peripheral clock generation module is connected to the output end of the system clock generation module and is used for generating a peripheral clock according to the system clock; the cross-clock-domain synchronization module is connected between the system clock generation module and the clock source selection module and is used for generating the final selection control signal according to an initial selection control signal and performing cross-clock-domain transmission. Through the clock circuit provided by the application, the problem of too many clock constraint commands and a low-efficiency clock tree in the prior art clock circuit is solved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and in particular relates to a clock circuit. Background Technology

[0002] Clock circuit modules are important functional units in digital ICs. During the synthesis process, existing clock circuit modules need to constrain all clocks. Then, back-end engineers control the skew of all clocks in the same clock domain within the allowable range according to the constraints to meet the setup and hold times of all logic.

[0003] Because constraints need to be applied to all clocks, if there are many modules in the chip, the clock circuit module needs to provide the corresponding clocks, and the corresponding constraint commands will also increase, increasing the probability of errors and workload in the synthesis process. In addition, backend developers need to spend a lot of time building clock trees, because after the clock structure design becomes complex, the related clocks and their generated signals need to be balanced after interaction, making the clock tree extremely complex and inefficient. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a clock circuit to solve the problems of excessive clock constraint commands and complex and inefficient clock trees in existing clock circuits.

[0005] To achieve the above and other related objectives, the present invention provides a clock circuit, comprising: a clock source selection module, a system clock generation module, a peripheral clock generation module, and a cross-clock domain synchronization module; wherein,

[0006] The clock source selection module is used to select a clock from the low-frequency external clock, low-frequency crystal clock, high-frequency external clock and high-frequency crystal clock as the source clock output according to the final selection control signal.

[0007] The system clock generation module is connected to the output of the clock source selection module and is used to divide the source clock and generate the system clock.

[0008] The peripheral clock generation module is connected to the output of the system clock generation module and is used to generate a peripheral clock based on the system clock.

[0009] The cross-clock domain synchronization module is connected between the system clock generation module and the clock source selection module, and is used to generate the final selection control signal according to the initial selection control signal and perform cross-clock domain transmission.

[0010] Optionally, the clock source selection module includes: a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, and a sixth AND gate; wherein,

[0011] The first input terminal of the first AND gate is connected to the low-frequency external clock, the second input terminal is connected to the first final selection control signal, and the output terminal is connected to the output terminal of the second AND gate.

[0012] The first input of the second AND gate is connected to the low-frequency crystal clock, and the second input is connected to the second final selection control signal;

[0013] The first input terminal of the third AND gate is connected to the high-frequency external clock, the second input terminal is connected to the third final selection control signal, and the output terminal is connected to the output terminal of the fourth AND gate.

[0014] The first input terminal of the fourth AND gate is connected to the high-frequency crystal clock, and the second input terminal is connected to the fourth final selection control signal.

[0015] The first input terminal of the fifth AND gate is connected to the output terminals of the first AND gate and the second AND gate, the second input terminal is connected to the fifth final selection control signal, and the output terminal is connected to the output terminal of the sixth AND gate to generate the source clock.

[0016] The first input terminal of the sixth AND gate is connected to the output terminals of the third AND gate and the fourth AND gate, and the second input terminal is connected to the sixth final selection control signal.

[0017] Optionally, the cross-clock domain synchronization module includes: a low-frequency control unit, a high-frequency control unit, and an output control unit, all connected to the output terminal of the clock source selection module; wherein,

[0018] The low-frequency control unit is used to perform logical operations on the low-frequency initial selection control signal to generate a first final selection control signal and a second final selection control signal, and to transmit them across clock domains.

[0019] The high-frequency control unit is used to perform logical operations on the high-frequency initial selection control signal to generate a third final selection control signal and a fourth final selection control signal, and to transmit them across clock domains.

[0020] The output control unit is used to perform logical operations on the high / low frequency initial selection control signals to generate the fifth final selection control signal and the sixth final selection control signal, and to transmit them across clock domains.

[0021] Optionally, the low-frequency control unit includes: a low-frequency control signal generation section, a first low-frequency cross-clock domain synchronization section, and a second low-frequency cross-clock domain synchronization section; wherein,

[0022] The low-frequency control signal generation section includes: a first D flip-flop, a seventh AND gate, an eighth AND gate, and a first inverter; the clock input of the first D flip-flop is connected to the system clock, the data input is connected to the low-frequency initial selection control signal, and the non-inverting output is connected to the first input of the seventh AND gate and the input of the first inverter; the second input of the seventh AND gate is connected to the inverted signal of the first final selection control signal, and the output generates a second final selection control signal to be synchronized; the output of the first inverter is connected to the first input of the eighth AND gate; the second input of the eighth AND gate is connected to the inverted signal of the second final selection control signal, and the output generates a first final selection control signal to be synchronized.

[0023] The first low-frequency cross-clock domain synchronization section includes: at least two second D flip-flops; the clock terminal of any second D flip-flop is connected to the low-frequency external clock, the data terminal of the first second D flip-flop is connected to the first final selection control signal to be synchronized, the non-inverting output terminal of the previous stage second D flip-flop is connected to the data terminal of the next stage second D flip-flop, and the non-inverting output terminal of the last second D flip-flop generates the first final selection control signal.

[0024] The second low-frequency cross-clock domain synchronization section includes: at least two third D flip-flops; the clock terminal of any of the third D flip-flops is connected to the low-frequency crystal clock, the data terminal of the first third D flip-flop is connected to the second final selection control signal to be synchronized, the non-inverting output terminal of the previous stage third D flip-flop is connected to the data terminal of the next stage third D flip-flop, and the non-inverting output terminal of the last third D flip-flop generates the second final selection control signal.

[0025] Optionally, the high-frequency control unit includes: a high-frequency control signal generation section, a first high-frequency cross-clock domain synchronization section, and a second high-frequency cross-clock domain synchronization section; wherein,

[0026] The high-frequency control signal generation section includes: a fourth D flip-flop, a ninth AND gate, a tenth AND gate, and a second inverter; the clock input of the fourth D flip-flop is connected to the system clock, the data input is connected to the high-frequency initial selection control signal, and the non-inverting output is connected to the first input of the ninth AND gate and the input of the second inverter; the second input of the ninth AND gate is connected to the inverted signal of the third final selection control signal, and the output generates a fourth final selection control signal to be synchronized; the output of the second inverter is connected to the first input of the tenth AND gate; the second input of the tenth AND gate is connected to the inverted signal of the fourth final selection control signal, and the output generates a third final selection control signal to be synchronized.

[0027] The first high-frequency cross-clock domain synchronization section includes: at least two fifth D flip-flops; the clock terminal of any fifth D flip-flop is connected to the high-frequency external clock, the data terminal of the first fifth D flip-flop is connected to the third final selection control signal to be synchronized, the non-inverting output terminal of the previous fifth D flip-flop is connected to the data terminal of the next fifth D flip-flop, and the non-inverting output terminal of the last fifth D flip-flop generates the third final selection control signal.

[0028] The second high-frequency cross-clock domain synchronization section includes: at least two sixth D flip-flops; the clock terminal of any of the sixth D flip-flops is connected to the high-frequency crystal clock, the data terminal of the first sixth D flip-flop is connected to the fourth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage sixth D flip-flop is connected to the data terminal of the next stage sixth D flip-flop, and the non-inverting output terminal of the last sixth D flip-flop generates the fourth final selection control signal.

[0029] Optionally, the output control unit includes: a high / low frequency control signal generation section, a first high / low frequency cross-clock domain synchronization section, and a second high / low frequency cross-clock domain synchronization section; wherein,

[0030] The high / low frequency control signal generation section includes: a seventh D flip-flop, an eleventh AND gate, a twelfth AND gate, and a third inverter; the clock input of the seventh D flip-flop is connected to the system clock, the data input is connected to the high / low frequency initial selection control signal, and the non-inverting output is connected to the first input of the eleventh AND gate and the input of the third inverter; the second input of the eleventh AND gate is connected to the inverted signal of the fifth final selection control signal, and the output generates a sixth final selection control signal to be synchronized; the output of the third inverter is connected to the first input of the twelfth AND gate; the second input of the twelfth AND gate is connected to the inverted signal of the sixth final selection control signal, and the output generates a fifth final selection control signal to be synchronized;

[0031] The first high / low frequency cross-clock domain synchronization section includes: at least two eighth D flip-flops; the clock terminal of any eighth D flip-flop is connected to the low-frequency external clock or the low-frequency crystal oscillator clock, the data terminal of the first eighth D flip-flop is connected to the fifth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage eighth D flip-flop is connected to the data terminal of the next stage eighth D flip-flop, and the non-inverting output terminal of the last eighth D flip-flop generates the fifth final selection control signal;

[0032] The second high / low frequency cross-clock domain synchronization section includes: at least two ninth D flip-flops; the clock terminal of any of the ninth D flip-flops is connected to the high-frequency external clock or the high-frequency crystal oscillator clock, the data terminal of the first ninth D flip-flop is connected to the sixth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage ninth D flip-flop is connected to the data terminal of the next stage ninth D flip-flop, and the non-inverting output terminal of the last ninth D flip-flop generates the sixth final selection control signal.

[0033] Optionally, among the multiple D flip-flops across the clock synchronization section, at least one D flip-flop has a fourth inverter between its clock input and the clock it is connected to.

[0034] Optionally, among the multiple D flip-flops across the clock synchronization section, the fourth inverter is spaced out starting from the second D flip-flop.

[0035] Optionally, the system clock generation module includes: a system enable generation unit, a four-way selector, a thirteenth AND gate, a tenth D flip-flop, and a two-way selector; wherein,

[0036] The system enable generation unit is used to count the rising edges of the source clock and generate a divide-by-two enable signal, a divide-by-four enable signal, a divide-by-eight enable signal, and a divide-by-sixteen enable signal accordingly.

[0037] The control terminal of the four-way selector is connected to the first clock selection signal, the four input terminals are connected to the four frequency division enable signals respectively, and the output terminal is connected to the first input terminal of the thirteenth AND gate.

[0038] The second input of the thirteenth AND gate is connected to the source clock, and the output is connected to the clock terminal of the tenth D flip-flop.

[0039] The data terminal of the tenth D flip-flop is connected to its inverting output terminal, and the non-inverting output terminal is connected to the first input terminal of the two-way selector.

[0040] The control terminal of the two-way selector is connected to the second clock selection signal, the second input terminal is connected to the source clock, and the output terminal generates the system clock.

[0041] Optionally, the number of peripheral clock generation modules is greater than or equal to one; wherein, the peripheral clock generation module is used to divide the system clock and generate the peripheral clock, and / or, the peripheral clock generation module is used to control the output of the system clock according to the peripheral enable signal and generate the peripheral clock.

[0042] Optionally, when the peripheral clock generation module is used to divide the system clock and generate the peripheral clock, the peripheral clock generation module includes: a peripheral enable generation unit, a five-way selector, a fourteenth AND gate, and a gating unit; wherein,

[0043] The peripheral enable generation unit is used to count the rising edges of the system clock and generate a divide-by-one enable signal, a divide-by-two enable signal, a divide-by-three enable signal, a divide-by-four enable signal, and a divide-by-five enable signal accordingly.

[0044] The control terminal of the five-way selector is connected to the peripheral clock selection signal, the five input terminals are connected to the five frequency division enable signals respectively, and the output terminal is connected to the first input terminal of the fourteenth AND gate.

[0045] The second input terminal of the fourteenth AND gate is connected to the peripheral enable signal, and the output terminal is connected to the control terminal of the gate control unit.

[0046] The gating unit's input terminal is connected to the system clock, and its output terminal generates the peripheral clock.

[0047] Optionally, when the peripheral clock generation module is used to control the output of the system clock and generate the peripheral clock according to the peripheral enable signal, the peripheral clock generation module is implemented by a gating unit, wherein the control terminal of the gating unit is connected to the peripheral enable signal, the input terminal is connected to the system clock, and the output terminal generates the peripheral clock.

[0048] As described above, the clock circuit of this invention, through the design of a clock source selection module, a system clock division module, a peripheral clock generation module, and a cross-clock domain synchronization module, treats the system clock and the source clock as asynchronous during synthesis and place-and-route processes, and simultaneously starts a new calculation of the clock tree from the system clock. By making the clock tree into two segments of length, the clock tree can be shortened quickly, and unnecessary padded lengths of the clock tree caused by too many mutual checks between the system clock and the source clock are avoided. The clock circuit of this invention has a simpler synthesis process, greatly reduces the required clock constraint commands, and is easier to converge at the same synthesis timing at the same frequency. In engineering applications, the RTL (logic level) synthesis time is reduced by an average of more than 10 minutes. In the 0.11μm process, during the back-end place-and-route process, the clock tree length is reduced from 32ns to 9ns, the maximum clock skew is reduced from 13ns to 0.6ns, and the density after place-and-route is reduced from 85% to 72%. Attached Figure Description

[0049] Figure 1 The diagram shown is a circuit diagram of the clock circuit described in this invention.

[0050] Figure 2The diagram shows the waveform of the frequency division enable signal generated by the system enable generation unit in the clock circuit described in this invention.

[0051] Figure 3 The diagram shows the waveform of the frequency division enable signal generated by the peripheral enable generation unit in the clock circuit described in this invention.

[0052] Component designation explanation

[0053] 10. Clock Source Selection Module

[0054] 20 System Clock Generation Module

[0055] 21 System Enable Generation Unit

[0056] 30 Peripheral Clock Generation Module

[0057] 31 Peripheral Enable Generation Unit

[0058] 32 gate control units

[0059] 40 Cross-clock domain synchronization modules

[0060] 41 Low-frequency control unit

[0061] 411 Low-frequency control signal generation section

[0062] 412 First Low-Frequency Cross-Clock Domain Synchronization Section

[0063] 413 Second Low-Frequency Cross-Clock Domain Synchronization Section

[0064] 42 High-frequency control unit

[0065] 421 High-frequency control signal generation section

[0066] 422 First High-Frequency Cross-Clock Domain Synchronization Section

[0067] 423 Second High-Frequency Cross-Clock Domain Synchronization Section

[0068] 43 Output Control Unit

[0069] 431 High / Low Frequency Control Signal Generation Section

[0070] 432 First High / Low Frequency Cross-Clock Domain Synchronization Section

[0071] 433 Second High / Low Frequency Cross-Clock Domain Synchronization Section Detailed Implementation

[0072] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0074] like Figure 1 As shown, this embodiment provides a clock circuit, which includes: a clock source selection module 10, a system clock generation module 20, a peripheral clock generation module 30, and a cross-clock domain synchronization module 40.

[0075] The clock source selection module 10 is used to select a clock from the low-frequency external clock CLK_LRCY, the low-frequency crystal oscillator clock CLK_LRC, the high-frequency external clock CLK_HRCY, and the high-frequency crystal oscillator clock CLK_HRC as the source clock ICLK output according to the final selection control signal.

[0076] Specifically, the clock source selection module 10 includes: a first AND gate AND1, a second AND gate AND2, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, and a sixth AND gate AND6; wherein, the first input terminal of the first AND gate AND1 is connected to the low-frequency external clock CLK_LRCY, the second input terminal is connected to the first final selection control signal SEL_SYN_LRCY, and the output terminal is connected to the output terminal of the second AND gate AND2; the first input terminal of the second AND gate AND2 is connected to the low-frequency crystal oscillator clock CLK_LRC, and the second input terminal is connected to the second final selection control signal SEL_SYN_LRC; the first input terminal of the third AND gate AND3 is connected to the high-frequency external clock CLK_HRCY, and the second input terminal is connected to the third final selection control signal SEL_SYN_LRC. The control signal SLE_SYN_HRCY is connected to the output of the fourth AND gate AND4; the first input of the fourth AND gate AND4 is connected to the high-frequency crystal clock CLK_HRC, and the second input is connected to the fourth final selection control signal SEL_SYN_HRC; the first input of the fifth AND gate AND5 is connected to the outputs of the first AND gate AND1 and the second AND gate AND2, the second input is connected to the fifth final selection control signal SEL_SYN_L, and the output is connected to the output of the sixth AND gate AND6 to generate the source clock ICLK; the first input of the sixth AND gate AND6 is connected to the outputs of the third AND gate AND3 and the fourth AND gate AND4, and the second input is connected to the sixth final selection control signal SEL_SYN_H.

[0077] In this embodiment, the first final selection control signal SEL_SYN_LRCY and the second final selection control signal SEL_SYN_LRC are not both "1", the third final selection control signal SEL_SYN_HRCY and the fourth final selection control signal SEL_SYN_HRC are not both "1", and the fifth final selection control signal SEL_SYN_L and the sixth final selection control signal SEL_SYN_H are not both "1", thereby enabling the selection of a clock as the source clock ICLK from the low-frequency external clock CLK_LRCY, the low-frequency crystal oscillator clock CLK_LRC, the high-frequency external clock CLK_HRCY, and the high-frequency crystal oscillator clock CLK_HRC.

[0078] The system clock generation module 20 is connected to the output terminal of the clock source selection module 10 and is used to divide the source clock ICLK and generate the system clock SYS_CLK.

[0079] Specifically, the system clock generation module 20 includes: a system enable generation unit 21, a four-way selector MUX4, a thirteenth AND gate AND13, a tenth D flip-flop DFF10, and a two-way selector MUX2; the system enable generation unit 21 is used to count the rising edges of the source clock ICLK and generate corresponding frequency divider enable signals Clk_div2_en, Clk_div4_en, Clk_div8_en, and Clk_div16_en; the control terminal of the four-way selector MUX4 is connected to the first clock selection signal SEL_C, the four input terminals are connected to the output terminal of the system enable generation unit 21 to correspondingly receive the four frequency divider enable signals, and the output terminal is connected to the thirteenth AND gate AND13. The first input terminal of the thirteenth AND gate AND13 is connected to the source clock ICLK, and the output terminal is connected to the clock terminal of the tenth D flip-flop DFF10; the data terminal of the tenth D flip-flop DFF10 is connected to its inverting output terminal, and the non-inverting output terminal is connected to the first input terminal of the two-way selector MUX2; the control terminal of the two-way selector MUX2 is connected to the second clock selection signal Bypass, the second input terminal is connected to the source clock ICLK, and the output terminal generates the system clock SYS_CLK; wherein, the specific waveforms of the divide-by-two enable signal Clk_div2_en, the divide-by-four enable signal Clk_div4_en, the divide-by-eight enable signal Clk_div8_en, and the divide-by-sixteen enable signal Clk_div16_en are as follows: Figure 2 As shown.

[0080] In this embodiment, when the first clock selection signal SEL_C is valid, the second clock selection signal Bypass controls the input clock of the first input terminal of the two-way selector MUX2 as the system clock SYS_CLK output. The four-way selector MUX4, under the control of the first clock selection signal SEL_C, selects a frequency divider enable signal for output, and performs a logical AND operation on the output frequency divider enable signal EN1 and the source clock ICLK through the thirteenth AND gate AND13. Finally, it generates a frequency divider clock through the tenth D flip-flop DFF10 as the system clock SYS_CLK output, equivalent to a 2-fold, 4-fold, 8-fold, or 16-fold division of the source clock as the system clock SYS_CLK. When the first clock selection signal SEL_C is invalid, the second clock selection signal Bypass controls the input clock of the second input terminal of the two-way selector MUX2 as the system clock SYS_CLK output, that is, the source clock ICLK is used as the system clock SYS_CLK output, equivalent to a 1-fold division of the source clock ICLK as the system clock SYS_CLK. In practical applications, when the first clock selection signal SEL_C is valid, the effective control bit of the first clock selection signal SEL_C can be designed according to specific requirements, thereby selecting the corresponding frequency division enable signal output.

[0081] The peripheral clock generation module 30 is connected to the output terminal of the system clock generation module 20 and is used to generate a peripheral clock based on the system clock SYS_CLK.

[0082] Specifically, the number of peripheral clock generation modules 30 is greater than or equal to one; wherein, the peripheral clock generation module 30 is used to divide the system clock SYS_CLK and generate the peripheral clock, and / or, the peripheral clock generation module 30 is used to control the output of the system clock SYS_CLK according to the peripheral enable signal and generate the peripheral clock.

[0083] In practical applications, the number of peripheral clock generation modules 30 can be set according to specific needs, and this embodiment does not limit this. The peripheral clock generation module 30 can generate the peripheral clock by dividing the system clock SYS_CLK, or by controlling the output of the system clock SYS_CLK according to the peripheral enable signal, or both can coexist. This depends on the peripheral type. If the peripheral is an asynchronous transceiver (UART), a timer, or an analog-to-digital converter (ADC), then the peripheral clock generation module 30 needs to divide the system clock SYS_CLK to generate the peripheral clock. If the peripheral is a CPU, then the peripheral clock generation module 30 needs to control the output of the system clock SYS_CLK according to the peripheral enable signal to generate the peripheral clock.

[0084] More specifically, when the peripheral clock generation module 30 is used to divide the system clock SYS_CLK and generate the peripheral clock, the peripheral clock generation module 30 includes: a peripheral enable generation unit 31, a five-way selector MUX5, a fourteenth AND gate AND14, and a gating unit 32; wherein, the peripheral enable generation unit 31 is used to count the rising edges of the system clock SYS_CLK and generate corresponding frequency divider enable signals sys_div1_en, sys_div2_en, sys_div3_en, sys_div4_en, and sys_div5_en; the control terminal of the five-way selector MUX5 is connected to a peripheral clock selection signal, such as Urat_sel, Timer_sel, or Adc_sel, and the five input terminals are connected to the peripheral. The output of enable generation unit 21 is connected to five frequency division enable signals, and the output is connected to the first input of the fourteenth AND gate AND14; the second input of the fourteenth AND gate AND14 is connected to a peripheral enable signal, such as Uart_en, Timer_en, or Adc_en, and the output is connected to the control terminal of the gate control unit (CKG) 32; the input of the gate control unit 32 is connected to the system clock SYS_CLK, and the output generates the peripheral clock, such as Uart_clk, Timer_clk, or Adc_clk; wherein, the specific waveforms of the frequency division enable signal sys_div1_en, the frequency division enable signal sys_div2_en, the frequency division enable signal sys_div3_en, the frequency division enable signal sys_div4_en, and the frequency division enable signal sys_div5_en are as follows: Figure 3As shown. In this embodiment, the five-way selector MUX5, under the control of the peripheral clock selection signal, selects a divide-by-one enable signal for output. The fourteenth AND gate AND14 performs a logical AND operation on the output divide-by-one enable signal and the peripheral enable signal to obtain an enable control signal EN2, which controls the gate control unit 32 to turn on or off, thereby achieving a divide-by-one, divide-by-two, divide-by-three, divide-by-four, or divide-by-five operation on the system clock SYS_CLK. In practical applications, the effective control bits of the peripheral clock selection signal can be designed according to specific requirements to select the corresponding divide-by-one enable signal for output.

[0085] When the peripheral clock generation module 30 controls the output of the system clock SYS_CLK based on the peripheral enable signal and generates the peripheral clock, the peripheral clock generation module 30 is implemented using a gating unit 32. The control terminal of the gating unit 32 is connected to the peripheral enable signal (e.g., cpu_en), the input terminal is connected to the system clock SYS_CLK, and the output terminal generates the peripheral clock (e.g., cpu_clk). In this embodiment, the gating unit 32 is turned on or off under the control of the peripheral enable signal, thereby controlling the output of the system clock SYS_CLK to generate the peripheral clock.

[0086] The cross-clock domain synchronization module 40 is connected between the system clock generation module 20 and the clock source selection module 10, and is used to generate the final selection control signal according to the initial selection control signal and perform cross-clock domain transmission.

[0087] Specifically, the cross-clock domain synchronization module 40 includes a low-frequency control unit 41, a high-frequency control unit 42, and an output control unit 43, all of which are connected to the output terminal of the clock source selection module 20.

[0088] The low-frequency control unit 41 is used to perform logical operations on the low-frequency initial selection control signal LIN to generate a first final selection control signal SEL_SYN_LRCY and a second final selection control signal SEL_SYN_LRC, and to perform cross-clock domain transmission.

[0089] More specifically, the low-frequency control unit 41 includes: a low-frequency control signal generation section 411, a first low-frequency cross-clock domain synchronization section 412, and a second low-frequency cross-clock domain synchronization section 413; wherein,

[0090] The low-frequency control signal generation section 411 includes: a first D flip-flop DFF1, a seventh AND gate AND7, an eighth AND gate AND8, and a first inverter INV1; the clock terminal of the first D flip-flop DFF1 is connected to the system clock SYS_CLK, the data terminal is connected to the low-frequency initial selection control signal LIN, and the non-inverting output terminal is connected to the first input terminal of the seventh AND gate AND7 and the input terminal of the first inverter INV1; the second input terminal of the seventh AND gate AND7 is connected to the inverted signal of the first final selection control signal SEL_SYN_LRCY, and the output terminal generates a second final selection control signal to be synchronized; the output terminal of the first inverter INV1 is connected to the first input terminal of the eighth AND gate AND8; the second input terminal of the eighth AND gate AND8 is connected to the inverted signal of the second final selection control signal SEL_SYN_LRC, and the output terminal generates a first final selection control signal to be synchronized;

[0091] The first low-frequency cross-clock domain synchronization section 412 includes: at least two second D flip-flops DFF2; the clock terminal of any second D flip-flop DFF2 is connected to the low-frequency external clock CLK_LRCY; the data terminal of the first second D flip-flop DFF2 is connected to the first final selection control signal to be synchronized; the non-inverting output of the previous stage second D flip-flop DFF2 is connected to the data terminal of the next stage second D flip-flop DFF2; and the non-inverting output of the last second D flip-flop DFF2 generates the first final selection control signal SEL_SYN_LRCY.

[0092] The second low-frequency cross-clock domain synchronization section 413 includes: at least two third D flip-flops DFF3; the clock terminal of any of the third D flip-flops DFF3 is connected to the low-frequency crystal oscillator clock CLK_LRC, the data terminal of the first third D flip-flop DFF3 is connected to the second final selection control signal to be synchronized, the non-inverting output terminal of the previous stage third D flip-flop DFF3 is connected to the data terminal of the next stage third D flip-flop DFF3, and the non-inverting output terminal of the last third D flip-flop DFF3 generates the second final selection control signal SEL_SYN_LRC.

[0093] Furthermore, for the first low-frequency cross-clock domain synchronization section 412, among its plurality of second D flip-flops DFF2, at least one second D flip-flop DFF2 has a fourth inverter between its clock input and the low-frequency external clock CLK_LRCY it is connected to. Even further, among the plurality of D flip-flops, the fourth inverter is spaced out starting from the second D flip-flop; that is, the clock inputs of the odd-numbered D flip-flops are connected to the low-frequency external clock CLK_LRCY, and the clock inputs of the even-numbered D flip-flops are connected to the inverted signal of the low-frequency external clock CLK_LRCY, thereby improving the synchronization speed. And / or, for the second low-frequency cross-clock domain synchronization section 413, among its plurality of third D flip-flops DFF3, at least one third D flip-flop DFF3 has a fourth inverter between its clock input and the low-frequency crystal oscillator clock CLK_LRC it is connected to. Furthermore, among the multiple D flip-flops, the fourth inverter is set at intervals starting from the second D flip-flop. That is, the clock terminals of the odd-numbered D flip-flops are connected to the low-frequency crystal oscillator clock CLK_LRC, and the clock terminals of the even-numbered D flip-flops are connected to the inverted signal of the low-frequency crystal oscillator clock CLK_LRC, thereby improving the synchronization speed.

[0094] In this embodiment, when the low-frequency initial selection control signal LIN is set to "0", the low-frequency external clock CLK_LRCY is selected; when the low-frequency initial selection control signal LIN is set to "1", the low-frequency crystal oscillator clock CLK_LRC is selected. When the low-frequency initial selection control signal LIN is "0", the output of the first D flip-flop DFF1 is "0", and after passing through the first inverter INV1, it becomes "1". At this time, the output of the seventh AND gate AND7 is "0", and the second final selection control signal SEL_SYN_LRC output after passing through the second low-frequency cross-clock domain synchronization section 413 is "0". At this time, the output of the eighth AND gate AND8 is "1", and the first final selection control signal SEL_SYN_LRC output after passing through the first low-frequency cross-clock domain synchronization section 412 is "1". When RCY is "1", the clock source selection module 10 selects and outputs the low-frequency external clock CLK_LRCY. When the low-frequency initial selection control signal LIN is "1", the output of the first D flip-flop DFF1 is "1", and after passing through the first inverter INV1, it is "0". At this time, the output of the eighth AND gate AND8 is "0", and after passing through the first low-frequency cross-clock domain synchronization section 412, the first final selection control signal SEL_SYN_LRCY output is "0". At this time, the output of the seventh AND gate AND7 is "1", and after passing through the second low-frequency cross-clock domain synchronization section 413, the second final selection control signal SEL_SYN_LRC output is "1", thereby the clock source selection module 10 selects and outputs the low-frequency crystal oscillator clock CLK_LRC.

[0095] The high-frequency control unit 42 is used to perform logical operations on the high-frequency initial selection control signal HIN to generate the third final selection control signal SLE_SYN_HRCY and the fourth final selection control signal SEL_SYN_HRC, and to transmit them across clock domains.

[0096] The high-frequency control unit 42 includes: a high-frequency control signal generation section 421, a first high-frequency cross-clock domain synchronization section 422, and a second high-frequency cross-clock domain synchronization section 423; wherein...

[0097] The high-frequency control signal generation section 421 includes: a fourth D flip-flop DFF4, a ninth AND gate AND9, a tenth AND gate AND10, and a second inverter INV2; the clock terminal of the fourth D flip-flop DFF4 is connected to the system clock SYS_CLK, the data terminal is connected to the high-frequency initial selection control signal HIN, and the non-inverting output terminal is connected to the first input terminal of the ninth AND gate AND9 and the input terminal of the second inverter INV2; the second input terminal of the ninth AND gate AND9 is connected to the inverted signal of the third final selection control signal SEL_SYN_HRCY, and the output terminal generates a fourth final selection control signal to be synchronized; the output terminal of the second inverter INV2 is connected to the first input terminal of the tenth AND gate AND10; the second input terminal of the tenth AND gate AND10 is connected to the inverted signal of the fourth final selection control signal SEL_SYN_HRC, and the output terminal generates a third final selection control signal to be synchronized;

[0098] The first high-frequency cross-clock domain synchronization section 422 includes: at least two fifth D flip-flops DFF5; the clock terminal of any fifth D flip-flop DFF5 is connected to the high-frequency external clock CLK_HRCY, the data terminal of the first fifth D flip-flop DFF5 is connected to the third final selection control signal to be synchronized, the non-inverting output of the previous stage fifth D flip-flop DFF5 is connected to the data terminal of the next stage fifth D flip-flop DFF5, and the non-inverting output of the last fifth D flip-flop DFF5 generates the third final selection control signal SEL_SYN_HRCY;

[0099] The second high-frequency cross-clock domain synchronization section 423 includes: at least two sixth D flip-flops DFF6; the clock terminal of any of the sixth D flip-flops DFF6 is connected to the high-frequency crystal clock CLK_HRC, the data terminal of the first sixth D flip-flop DFF6 is connected to the fourth final selection control signal to be synchronized, the non-inverting output of the previous stage sixth D flip-flop DFF6 is connected to the data terminal of the next stage sixth D flip-flop DFF6, and the non-inverting output of the last sixth D flip-flop DFF6 generates the fourth final selection control signal SEL_SYN_HRC.

[0100] Furthermore, for the first high-frequency cross-clock domain synchronization section 422, among its plurality of fifth D flip-flops DFF5, at least one fifth D flip-flop DFF5 has a fourth inverter between its clock input and the high-frequency external clock CLK_HRCY it is connected to. Even further, among the plurality of D flip-flops, the fourth inverter is spaced out starting from the second D flip-flop; that is, the clock inputs of the odd-numbered D flip-flops are connected to the high-frequency external clock CLK_HRCY, and the clock inputs of the even-numbered D flip-flops are connected to the inverted signal of the high-frequency external clock CLK_HRCY, thereby improving the synchronization speed. And / or, for the second high-frequency cross-clock domain synchronization section 423, among its plurality of sixth D flip-flops DFF6, at least one sixth D flip-flop DFF6 has a fourth inverter between its clock input and the high-frequency crystal oscillator clock CLK_HRC it is connected to. Furthermore, among the multiple D flip-flops, the fourth inverter is set at intervals starting from the second D flip-flop. That is, the clock terminals of the odd-numbered D flip-flops are connected to the high-frequency crystal oscillator clock CLK_HRC, and the clock terminals of the even-numbered D flip-flops are connected to the inverted signal of the high-frequency crystal oscillator clock CLK_HRC, thereby improving the synchronization speed.

[0101] In this embodiment, when the high-frequency initial selection control signal HIN is set to "0", the high-frequency external clock CLK_HRCY is selected; when the high-frequency initial selection control signal HIN is set to "1", the high-frequency crystal oscillator clock CLK_HRC is selected. When the high-frequency initial selection control signal HIN is "0", the output of the fourth D flip-flop DFF4 is "0", which becomes "1" after passing through the second inverter INV2. At this time, the output of the ninth AND gate AND9 is "0", and the fourth final selection control signal SEL_SYN_HRC output after passing through the second high-frequency cross-clock domain synchronization section 423 is "0". At this time, the output of the tenth AND gate AND10 is "1", and the third final selection control signal SEL_SYN_HRC output after passing through the first high-frequency cross-clock domain synchronization section 422 is "1". When RCY is "1", the clock source selection module 10 selects and outputs the high-frequency external clock CLK_HRCY. When the high-frequency initial selection control signal HIN is "1", the output of the fourth D flip-flop DFF4 is "1", which becomes "0" after passing through the second inverter INV2. At this time, the output of the tenth AND gate AND10 is "0", and the third final selection control signal SEL_SYN_HRCY output after passing through the first high-frequency cross-clock domain synchronization section 422 is "0". At this time, the output of the ninth AND gate AND9 is "1", and the fourth final selection control signal SEL_SYN_HRC output after passing through the second high-frequency cross-clock domain synchronization section 423 is "1", thereby selecting and outputting the high-frequency crystal oscillator clock CLK_HRC by the clock source selection module 10.

[0102] The output control unit 43 is used to perform logical operations on the high / low frequency initial selection control signal H / LIN to generate the fifth final selection control signal SEL_SYN_L and the sixth final selection control signal SEL_SYN_H, and to transmit them across clock domains.

[0103] The output control unit 43 includes: a high / low frequency control signal generation section 431, a first high / low frequency cross-clock domain synchronization section 432, and a second high / low frequency cross-clock domain synchronization section 433; wherein...

[0104] The high / low frequency control signal generation section 431 includes: a seventh D flip-flop DFF7, an eleventh AND gate AND11, a twelfth AND gate AND12, and a third inverter INV3; the clock terminal of the seventh D flip-flop DFF7 is connected to the system clock SYS_CLK, the data terminal is connected to the high / low frequency initial selection control signal H / LIN, and the non-inverting output terminal is connected to the first input terminal of the eleventh AND gate AND11 and the input terminal of the third inverter INV3; the second input terminal of the eleventh AND gate AND11 is connected to the inverted signal of the fifth final selection control signal SEL_SYN_L, and the output terminal generates a sixth final selection control signal to be synchronized; the output terminal of the third inverter INV3 is connected to the first input terminal of the twelfth AND gate AND12; the second input terminal of the twelfth AND gate AND12 is connected to the inverted signal of the sixth final selection control signal SEL_SYN_H, and the output terminal generates a fifth final selection control signal to be synchronized;

[0105] The first high / low frequency cross-clock domain synchronization section 432 includes: at least two eighth D flip-flops DFF8; the clock terminal of any of the eighth D flip-flops DFF8 is connected to the low-frequency external clock CLK_LRCY or the low-frequency crystal oscillator clock CLK_LRC, the data terminal of the first eighth D flip-flop DFF8 is connected to the fifth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage eighth D flip-flop DFF8 is connected to the data terminal of the next stage eighth D flip-flop DFF8, and the non-inverting output terminal of the last eighth D flip-flop DFF8 generates the fifth final selection control signal SEL_SYN_L;

[0106] The second high / low frequency cross-clock domain synchronization section 433 includes: at least two ninth D flip-flops DFF9; the clock terminal of any of the ninth D flip-flops DFF9 is connected to the high-frequency external clock CLK_HRCY or the high-frequency crystal oscillator clock CLK_HRC; the data terminal of the first ninth D flip-flop DFF9 is connected to the sixth final selection control signal to be synchronized; the non-inverting output terminal of the previous stage ninth D flip-flop DFF9 is connected to the data terminal of the next stage ninth D flip-flop DFF9; and the non-inverting output terminal of the last ninth D flip-flop DFF9 generates the sixth final selection control signal SEL_SYN_H.

[0107] Furthermore, for the first high / low frequency cross-clock domain synchronization section 432, among its plurality of eighth D flip-flops DFF8, at least one eighth D flip-flop DFF8 has a fourth inverter between its clock input and the low-frequency clock CLK_L it is connected to. Even further, among the plurality of D flip-flops, the fourth inverter is spaced out starting from the second D flip-flop; that is, the clock inputs of the odd-numbered D flip-flops are connected to the low-frequency clock CLK_L, and the clock inputs of the even-numbered D flip-flops are connected to the inverted signal of the low-frequency clock CLK_L, thereby improving the synchronization speed. And / or, for the second high / low frequency cross-clock domain synchronization section 433, among its plurality of ninth D flip-flops DFF9, at least one ninth D flip-flop DFF9 has a fourth inverter between its clock input and the high-frequency clock CLK_H it is connected to. Furthermore, among the multiple D flip-flops, the fourth inverter is set at intervals starting from the second D flip-flop. That is, the clock terminals of the odd-numbered D flip-flops are connected to the high-frequency clock CLK_H, and the clock terminals of the even-numbered D flip-flops are connected to the inverted signal of the high-frequency clock CLK_H, thereby improving the synchronization speed.

[0108] In this embodiment, a low-frequency clock is selected when the high / low frequency initial selection control signal H / LIN is "0", and a high-frequency clock is selected when the high / low frequency initial selection control signal H / LIN is "1". When the high / low frequency initial selection control signal H / LIN is "0", the output of the seventh D flip-flop DFF7 is "0", which becomes "1" after passing through the third inverter INV3. At this time, the output of the eleventh AND gate AND11 is "0", and the sixth final selection control signal SEL_SYN_H output after passing through the second high / low frequency cross-clock domain synchronization section 433 is "0". At this time, the output of the twelfth AND gate AND12 is "1", and the fifth final selection control signal SE output after passing through the first high / low frequency cross-clock domain synchronization section 432 is "1". When L_SYN_L is "1", the clock source selection module 10 selects and outputs a low-frequency clock. When the high / low frequency initial selection control signal H / LIN is "1", the output of the seventh D flip-flop DFF7 is "1", and after passing through the third inverter INV3, it becomes "0". At this time, the output of the twelfth AND gate AND12 is "0", and after passing through the first high / low frequency cross-clock domain synchronization section 432, the fifth final selection control signal SEL_SYN_L output is "0". At this time, the output of the eleventh AND gate AND11 is "1", and after passing through the second high / low frequency cross-clock domain synchronization section 433, the sixth final selection control signal SEL_SYN_H output is "1", thereby selecting and outputting a high-frequency clock by the clock source selection module 10. It should be noted that the "low-frequency clock" mentioned here refers to the clock selected and output by the clock source selection module 10 from the low-frequency external clock CLK_LRCY and the low-frequency crystal oscillator clock CLK_LRC, and the "high-frequency clock" refers to the clock selected and output by the clock source selection module 10 from the high-frequency external clock CLK_HRCY and the high-frequency crystal oscillator clock CLK_HRC.

[0109] In summary, the clock circuit of this invention, through the design of a clock source selection module, a system clock division module, a peripheral clock generation module, and a cross-clock domain synchronization module, treats the system clock and source clock as asynchronous during synthesis and placement / routing, and simultaneously starts a new calculation of the clock tree from the system clock. By making the clock tree into two segments of length, the clock tree can be shortened quickly, and unnecessary padded lengths caused by too many mutual checks between the system clock and source clock are avoided. The clock circuit of this invention has a simpler synthesis process, greatly reduces the required clock constraint commands, and is easier to converge at the same synthesis timing at the same frequency. In engineering applications, the RTL (logic level) synthesis time is reduced by an average of more than 10 minutes. In 0.11μm process technology, during the back-end placement and routing process, the clock tree length is reduced from 32ns to 9ns, the maximum clock skew is reduced from 13ns to 0.6ns, and the density after placement and routing is reduced from 85% to 72%. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A clock circuit, characterized in that, The clock circuit includes: a clock source selection module, a system clock generation module, a peripheral clock generation module, and a cross-clock domain synchronization module; wherein... The clock source selection module is used to select a clock from the low-frequency external clock, low-frequency crystal clock, high-frequency external clock and high-frequency crystal clock as the source clock output according to the final selection control signal. The final selection control signal includes a first final selection control signal, a second final selection control signal, a third final selection control signal, a fourth final selection control signal, a fifth final selection control signal, and a sixth final selection control signal; The first final selection control signal and the second final selection control signal are used to control the selection of the low-frequency external clock and the low-frequency crystal oscillator clock, respectively, and the selected clock is a low-frequency clock. The third final selection control signal and the fourth final selection control signal are used to control the selection of the high-frequency external clock and the high-frequency crystal oscillator clock, respectively, and the selected clock is a high-frequency clock. The fifth final selection control signal and the sixth final selection control signal are used to control the selection of the low-frequency clock and the high-frequency clock, respectively. The system clock generation module is connected to the output of the clock source selection module and is used to divide the source clock and generate the system clock. The peripheral clock generation module is connected to the output of the system clock generation module and is used to generate a peripheral clock based on the system clock. The cross-clock domain synchronization module is connected between the system clock generation module and the clock source selection module, and is used to generate the final selection control signal according to the initial selection control signal and perform cross-clock domain transmission. The initial selection control signal includes: a low-frequency initial selection control signal, a high-frequency initial selection control signal, and a high / low-frequency initial selection control signal; The cross-clock domain synchronization module includes: a low-frequency control unit, a high-frequency control unit, and an output control unit, all connected to the input terminal of the clock source selection module; wherein, The low-frequency control unit is used to perform logical operations on the low-frequency initial selection control signal to generate a first final selection control signal and a second final selection control signal, and to transmit them across clock domains. The high-frequency control unit is used to perform logical operations on the high-frequency initial selection control signal to generate a third final selection control signal and a fourth final selection control signal, and to transmit them across clock domains. The output control unit is used to perform logical operations on the high / low frequency initial selection control signals to generate the fifth final selection control signal and the sixth final selection control signal, and to transmit them across clock domains.

2. The clock circuit according to claim 1, characterized in that, The clock source selection module includes: a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, and a sixth AND gate; wherein, The first input terminal of the first AND gate is connected to the low-frequency external clock, the second input terminal is connected to the first final selection control signal, and the output terminal is connected to the output terminal of the second AND gate. The first input of the second AND gate is connected to the low-frequency crystal clock, and the second input is connected to the second final selection control signal; The first input terminal of the third AND gate is connected to the high-frequency external clock, the second input terminal is connected to the third final selection control signal, and the output terminal is connected to the output terminal of the fourth AND gate. The first input terminal of the fourth AND gate is connected to the high-frequency crystal clock, and the second input terminal is connected to the fourth final selection control signal. The first input terminal of the fifth AND gate is connected to the output terminals of the first AND gate and the second AND gate, the second input terminal is connected to the fifth final selection control signal, and the output terminal is connected to the output terminal of the sixth AND gate to generate the source clock. The first input terminal of the sixth AND gate is connected to the output terminals of the third AND gate and the fourth AND gate, and the second input terminal is connected to the sixth final selection control signal.

3. The clock circuit according to claim 1, characterized in that, The low-frequency control unit includes: a low-frequency control signal generation section, a first low-frequency cross-clock domain synchronization section, and a second low-frequency cross-clock domain synchronization section; wherein... The low-frequency control signal generation section includes: a first D flip-flop, a seventh AND gate, an eighth AND gate, and a first inverter; the clock input of the first D flip-flop is connected to the system clock, the data input is connected to the low-frequency initial selection control signal, and the non-inverting output is connected to the first input of the seventh AND gate and the input of the first inverter; the second input of the seventh AND gate is connected to the inverted signal of the first final selection control signal, and the output generates a second final selection control signal to be synchronized; the output of the first inverter is connected to the first input of the eighth AND gate; the second input of the eighth AND gate is connected to the inverted signal of the second final selection control signal, and the output generates a first final selection control signal to be synchronized. The first low-frequency cross-clock domain synchronization section includes: at least two second D flip-flops; the clock terminal of any second D flip-flop is connected to the low-frequency external clock, the data terminal of the first second D flip-flop is connected to the first final selection control signal to be synchronized, the non-inverting output terminal of the previous stage second D flip-flop is connected to the data terminal of the next stage second D flip-flop, and the non-inverting output terminal of the last second D flip-flop generates the first final selection control signal. The second low-frequency cross-clock domain synchronization section includes: at least two third D flip-flops; the clock terminal of any of the third D flip-flops is connected to the low-frequency crystal clock, the data terminal of the first third D flip-flop is connected to the second final selection control signal to be synchronized, the non-inverting output terminal of the previous stage third D flip-flop is connected to the data terminal of the next stage third D flip-flop, and the non-inverting output terminal of the last third D flip-flop generates the second final selection control signal.

4. The clock circuit according to claim 1, characterized in that, The high-frequency control unit includes: a high-frequency control signal generation section, a first high-frequency cross-clock domain synchronization section, and a second high-frequency cross-clock domain synchronization section; wherein... The high-frequency control signal generation section includes: a fourth D flip-flop, a ninth AND gate, a tenth AND gate, and a second inverter; the clock input of the fourth D flip-flop is connected to the system clock, the data input is connected to the high-frequency initial selection control signal, and the non-inverting output is connected to the first input of the ninth AND gate and the input of the second inverter; the second input of the ninth AND gate is connected to the inverted signal of the third final selection control signal, and the output generates a fourth final selection control signal to be synchronized; the output of the second inverter is connected to the first input of the tenth AND gate; the second input of the tenth AND gate is connected to the inverted signal of the fourth final selection control signal, and the output generates a third final selection control signal to be synchronized. The first high-frequency cross-clock domain synchronization section includes: at least two fifth D flip-flops; the clock terminal of any fifth D flip-flop is connected to the high-frequency external clock, the data terminal of the first fifth D flip-flop is connected to the third final selection control signal to be synchronized, the non-inverting output terminal of the previous fifth D flip-flop is connected to the data terminal of the next fifth D flip-flop, and the non-inverting output terminal of the last fifth D flip-flop generates the third final selection control signal. The second high-frequency cross-clock domain synchronization section includes: at least two sixth D flip-flops; the clock terminal of any of the sixth D flip-flops is connected to the high-frequency crystal clock, the data terminal of the first sixth D flip-flop is connected to the fourth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage sixth D flip-flop is connected to the data terminal of the next stage sixth D flip-flop, and the non-inverting output terminal of the last sixth D flip-flop generates the fourth final selection control signal.

5. The clock circuit according to claim 1, characterized in that, The output control unit includes: a high / low frequency control signal generation section, a first high / low frequency cross-clock domain synchronization section, and a second high / low frequency cross-clock domain synchronization section; wherein... The high / low frequency control signal generation section includes: a seventh D flip-flop, an eleventh AND gate, a twelfth AND gate, and a third inverter; the clock input of the seventh D flip-flop is connected to the system clock, the data input is connected to the high / low frequency initial selection control signal, and the non-inverting output is connected to the first input of the eleventh AND gate and the input of the third inverter; the second input of the eleventh AND gate is connected to the inverted signal of the fifth final selection control signal, and the output generates a sixth final selection control signal to be synchronized; the output of the third inverter is connected to the first input of the twelfth AND gate; the second input of the twelfth AND gate is connected to the inverted signal of the sixth final selection control signal, and the output generates a fifth final selection control signal to be synchronized; The first high / low frequency cross-clock domain synchronization section includes: at least two eighth D flip-flops; the clock terminal of any eighth D flip-flop is connected to the low-frequency external clock or the low-frequency crystal oscillator clock, the data terminal of the first eighth D flip-flop is connected to the fifth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage eighth D flip-flop is connected to the data terminal of the next stage eighth D flip-flop, and the non-inverting output terminal of the last eighth D flip-flop generates the fifth final selection control signal; The second high / low frequency cross-clock domain synchronization section includes: at least two ninth D flip-flops; the clock terminal of any of the ninth D flip-flops is connected to the high-frequency external clock or the high-frequency crystal oscillator clock, the data terminal of the first ninth D flip-flop is connected to the sixth final selection control signal to be synchronized, the non-inverting output terminal of the previous stage ninth D flip-flop is connected to the data terminal of the next stage ninth D flip-flop, and the non-inverting output terminal of the last ninth D flip-flop generates the sixth final selection control signal.

6. The clock circuit according to claim 3, 4 or 5, characterized in that, In a cross-clock synchronization section of multiple D flip-flops, at least one D flip-flop has a fourth inverter between its clock input and the clock it is connected to.

7. The clock circuit according to claim 6, characterized in that, In the multiple D flip-flops across the clock synchronization section, the fourth inverter is spaced out starting from the second D flip-flop.

8. The clock circuit according to claim 1, characterized in that, The system clock generation module includes: a system enable generation unit, a four-way selector, a thirteenth AND gate, a tenth D flip-flop, and a two-way selector; wherein... The system enable generation unit is used to count the rising edges of the source clock and generate a divide-by-two enable signal, a divide-by-four enable signal, a divide-by-eight enable signal, and a divide-by-sixteen enable signal accordingly. The control terminal of the four-way selector is connected to the first clock selection signal, the four input terminals are connected to the four frequency division enable signals respectively, and the output terminal is connected to the first input terminal of the thirteenth AND gate. The second input of the thirteenth AND gate is connected to the source clock, and the output is connected to the clock terminal of the tenth D flip-flop. The data terminal of the tenth D flip-flop is connected to its inverting output terminal, and the non-inverting output terminal is connected to the first input terminal of the two-way selector. The control terminal of the two-way selector is connected to the second clock selection signal, the second input terminal is connected to the source clock, and the output terminal generates the system clock.

9. The clock circuit according to claim 1, characterized in that, The number of peripheral clock generation modules is greater than or equal to 1; wherein, the peripheral clock generation module is used to divide the system clock and generate the peripheral clock, and / or, the peripheral clock generation module is used to control the output of the system clock according to the peripheral enable signal and generate the peripheral clock.

10. The clock circuit according to claim 9, characterized in that, When the peripheral clock generation module is used to divide the system clock and generate the peripheral clock, the peripheral clock generation module includes: a peripheral enable generation unit, a five-way selector, a fourteenth AND gate, and a gating unit; wherein... The peripheral enable generation unit is used to count the rising edges of the system clock and generate a divide-by-one enable signal, a divide-by-two enable signal, a divide-by-three enable signal, a divide-by-four enable signal, and a divide-by-five enable signal accordingly. The control terminal of the five-way selector is connected to the peripheral clock selection signal, the five input terminals are connected to the five frequency division enable signals respectively, and the output terminal is connected to the first input terminal of the fourteenth AND gate. The second input terminal of the fourteenth AND gate is connected to the peripheral enable signal, and the output terminal is connected to the control terminal of the gate control unit. The gating unit's input terminal is connected to the system clock, and its output terminal generates the peripheral clock.

11. The clock circuit according to claim 10, characterized in that, When the peripheral clock generation module is used to control the output of the system clock and generate the peripheral clock according to the peripheral enable signal, the peripheral clock generation module is implemented by a gating unit, wherein the control terminal of the gating unit is connected to the peripheral enable signal, the input terminal is connected to the system clock, and the output terminal generates the peripheral clock.

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