Eeprom and method of operating the same

Abstract

The application discloses an EEPROM, which is composed of a plurality of memory cells to form an array unit, and a plurality of array units to form an array structure of the EEPROM. Each memory cell is a split-gate floating-gate device. In the array structure, each array unit in the same row shares a same row control gate line, and a local word line is independently arranged. An erase process is divided into an initial stage, a word line power-on stage and an erase stage. In the initial stage, the local word line of an unselected cell is also connected to the ground potential of the main word line for one pulse time; in the word line power-on stage, the local word line of the unselected cell is floated on the basis of the ground potential; and in the erase stage, the floating potential of the local word line of the unselected cell is below the ground potential under the coupling effect of the negative erase voltage of the control gate line, so that the risk of erasing each memory cell of the unselected cell is reduced. The application also discloses an operating method of the EEPROM. The application can reduce the risk of erasing the unselected array unit in the same row in the erase process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to an EEPROM. This invention also relates to a method for operating an EEPROM. Background Technology

[0002] like Figure 1 The diagram shown is a schematic diagram of the circuit structure of a conventional EEPROM storage cell 101; as shown... Figure 2 The diagram shown is a cross-sectional view of a conventional EEPROM storage cell 101; as shown... Figure 3 The diagram shown is an array structure diagram of an existing EEPROM. The existing EEPROM includes multiple storage cells 101, which together form an array cell 301. The array cells 301 are arranged to form the array structure of the EEPROM.

[0003] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0004] like Figure 2 As shown, the split-gate floating gate device includes: a source region 205 and a drain region 206, a plurality of split first gate structures with floating gates 104 located between the source region 205 and the drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0005] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0006] The separated gate floating gate device is an N-type device, and both the source region 205 and the drain region 206 are composed of N+ regions.

[0007] The P-type doped channel region is located between the source region 205 and the drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The source region 205 and the drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the source region 205 and the drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0008] The drain region 206 of the storage cell 101 is connected to the drain electrode D.

[0009] The source region 205 of the storage unit 101 is connected to the source S.

[0010] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0011] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0012] The control gate 105 is connected to the control gate line CG, and the word line gate 106 is connected to the word line WL.

[0013] When erasing the storage unit 101:

[0014] The control gate line CG is connected to a negative erase voltage.

[0015] The word line WL is connected to the positive erase voltage.

[0016] Both the drain D and the source S are connected to 0V.

[0017] The voltage difference between the negative erase voltage and the positive erase voltage causes the stored charge in each of the floating gates 104 to be erased.

[0018] When programming the storage unit 101:

[0019] The control gate line CG is connected to the positive programming voltage. The positive programming voltage can be equal to or greater than the positive erase voltage.

[0020] The word line WL is connected to a second positive voltage, which is greater than or equal to the third threshold voltage of the second gate structure 103.

[0021] The source S is connected to a third positive voltage.

[0022] The drain D is connected to the programming current; the third positive voltage is greater than the second positive voltage, and the positive erase voltage is greater than the third positive voltage.

[0023] When reading from the storage unit 101:

[0024] The control gate line CG is connected to 0V.

[0025] The word line WL is connected to the fourth positive voltage.

[0026] The source electrode S is connected to 0V.

[0027] The drain D will output current.

[0028] Table 1 provides the specific parameters for operating the storage cell 101 in the existing memory:

[0029] Table 1

[0030] programming 8 1.5 5 Idp erase -7 8 0 0 Read 0 2.5 0 I

[0031] In Table 1, the negative erase voltage is equal to -7V, the positive erase voltage is equal to 8V; the second positive voltage is equal to 1.5V, the third positive voltage is equal to 5V, Idp represents the programming current; the fourth positive voltage is equal to 2.5V, and I represents the read current output by the drain D.

[0032] like Figure 3 As shown, in the array unit 301: each of the memory cells 101 is arranged in a row, the control gate 105 of each of the memory cells 101 is connected to the corresponding control gate line CG, and the second gate structure 103 of each of the memory cells 101 is connected to the corresponding local word line.

[0033] In the array structure, each array unit 301 in the same row shares the same row of control gate lines CG.

[0034] Each array unit 301 in the same row has its local word line independently configured. Each local word line in the same row is connected to the main word line MWL of the same row via a corresponding first select transistor 302. The gate of each first select transistor 302 is connected to a corresponding first select signal line. Each array unit 301 in the same row has two local word lines, labeled LWL0 and LWL1 respectively. Figure 3 The image shows two array units 301 and two first selection transistors 302, with the corresponding first selection signal lines labeled CSL0 and CSL1, respectively. Figure 3 It can be seen that the word line WL of each of the storage units 101 is implemented by the main word line MWL and the local word line LWL together.

[0035] The selected array cell 301 is designated as the selected cell, and the unselected array cells 301 in the same row as the selected cell are designated as unselected cells. Figure 3 The following explanation uses the array cell corresponding to the local word line LWL0 as the selected cell and the array cell corresponding to the local word line LWL1 as the unselected cell as examples. Figure 3 In the table, the selected unit is a storage unit including data bit a, and the unselected unit is a storage unit including data bit b. When performing an erase operation on the selected unit according to Table 1, there is often a certain erase effect on the unselected unit as well, so there is an erase risk. That is, when erasing data bit a, data bit b may also be adversely affected, as explained below:

[0036] Combining the operations on data bit a and data bit b together results in the operations described in Table 2 below:

[0037] Table 2

[0038]

[0039] In Table 2, LWL0 represents the word line WL of the memory cell corresponding to data bit "a"; LWL1 represents the word line WL of the memory cell corresponding to data bit "b". For operation "a", the values ​​of CG, LWL0, and LWL1 in Table 2 differ slightly from those in Table 1. The actual values ​​should be selected according to actual needs. It can be seen that for operation "b", during the erase operation of "a", LWL1 (V) is floating. Thus, the voltage difference between CG and LWL1 is the difference between -7V and the floating value. However, in practice, because the existing method does not control the floating voltage of LWL1, the floating voltage of LWL1 may fluctuate significantly. This can cause a large difference between -7V and the floating value of LWL1, creating a risk during the erase operation of "b". Therefore, in the existing technology, there is a certain risk associated with unselected LWLFloating values ​​in the same row during the erase state. Summary of the Invention

[0040] The technical problem to be solved by the present invention is to provide an EEPROM that can reduce the risk of erasing unselected array cells in the same row during the erasure of selected array cells. To this end, the present invention also provides an EEPROM operation method.

[0041] Therefore, the present invention provides an EEPROM comprising multiple storage cells, wherein the multiple storage cells form an array cell, and the multiple array cells are arranged to form an array structure of the EEPROM.

[0042] Each of the aforementioned memory cells employs a discrete-gate floating-gate device.

[0043] The split-gate floating gate device includes: a source region and a drain region, a plurality of split first gate structures with floating gates located between the source region and the drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0044] In the array unit: the memory cells are arranged in a row, the control gate of each memory cell is connected to the corresponding control gate line, and the second gate structure of each memory cell is connected to the corresponding local word line.

[0045] In the array structure, each array element in the same row shares the same row of control gate lines.

[0046] The local word lines of each array unit in the same row are independently configured, and the local word lines of each array unit in the same row are respectively connected to the main word line of the same row through corresponding first selection transistors. The gate of each first selection transistor is connected to the corresponding first selection signal line.

[0047] The selected array cell is designated as the selected cell, and the unselected array cells in the same row as the selected cell are designated as unselected cells. The erase process is set to an initial stage, a word line power-on stage, and an erase stage.

[0048] In the initial stage:

[0049] The main word line is kept at ground potential, and the control gate line is kept at ground potential.

[0050] The first selection signal line of the selected unit is applied to a first voltage, and then rises to a second voltage after the first voltage is maintained for a set time. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube to be fully turned on.

[0051] The first selection signal line of the unselected cell is given the first voltage, which is then held for a set time before dropping to the ground potential. The first voltage causes the first selection tube to partially open and sets the voltage of the local word line of the unselected cell to the ground potential of the main word line.

[0052] During the power-on phase of the word line:

[0053] The main word line gradually rises from the ground potential to the positive erase voltage.

[0054] The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is equal to the voltage of the main word line.

[0055] The first selection signal line of the unselected unit is kept at ground potential, the first selection transistor of the unselected unit is turned off, and the local word line of the unselected unit is floated at ground potential.

[0056] The control grid line is kept at ground potential.

[0057] During the erasure phase:

[0058] The main word line is maintained at a positive erase voltage.

[0059] The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is maintained at the positive erase voltage.

[0060] The first selection signal line of the unselected unit remains at ground potential.

[0061] The control gate line drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete.

[0062] The first selection signal line of the unselected cell is kept at ground potential, the first selection transistor of the unselected cell is turned off, the local word line of the unselected cell is floating, and the coupling between the control gate line and the local word line of the unselected cell causes the local word line of the unselected cell to float below the ground potential.

[0063] Each of the selected storage cells is erased under the voltage difference between the positive erase voltage and the negative erase voltage.

[0064] The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each memory cell of the unselected cell being erased.

[0065] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0066] A further improvement is that the separated gate floating gate device is an N-type device, and both the source region and the drain region are composed of N+ regions.

[0067] The P-type doped channel region is located between the source region and the drain region and is covered by each of the first gate structure and the second gate structure.

[0068] A further improvement is that the wiring structure of the EEPROM includes:

[0069] Each of the first selection tubes of each array unit in the same row is disposed in a selection module, which is disposed at the first end of the array row composed of the array units.

[0070] The control grid lines extend from the selection module into each of the array cells.

[0071] The local word line of each array unit extends between the selection module and the corresponding array unit.

[0072] The control gate line and the local word line of each array cell are parallel and have parasitic capacitance, which couples the control gate line and the first selection signal line of the unselected cell during the erase phase.

[0073] A further improvement is that the number of storage units in the array unit includes eight.

[0074] A further improvement is that, during the erasure process, both the source and drain regions of each of the memory cells are grounded.

[0075] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0076] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0077] To solve the above-mentioned technical problems, the EEPROM operation method provided by the present invention includes an EEPROM comprising multiple storage units, an array unit composed of the multiple storage units, and an array structure of the EEPROM formed by arranging the multiple array units.

[0078] Each of the aforementioned memory cells employs a discrete-gate floating-gate device.

[0079] The split-gate floating gate device includes: a source region and a drain region, a plurality of split first gate structures with floating gates located between the source region and the drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0080] In the array unit: the memory cells are arranged in a row, the control gate of each memory cell is connected to the corresponding control gate line, and the second gate structure of each memory cell is connected to the corresponding local word line.

[0081] In the array structure, each array element in the same row shares the same row of control gate lines.

[0082] The local word lines of each array unit in the same row are independently configured, and the local word lines of each array unit in the same row are respectively connected to the main word line of the same row through corresponding first selection transistors. The gate of each first selection transistor is connected to the corresponding first selection signal line.

[0083] The selected array cell is designated as the selected cell, and the unselected array cells in the same row as the selected cell are designated as unselected cells; the operation method includes an erase operation, the erase operation process includes an initial stage, a word line power-on stage and an erase stage.

[0084] In the initial stage:

[0085] The main word line is kept at ground potential, and the control gate line is kept at ground potential.

[0086] The first selection signal line of the selected unit is applied to a first voltage, and then rises to a second voltage after the first voltage is maintained for a set time. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube to be fully turned on.

[0087] The first selection signal line of the unselected cell is given the first voltage, which is then held for a set time before dropping to the ground potential. The first voltage causes the first selection tube to partially open and sets the voltage of the local word line of the unselected cell to the ground potential of the main word line.

[0088] During the power-on phase of the word line:

[0089] The main word line gradually rises from the ground potential to the positive erase voltage.

[0090] The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is equal to the voltage of the main word line.

[0091] The first selection signal line of the unselected unit is kept at ground potential, the first selection transistor of the unselected unit is turned off, and the local word line of the unselected unit is floated at ground potential.

[0092] The control grid line is kept at ground potential.

[0093] During the erasure phase:

[0094] The main word line is maintained at a positive erase voltage.

[0095] The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is maintained at the positive erase voltage.

[0096] The first selection signal line of the unselected unit remains at ground potential.

[0097] The control gate line drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete.

[0098] The first selection signal line of the unselected cell is kept at ground potential, the first selection transistor of the unselected cell is turned off, the local word line of the unselected cell is floating, and the coupling between the control gate line and the local word line of the unselected cell causes the local word line of the unselected cell to float below the ground potential.

[0099] Each of the selected storage cells is erased under the voltage difference between the positive erase voltage and the negative erase voltage.

[0100] The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each memory cell of the unselected cell being erased.

[0101] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0102] A further improvement is that the separated gate floating gate device is an N-type device, and both the source region and the drain region are composed of N+ regions.

[0103] The P-type doped channel region is located between the source region and the drain region and is covered by each of the first gate structure and the second gate structure.

[0104] A further improvement is that the wiring structure of the EEPROM includes:

[0105] Each of the first selection tubes of each array unit in the same row is disposed in a selection module, which is disposed at the first end of the array row composed of the array units.

[0106] The control grid lines extend from the selection module into each of the array cells.

[0107] The local word line of each array unit extends between the selection module and the corresponding array unit.

[0108] The control gate line and the local word line of each array cell are parallel and have parasitic capacitance, which couples the control gate line and the first selection signal line of the unselected cell during the erase phase.

[0109] A further improvement is that the number of storage units in the array unit includes eight.

[0110] A further improvement is that, during the erasure process, both the source and drain regions of each of the memory cells are grounded.

[0111] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate;

[0112] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0113] A further improvement is that the floating gate is made of polysilicon, the control gate is made of polysilicon, and the word line gate is made of polysilicon.

[0114] This invention features a special setting for the EEPROM erasure process. During the erasure process, before the main word line begins the initial stage described above, a pulse of magnitude one voltage is applied to the first selection signal line of the unselected cell, causing the voltage of the local word line of the unselected cell to be set to the ground potential of the main word line. Thus, as the main word line begins to rise and after its rise is complete, the voltage of the local word line of the unselected cell remains floating, but the floating voltage of the local word line of the unselected cell can be well controlled. Furthermore, during the erasure stage, by utilizing the negative erase voltage of the control gate line and the coupling effect between the control gate line and the local word line of the unselected cell, the local word line of the unselected cell can be kept below the ground potential. This allows the local word line of the unselected cell to be kept at a low voltage during the erasure process, thereby reducing the voltage difference between the local word line and the negative erase voltage and thus reducing the risk of erasing the memory cells of the unselected cells, preventing erasure errors.

[0115] This invention can route according to the coupling requirements of the control gate line and the local word line of the unselected cell during the erasure phase, so that the control gate line and the adjacent local word line are parallel and have the parasitic capacitance required for coupling. Finally, by combining the power-on sequence of the word lines, including the main word line and the local word line, and the parasitic capacitance between the control gate line and the adjacent local word line, the risk of erasing each memory cell of the unselected cell can be reduced without making any other additional modifications. Therefore, this invention also has the advantages of simple operation and low cost. Attached Figure Description

[0116] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0117] Figure 1 This is a schematic diagram of the circuit structure of an existing EEPROM storage cell;

[0118] Figure 2 This is a cross-sectional structural diagram of an existing EEPROM storage cell;

[0119] Figure 3 This is a diagram of the existing EEPROM array structure;

[0120] Figure 4 This is a diagram of the array structure of the EEPROM according to a preferred embodiment of the present invention;

[0121] Figure 5 This is a diagram showing the power-on sequence of word lines and control gate lines in the erase operation of the EEPROM according to an embodiment of the present invention. Detailed Implementation

[0122] The EEPROM of this embodiment does not require changes to the structure of the storage cell 101. Therefore, the circuit structure of the storage cell 101 of the EEPROM in this embodiment is still referred to. Figure 1Please refer to the diagram and cross-sectional structure shown. Figure 2 The structure of array unit 301 is still referred to above. Figure 3 As shown, the EEPROM of this embodiment includes multiple storage units 101, an array unit 301 composed of the multiple storage units 101, and an array structure of the EEPROM formed by arranging the multiple array units 301.

[0123] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0124] like Figure 2 As shown, the split-gate floating gate device includes: a source region 205 and a drain region 206, a plurality of split first gate structures with floating gates 104 located between the source region 205 and the drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0125] In this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the designations 102a and 102b.

[0126] The separated gate floating gate device is an N-type device, and both the source region 205 and the drain region 206 are composed of N+ regions.

[0127] The P-type doped channel region is located between the source region 205 and the drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The source region 205 and the drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the source region 205 and the drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0128] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0129] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0130] In some embodiments, the floating gate 104 is made of polysilicon, the control gate 105 is made of polysilicon, and the word line gate 106 is made of polysilicon. The tunneling dielectric layer 202 is made of oxide, the control gate dielectric layer 203 is made of oxide, and the word line gate dielectric layer 204 is made of oxide.

[0131] like Figure 3 As shown, in the array unit 301: each of the memory cells 101 is arranged in a row, the control gate 105 of each of the memory cells 101 is connected to the corresponding control gate line CG, and the second gate structure 103 of each of the memory cells 101 is connected to the corresponding local word line.

[0132] In the array structure, each array unit 301 in the same row shares the same row of control gate lines CG.

[0133] The local word lines of each array unit 301 in the same row are independently configured. The local word lines of each array unit 301 in the same row are respectively connected to the main word line MWL of the same row through the corresponding first selection transistor 302. The gate of each first selection transistor 302 is connected to the corresponding first selection signal line.

[0134] In this embodiment of the invention, each array unit 301 in the same row has two local word lines, which are marked as LWL0 and LWL1 respectively. Figure 3 The image shows two array units 301 and two first selection transistors 302, with the corresponding first selection signal lines marked CSL0 and CSL1, respectively.

[0135] The selected array cell 301 is designated as the selected cell, and the unselected array cells 301 in the same row as the selected cell are designated as unselected cells. Figure 3 In this example, the array cell corresponding to the local word line LWL0 is taken as the selected cell and the array cell corresponding to the local word line LWL1 is taken as the unselected cell. Figure 5 As shown, the erasure process is set up with an initial stage, a word line power-on stage, and an erasure stage. Figure 5 In the process, the stage before time t2 is the initial stage, the stage between time t2 and t3 is the word line power-on stage, and the stage after time t3 is the erasure stage.

[0136] In the initial stage:

[0137] The main word line MWL is kept at ground potential, and the control gate line CG is kept at ground potential.

[0138] The first selection signal line, namely the first selection signal line CSL0, of the selected unit is applied to a first voltage, and then after the first voltage is maintained for a set time, it rises to a second voltage. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube 302 to be fully turned on. Figure 5 At time t1, the first selection signal line CSL0 begins to rise from a first voltage to a second voltage. The voltage of the local word line LWL0 of the selected unit is set to the ground potential of the main word line MWL.

[0139] The first selection signal line CSL1 of the unselected unit is given the first voltage, and then drops to the ground potential after the first voltage is maintained for a set time. The first voltage causes the first selection tube 302 to partially turn on and sets the voltage of the local word line LWL1 of the unselected unit to the ground potential of the main word line MWL. Figure 5 At time t1, the first selection signal line CSL1 drops the first voltage to the ground voltage.

[0140] During the power-on phase of the word line:

[0141] The main word line MWL gradually rises from the ground potential to the positive erase voltage. In some embodiments, the positive erase voltage is 8V. The first select signal line CSL0 of the selected cell remains at the second voltage, and the voltage of the local word line LWL0 of the selected cell is equal to the voltage of the main word line MWL, and also gradually rises to the positive erase voltage.

[0142] The first selection signal line of the unselected unit is kept at ground potential, the first selection tube 302 of the unselected unit is turned off, and the local word line of the unselected unit is floated at ground potential.

[0143] The interval between time t1 and t2 is short. After time t1, the local word line LWL1 of the unselected unit begins to float. When floating, the voltage of the local word line LWL1 will be affected by the coupling of the adjacent signal line and will change to a certain extent. For example, after the voltage of the local word line LWL0 rises, the voltage of the local word line LWL1 will also be slightly higher than the ground potential. Figure 5 In this process, the potential of the main word line MWL rises to the positive erase voltage from time t2 to t3. Between time t1 and t3, the local word line LWL1 is in a floating state and is marked as Floating.

[0144] The control gate line CG is kept at ground potential. Similarly, due to the coupling effect, when the voltage of the local word line LWL0 rises, the actual potential of the control gate line CG will also rise slightly from the ground potential due to the coupling effect.

[0145] During the erasure phase:

[0146] The main word line MWL is maintained at a positive erase voltage.

[0147] The first selection signal line CSL0 of the selected unit is maintained at the second voltage, and the voltage of the local word line LWL0 of the selected unit is maintained at the positive erase voltage.

[0148] The first selection signal line CSL1 of the unselected unit remains at ground potential.

[0149] The control gate line CG drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete. In some embodiments, the negative erase voltage is -7V.

[0150] The first selection signal line CSL1 of the unselected unit is kept at ground potential, the first selection transistor 302 of the unselected unit is turned off, the local word line LWL1 of the unselected unit is floating, and the coupling between the control gate line CG and the local word line LWL1 of the unselected unit causes the local word line LWL1 of the unselected unit to float below the ground potential. Figure 5 As shown, starting at time t3, the local word line LWL1 will drop below the ground potential. This is due to the coupling of the negative erase voltage to the local word line LWL1. After the local word line LWL1 is coupled to a negative potential, it will slowly leak current to a very low voltage. Figure 5 After time t3, the local word line LWL1 is floating, indicated by Floating. The value is also marked as -0.1V to -0.3V in parentheses. In other words, in some embodiments, the local word line LWL1 will float at -0.1V to -0.3V.

[0151] During the erasure process, the source region 205 and drain region 206 of each of the memory cells 101 are grounded. Each of the selected memory cells 101 is erased under the voltage difference between the positive erase voltage and the negative erase voltage.

[0152] The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each of the memory cells 101 of the unselected cell being erased.

[0153] In some preferred embodiments, such as Figure 4 The diagram shown is an array structure diagram of an EEPROM according to a preferred embodiment of the present invention; the wiring structure of the EEPROM includes:

[0154] Each of the first selection tubes 302 of each array unit 301 in the same row is disposed in the selection module 303, which is disposed at the first end of the array row composed of the array units 301.

[0155] The array unit 301 contains eight storage units 101. Figure 4 In this context, the selection module 303 is also represented by Byte select.

[0156] The control gate line CG extends from the selection module 303 into each of the array units 301. Figure 4 The image shows two array units 301, which are denoted as Array unit0 and Array unit1, respectively.

[0157] The local word line of each array unit 301 extends between the selection module 303 and the corresponding array unit 301.

[0158] The control gate line CG is parallel to the local word line of each array cell 301 and has a parasitic capacitance 304, which couples the control gate line CG to the first selection signal line of the unselected cell during the erase phase.

[0159] This invention provides a special setting for the EEPROM erasure process. During the erasure process, before the main word line MWL begins the initial stage described above, a pulse of magnitude one voltage is applied to the first selection signal line of the unselected cell, causing the voltage of the local word line of the unselected cell to be set to the ground potential of the main word line MWL. Thus, as the main word line MWL begins to rise and after its rise is completed, the voltage of the local word line of the unselected cell remains floating, but the floating voltage of the local word line of the unselected cell can be well controlled. Moreover, during the erasure stage, by utilizing the negative erase voltage of the control gate line CG and the coupling effect between the control gate line CG and the local word line of the unselected cell, the local word line of the unselected cell can be kept below the ground potential. This allows the local word line of the unselected cell to be kept at a low voltage during the erasure process, thereby reducing the voltage difference between the local word line and the negative erase voltage and thus reducing the risk of each memory cell 101 of the unselected cell being erased, preventing erasure errors.

[0160] The embodiments of the present invention can perform routing according to the coupling requirements of the control gate line CG and the local word line of the unselected cell during the erasure phase, so that the control gate line CG and the adjacent local word line are parallel and thus have the parasitic capacitance 304 required for coupling. Finally, by combining the power-on sequence of the word lines including the main word line MWL and the local word lines and the parasitic capacitance 304 between the control gate line CG and the adjacent local word lines, the risk of erasing each memory cell 101 of the unselected cell can be reduced without making any other additional modifications. Therefore, the embodiments of the present invention also have the advantages of simple operation and low cost.

[0161] In the EEPROM operation method of this embodiment, the EEPROM includes a plurality of storage units 101, the plurality of storage units 101 form an array unit 301, and the plurality of array units 301 are arranged to form an array structure of the EEPROM.

[0162] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0163] like Figure 2 As shown, the split-gate floating gate device includes: a source region 205 and a drain region 206, a plurality of split first gate structures with floating gates 104 located between the source region 205 and the drain region 206, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0164] In the method of this embodiment of the invention, the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are respectively represented by the markings 102a and 102b.

[0165] The separated gate floating gate device is an N-type device, and both the source region 205 and the drain region 206 are composed of N+ regions.

[0166] The P-type doped channel region is located between the source region 205 and the drain region 206 and is covered by each of the first gate structure and the second gate structure 103. The source region 205 and the drain region 206 are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the source region 205 and the drain region 206 or by further doping on the P-type semiconductor substrate 201.

[0167] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0168] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0169] In some embodiments, the floating gate 104 is made of polysilicon, the control gate 105 is made of polysilicon, and the word line gate 106 is made of polysilicon. The tunneling dielectric layer 202 is made of oxide, the control gate dielectric layer 203 is made of oxide, and the word line gate dielectric layer 204 is made of oxide.

[0170] like Figure 3 As shown, in the array unit 301: each of the memory cells 101 is arranged in a row, the control gate 105 of each of the memory cells 101 is connected to the corresponding control gate line CG, and the second gate structure 103 of each of the memory cells 101 is connected to the corresponding local word line.

[0171] In the array structure, each array unit 301 in the same row shares the same row of control gate lines CG.

[0172] The local word lines of each array unit 301 in the same row are independently configured. The local word lines of each array unit 301 in the same row are respectively connected to the main word line MWL of the same row through the corresponding first selection transistor 302. The gate of each first selection transistor 302 is connected to the corresponding first selection signal line.

[0173] In the method of this embodiment of the invention, each array unit 301 in the same row has two local word lines, which are marked as LWL0 and LWL1 respectively. Figure 3 The image shows two array units 301 and two first selection transistors 302, with the corresponding first selection signal lines marked CSL0 and CSL1, respectively.

[0174] The selected array cell 301 is designated as the selected cell, and the unselected array cells 301 in the same row as the selected cell are designated as unselected cells. Figure 3 In this example, the array cell corresponding to the local word line LWL0 is taken as the selected cell and the array cell corresponding to the local word line LWL1 is taken as the unselected cell. Figure 5 As shown, the operation method includes an erasure operation, and the process of the erasure operation includes an initial stage, a word line power-on stage, and an erasure stage. Figure 5 In the process, the stage before time t2 is the initial stage, the stage between time t2 and t3 is the word line power-on stage, and the stage after time t3 is the erasure stage.

[0175] In the initial stage:

[0176] The main word line MWL is kept at ground potential, and the control gate line CG is kept at ground potential.

[0177] The first selection signal line, namely the first selection signal line CSL0, of the selected unit is applied to a first voltage, and then after the first voltage is maintained for a set time, it rises to a second voltage. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube 302 to be fully turned on. Figure 5 At time t1, the first selection signal line CSL0 begins to rise from a first voltage to a second voltage. The voltage of the local word line LWL0 of the selected unit is set to the ground potential of the main word line MWL.

[0178] The first selection signal line CSL1 of the unselected unit is given the first voltage, and then drops to the ground potential after the first voltage is maintained for a set time. The first voltage causes the first selection tube 302 to partially turn on and sets the voltage of the local word line LWL1 of the unselected unit to the ground potential of the main word line MWL. Figure 5 At time t1, the first selection signal line CSL1 drops the first voltage to the ground voltage.

[0179] During the power-on phase of the word line:

[0180] The main word line MWL gradually rises from the ground potential to the positive erase voltage. In some embodiments, the positive erase voltage is 8V. The first select signal line CSL0 of the selected cell remains at the second voltage, and the voltage of the local word line LWL0 of the selected cell is equal to the voltage of the main word line MWL, and also gradually rises to the positive erase voltage.

[0181] The first selection signal line of the unselected unit is kept at ground potential, the first selection tube 302 of the unselected unit is turned off, and the local word line of the unselected unit is floated at ground potential.

[0182] The interval between time t1 and t2 is short. After time t1, the local word line LWL1 of the unselected unit begins to float. When floating, the voltage of the local word line LWL1 will be affected by the coupling of the adjacent signal line and will change to a certain extent. For example, after the voltage of the local word line LWL0 rises, the voltage of the local word line LWL1 will also be slightly higher than the ground potential. Figure 5 In this process, the potential of the main word line MWL rises to the positive erase voltage from time t2 to t3. Between time t1 and t3, the local word line LWL1 is in a floating state and is marked as Floating.

[0183] The control gate line CG is kept at ground potential. Similarly, due to the coupling effect, when the voltage of the local word line LWL0 rises, the actual potential of the control gate line CG will also rise slightly from the ground potential due to the coupling effect.

[0184] During the erasure phase:

[0185] The main word line MWL is maintained at a positive erase voltage.

[0186] The first selection signal line CSL0 of the selected unit is maintained at the second voltage, and the voltage of the local word line LWL0 of the selected unit is maintained at the positive erase voltage.

[0187] The first selection signal line CSL1 of the unselected unit remains at ground potential.

[0188] The control gate line CG drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete. In some embodiments, the negative erase voltage is -7V.

[0189] The first selection signal line CSL1 of the unselected unit is kept at ground potential, the first selection transistor 302 of the unselected unit is turned off, the local word line LWL1 of the unselected unit is floating, and the coupling between the control gate line CG and the local word line LWL1 of the unselected unit causes the local word line LWL1 of the unselected unit to float below the ground potential. Figure 5 As shown, starting at time t3, the local word line LWL1 will drop below the ground potential. This is due to the coupling of the negative erase voltage to the local word line LWL1. After the local word line LWL1 is coupled to a negative potential, it will slowly leak current to a very low voltage. Figure 5 After time t3, the local word line LWL1 is floating, indicated by Floating. The value is -0.1V to -0.3V, which means that in some embodiments, the local word line LWL1 will float at -0.1V to -0.3V.

[0190] During the erasure process, the source region 205 and drain region 206 of each of the memory cells 101 are grounded. Each of the selected memory cells 101 is erased under the voltage difference between the positive erase voltage and the negative erase voltage.

[0191] The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each of the memory cells 101 of the unselected cell being erased.

[0192] In some preferred embodiments of the method, such as Figure 4 The diagram shown is an array structure diagram of an EEPROM according to a preferred embodiment of the present invention; the wiring structure of the EEPROM includes:

[0193] Each of the first selection tubes 302 of each array unit 301 in the same row is disposed in the selection module 303, which is disposed at the first end of the array row composed of the array units 301.

[0194] The array unit 301 contains eight storage units 101. Figure 4 In this context, the selection module 303 is also represented by Byte select.

[0195] The control gate line CG extends from the selection module 303 into each of the array units 301. Figure 4 The image shows two array units 301, which are denoted as Array unit0 and Array unit1, respectively.

[0196] The local word line of each array unit 301 extends between the selection module 303 and the corresponding array unit 301.

[0197] The control gate line CG is parallel to the local word line of each array cell 301 and has a parasitic capacitance 304, which couples the control gate line CG to the first selection signal line of the unselected cell during the erase phase.

[0198] In the method of this invention embodiment, the programming and reading operations can be exactly the same as the existing methods. In the erasure operation, the power-on sequence of the local word lines LWL0 and LWL1 and the control gate line CG can be set, and it is not necessary to change the magnitude of the positive erasure voltage and the negative erasure voltage.

[0199] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An EEPROM, characterized in that, It includes multiple storage units, an array unit composed of the multiple storage units, and an array structure of EEPROM formed by arranging the multiple array units; Each of the aforementioned memory cells employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a source region and a drain region, a plurality of split first gate structures with floating gates located between the source region and the drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate; In the array unit: each of the memory cells is arranged in a row, the control gate of each of the memory cells is connected to the corresponding control gate line, and the second gate structure of each of the memory cells is connected to the corresponding local word line; In the array structure, each array unit in the same row shares the same row of control gate lines; The local word lines of each array unit in the same row are set independently, and the local word lines of each array unit in the same row are respectively connected to the main word line of the same row through the corresponding first selection transistor. The gate of each first selection transistor is connected to the corresponding first selection signal line. The selected array cell is designated as the selected cell, and the unselected array cells in the same row as the selected cell are designated as unselected cells. The erasure process is set to an initial stage, a word line power-on stage, and an erasure stage. In the initial stage: The main word line is kept at ground potential, and the control gate line is kept at ground potential; The first selection signal line of the selected unit is applied to a first voltage and then rises to a second voltage after the first voltage is maintained for a set time. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube to be fully turned on. The first selection signal line of the unselected cell is given the first voltage, and then drops to the ground potential after the first voltage is held for a set time. The first voltage causes the first selection tube to partially open and sets the voltage of the local word line of the unselected cell to the ground potential of the main word line. During the power-on phase of the word line: The main word line gradually rises from the ground potential to the positive erase voltage; The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is equal to the voltage of the main word line; The first selection signal line of the unselected cell remains at ground potential, the first selection transistor of the unselected cell is turned off, and the local word line of the unselected cell is floated. The control gate line is kept at ground potential; During the erasure phase: The main word line is maintained at a positive erase voltage; The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is maintained at the positive erase voltage; The first selection signal line of the unselected unit remains at ground potential; The control gate line drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete; The first selection signal line of the unselected cell is kept at ground potential, the first selection transistor of the unselected cell is turned off, the local word line of the unselected cell is floating, and the coupling between the control gate line and the local word line of the unselected cell causes the local word line of the unselected cell to float below the ground potential. Each of the selected unit's storage cells is erased under the voltage difference between the positive erase voltage and the negative erase voltage; The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each memory cell of the unselected cell being erased.

2. The EEPROM as described in claim 1, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

3. The EEPROM as described in claim 2, characterized in that: The separated gate floating gate device is an N-type device, and both the source region and the drain region are composed of N+ regions. The P-type doped channel region is located between the source region and the drain region and is covered by each of the first gate structure and the second gate structure.

4. The EEPROM as described in claim 1, characterized in that: The wiring structure of the EEPROM includes: Each of the first selection tubes of each array unit in the same row is disposed in a selection module, and the selection module is disposed at the first end of the array row composed of the array units; The control grid lines extend from the selection module into each of the array cells; The local word line of each array unit extends between the selection module and the corresponding array unit; The control gate line and the local word line of each array cell are parallel and have parasitic capacitance, which couples the control gate line and the first selection signal line of the unselected cell during the erase phase.

5. The EEPROM as described in claim 1 or 4, characterized in that: The array unit contains eight storage units.

6. The EEPROM as described in claim 1, characterized in that: During the erasure process, the source and drain regions of each memory cell are grounded.

7. The EEPROM as described in claim 1, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

8. An EEPROM operation method, characterized in that: EEPROM includes multiple storage cells, which form an array cell, and the array cells are arranged to form an EEPROM array structure. Each of the aforementioned memory cells employs a discrete-gate floating-gate device; The split-gate floating gate device includes: a source region and a drain region, a plurality of split first gate structures with floating gates located between the source region and the drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate; In the array unit: each of the memory cells is arranged in a row, the control gate of each of the memory cells is connected to the corresponding control gate line, and the second gate structure of each of the memory cells is connected to the corresponding local word line; In the array structure, each array unit in the same row shares the same row of control gate lines; The local word lines of each array unit in the same row are set independently, and the local word lines of each array unit in the same row are respectively connected to the main word line of the same row through the corresponding first selection transistor. The gate of each first selection transistor is connected to the corresponding first selection signal line. The selected array cell is designated as the selected cell, and the unselected array cells in the same row as the selected cell are designated as unselected cells; the operation method includes an erase operation, and the erase operation process includes an initial stage, a word line power-on stage, and an erase stage; In the initial stage: The main word line is kept at ground potential, and the control gate line is kept at ground potential; The first selection signal line of the selected unit is applied to a first voltage and then rises to a second voltage after the first voltage is maintained for a set time. The second voltage is greater than the first voltage, and the second voltage causes the first selection tube to be fully turned on. The first selection signal line of the unselected cell is given the first voltage, and then drops to the ground potential after the first voltage is held for a set time. The first voltage causes the first selection tube to partially open and sets the voltage of the local word line of the unselected cell to the ground potential of the main word line. During the power-on phase of the word line: The main word line gradually rises from the ground potential to the positive erase voltage; The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is equal to the voltage of the main word line; The first selection signal line of the unselected cell remains at ground potential, the first selection transistor of the unselected cell is turned off, and the local word line of the unselected cell is floated. The control gate line is kept at ground potential; During the erasure phase: The main word line is maintained at a positive erase voltage; The first selection signal line of the selected unit is maintained at the second voltage, and the voltage of the local word line of the selected unit is maintained at the positive erase voltage; The first selection signal line of the unselected unit remains at ground potential; The control gate line drops from the ground potential to a negative erase voltage and remains at the negative erase voltage after the drop is complete; The first selection signal line of the unselected cell is kept at ground potential, the first selection transistor of the unselected cell is turned off, the local word line of the unselected cell is floating, and the coupling between the control gate line and the local word line of the unselected cell causes the local word line of the unselected cell to float below the ground potential. Each of the selected unit's storage cells is erased under the voltage difference between the positive erase voltage and the negative erase voltage; The local word line of the unselected cell is floated below the ground potential to reduce the voltage difference between the local word line and the negative erase voltage, thereby reducing the risk of each memory cell of the unselected cell being erased.

9. The EEPROM operation method as described in claim 8, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

10. The EEPROM operation method as described in claim 9, characterized in that: The separated gate floating gate device is an N-type device, and both the source region and the drain region are composed of N+ regions. The P-type doped channel region is located between the source region and the drain region and is covered by each of the first gate structure and the second gate structure.

11. The EEPROM operation method as described in claim 8, characterized in that: The wiring structure of the EEPROM includes: Each of the first selection tubes of each array unit in the same row is disposed in a selection module, and the selection module is disposed at the first end of the array row composed of the array units; The control grid lines extend from the selection module into each of the array cells; The local word line of each array unit extends between the selection module and the corresponding array unit; The control gate line and the local word line of each array cell are parallel and have parasitic capacitance, which couples the control gate line and the first selection signal line of the unselected cell during the erase phase.

12. The EEPROM operation method as described in claim 8 or 11, characterized in that: The array unit contains eight storage units.

13. The EEPROM operation method as described in claim 8, characterized in that: During the erase operation, the source and drain regions of each memory cell are grounded.

14. The EEPROM operation method as described in claim 8, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

15. The EEPROM operation method as described in claim 14, characterized in that: The floating gate is made of polysilicon, the control gate is made of polysilicon, and the word line gate is made of polysilicon.

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