Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and an operating method of a semiconductor memory device. The semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation on a selected memory cell among the plurality of memory cells. The control logic controls the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform the program operation on the selected memory cell by using a first program voltage determined based on a first step voltage during a first program period, and controls the peripheral circuit to perform the program operation on the selected memory cell by using a second program voltage determined based on a second step voltage different from the first step voltage during a second program period after the first program period.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0011443, filed on January 26, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to electronic devices, and more specifically to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Memory devices can be formed as a two-dimensional structure in which strings are arranged horizontally on a semiconductor substrate, or as a three-dimensional structure in which strings are arranged vertically on a semiconductor substrate. Three-dimensional memory devices are semiconductor memory devices designed to overcome the integration limitations of two-dimensional semiconductor memory devices and can include multiple memory cells vertically stacked on a semiconductor substrate. Summary of the Invention

[0005] According to one embodiment of this disclosure, a semiconductor memory device is provided, comprising: a memory cell array including a plurality of memory cells; peripheral circuitry configured to perform a programming operation on a selected memory cell among the plurality of memory cells; and control logic configured to control the programming operation of the peripheral circuitry, wherein during a first programming period, the control logic controls the peripheral circuitry to perform a programming operation on the selected memory cell by using a first programming voltage determined based on a first step voltage, and during a second programming period following the first programming period, the control logic controls the peripheral circuitry to perform a programming operation on the selected memory cell by using a second programming voltage determined based on a second step voltage different from the first step voltage.

[0006] According to one embodiment of the present disclosure, a method for operating a semiconductor memory device is provided, the method including a plurality of programming cycles, wherein at least some of the plurality of programming cycles include: determining a step voltage based on a current programming cycle number, and determining a programming voltage based on the step voltage; applying the programming voltage to a selected memory cell; and performing a verification operation on the selected memory cell. Attached Figure Description

[0007] Examples of embodiments will now be described with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. The same reference numerals always refer to the same element.

[0009] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 It's a diagram. Figure 1 A diagram illustrating an embodiment of the memory cell array shown.

[0011] Figure 3 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory cell array shown.

[0012] Figure 4 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory cell array shown.

[0013] Figure 5 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory cell array shown.

[0014] Figure 6 The figure shows the distribution of threshold voltages in memory cells when the threshold voltage window is widened to improve read margin.

[0015] Figure 7 The diagram is as shown in the reference. Figure 6 The graph shows the programming voltage change for each programming cycle in incremental step pulse programming when the threshold voltage window is widened.

[0016] Figure 8 The diagram is as shown in the reference. Figure 7 The graph describes the phenomenon that programming speed decreases when the initial programming voltage decreases.

[0017] Figure 9 This is a graph illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 10 The diagram is as shown in the reference. Figure 9 The graph shows the increase in programming speed as the step voltage increases during the initial programming stage.

[0019] Figure 11 This is a flowchart illustrating one aspect of an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Figure 12 This is a flowchart illustrating another aspect of the operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0021] Figure 13 It's a diagram. Figure 12 A flowchart of one embodiment of step S210 is shown.

[0022] Figure 14 The illustration shows the determination of one embodiment of the present disclosure. Figure 13 A diagram illustrating the method for specifying the first voltage in step S213.

[0023] Figure 15 The illustration shows the determination of one embodiment of the present disclosure. Figure 13 A flowchart illustrating an embodiment of the first voltage specified in step S213.

[0024] Figure 16 It is illustrated in Figure 13 A diagram illustrating the method for determining the step voltage in step S213.

[0025] Figure 17 It is illustrated in Figure 13 The flowchart shows an embodiment of determining the step voltage in step S213.

[0026] Figure 18 The diagram includes Figure 1 The diagram shows a block diagram of a semiconductor memory device's memory system.

[0027] Figure 19 It's a diagram. Figure 18 A block diagram illustrating an application example of the memory system.

[0028] Figure 20 It is illustrated, including references. Figure 19 A block diagram of the computing system describing the memory system. Detailed Implementation

[0029] The specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0030] The embodiments provide a semiconductor memory device with improved programming speed and a method of operating the semiconductor memory device.

[0031] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0032] refer to Figure 1 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150. The control logic 140 may be implemented in hardware, software, or a combination of both. For example, the control logic 140 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0033] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each memory block among the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells may be non-volatile memory cells and are configured as non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 110 may be configured as a memory cell array with a three-dimensional structure. Each memory cell among the multiple memory cells included in the memory cell array 110 may store at least one bit of data. In one embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell among the multiple memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a three-level cell (TLC) storing 3 bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a four-level cell (QLC) storing 4 bits of data. In some embodiments, the memory cell array 110 may include a plurality of memory cells each storing 5 bits or more of data.

[0034] Address decoder 120, read / write circuit 130, and voltage generator 150 operate as peripheral circuitry for driving memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 operates under the control of control logic 140. Address decoder 120 receives addresses through input / output buffers (not shown) in semiconductor memory device 100.

[0035] Address decoder 120 decodes the block address from the received address. Address decoder 120 selects at least one memory block based on the decoded block address. Furthermore, during a read voltage application operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block, and applies a pass voltage Vpass generated by voltage generator 150 to the other unselected word lines. Furthermore, during a program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word line of the selected memory block, and applies a pass voltage Vpass to the other unselected word lines.

[0036] Address decoder 120 decodes the column address in the received address. Address decoder 120 transmits the decoded column address to read / write circuit 130.

[0037] Read and programming operations on the semiconductor memory device 100 are performed on a page-by-page basis. Addresses received in response to requests for read and programming operations include block addresses, row addresses, and column addresses. Address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by address decoder 120 and provided to read / write circuitry 130.

[0038] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0039] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during a read operation and as a "write circuit" during a write operation. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. To sense the threshold voltage of the memory cells during a read operation or a programming verification operation, the multiple page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cells while sensing changes in the amount of current flowing according to the programming state of the corresponding memory cells via sensing nodes, and latch the sensed current changes as sensed data. The read / write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0040] During a read operation, the read / write circuit 130 temporarily stores the read data by sensing the data in the memory cell, and then outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, for example, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0041] Control logic 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 controls the normal operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals to adjust the precharge potential levels of the sensing nodes of multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110.

[0042] According to various embodiments of the semiconductor memory device and its operation method, since the programming voltage applied to the bit line is adjusted according to the location of the memory cell, the difference between the programming speeds of the memory cells can be reduced, and therefore the programming speed of the semiconductor memory device 100 can be increased. Reference will be made later. Figures 6 to 16 This describes the adjustment of the programming voltage applied to the bit line according to the semiconductor memory device and the method of operating the semiconductor memory device according to embodiments of the present disclosure.

[0043] In response to a control signal output from control logic 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors for receiving internal power supply voltages, and generates multiple voltages by selectively activating the multiple pump capacitors under the control of control logic 140.

[0044] Figure 2 It's a diagram. Figure 1 A diagram illustrating an embodiment of the memory cell array shown.

[0045] refer to Figure 2 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate (not shown). The multiple memory cells may be arranged along the +X, +Y, and +Z directions. The structure of each memory block will be referenced... Figure 3 and Figure 4 To describe in more detail.

[0046] Figure 3 It's a diagram. Figure 1 A diagram illustrating another embodiment of the memory cell array shown.

[0047] refer to Figure 3The first to z-th memory blocks BLK1 to BLKz included in the memory cell array 110_1 are commonly connected to the first to m-th bit lines BL1 to BLm. Figure 3 For ease of description, the diagram illustrates the components included in the first memory block BLK1, one of the multiple memory blocks BLK1 to BLKz, while the components included in each of the other memory blocks BLK2 to BLKz are omitted. It should be understood that each of the other memory blocks BLK2 to BLKz is configured to be identical to the first memory block BLK1.

[0048] The first memory block BLK1 may include multiple cell strings CS1_1 to CS1_m. The first to m-th cell strings CS1_1 to CS1_m are respectively connected to the first to m-th bit lines BL1 to BLm.

[0049] Each of the first to m-th cell strings CS1_1 to CS1_m includes a drain select transistor (DST), a plurality of memory cells MC1 to MCn connected in series, and a source select transistor (SST). The drain select transistor DST is connected to the drain select line DSL1. The first to n-th memory cells MC1 to MCn are respectively connected to the first to n-th word lines WL1 to WLn. The source select transistor SST is connected to the source select line SSL1. The drain side of the drain select transistor DST is connected to the corresponding bit line. The drain select transistors of the first to m-th cell strings CS1_1 to CS1_m are respectively connected to the first to m-th bit lines BL1 to BLm. The source side of the source select transistor SST is connected to the common source line CSL. In one embodiment, the common source line CSL may be commonly connected to the first to z-th memory blocks BLK1 to BLKz.

[0050] The drain select line DSL1, the first to nth word lines WL1 to WLn, and the source select line SSL1 are controlled by the address decoder 120. The common source line CSL can be controlled by the control logic 140. The first to mth bit lines BL1 to BLm are controlled by the read / write circuit 130.

[0051] like Figure 3 As shown, the memory cell array 110 of the semiconductor memory device 100 according to an embodiment of the present disclosure can be configured as a memory cell array 110_1 with a two-dimensional structure. However, in some embodiments, the memory cell array 110 of the semiconductor memory device 100 can be configured as a memory cell array with a three-dimensional structure. Reference will be made later. Figure 4 and Figure 5 To describe a memory cell array with a three-dimensional structure.

[0052] Figure 4 It's a diagram. Figure 1A diagram of another embodiment 110_2 of the memory cell array 110 shown.

[0053] refer to Figure 4 The memory cell array 110_2 includes multiple memory blocks BLK1 to BLKz. Figure 4 For ease of description, the internal configuration of the first memory block BLK1 is illustrated, while the internal configurations of the other memory blocks BLK2 to BLKz are omitted. It should be understood that the second to z-th memory blocks BLK2 to BLKz are configured similarly to the first memory block BLK1.

[0054] refer to Figure 4 The first memory block BLK1 may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the first memory block BLK1, m cell strings are arranged along the row direction (i.e., the +X direction). Although in Figure 4 The diagram illustrates two unit strings arranged along the column direction (i.e., the +Y direction), but this is for ease of description, and it should be understood that three unit strings can be arranged along the column direction.

[0055] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0056] The select transistors SST and DST, and the memory cells MC1 to MCn, can have structures similar to each other. In one embodiment, each of the select transistors SST and DST, and the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0057] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0058] In one embodiment, the source select transistors of cell strings arranged in the same row are connected to source select lines extending along the row direction, and the source select transistors of cell strings arranged in different rows are connected to different source select lines. Figure 4In the first row, the source selection transistors of cell strings CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors of cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0059] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0060] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0061] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in opposite directions in the +Z direction and connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected through the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0062] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0063] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged along the row direction are connected to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0064] The cell strings arranged in the column direction are connected to bit lines extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 in the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0065] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, in cell strings CS11 to CS1m on the first row, memory cells connected to the first word line WL1 constitute one page. In cell strings CS21 to CS2m on the second row, memory cells connected to the first word line WL1 constitute another page. When either drain selection line DSL1 or DSL2 is selected, a cell string arranged in one row direction can be selected. When any of the word lines WL1 to WLn is selected, a page can be selected from the selected cell string.

[0066] Figure 5 It's a diagram. Figure 1 A diagram of another embodiment 110_3 of the memory cell array 110 shown.

[0067] refer to Figure 5 The memory cell array 110_3 includes multiple memory blocks BLK1' to BLKz'. Figure 4 For ease of description, the internal configuration of the first memory block BLK1' is illustrated, while the internal configurations of the other memory blocks BLK2' to BLKz' are omitted. It should be understood that the second to z-th memory blocks BLK2' to BLKz' are configured similarly to the first memory block BLK1'.

[0068] The first memory block BLK1' may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends in the +Z direction. In the first memory block BLK1', m cell strings are arranged along the +X direction. Although in Figure 5 The diagram illustrates two unit strings arranged along the +Y direction, but this is for ease of description, and it should be understood that three unit strings can be arranged along the column direction.

[0069] Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST.

[0070] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be commonly connected to a single source select line.

[0071] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are respectively connected to the first to nth word lines WL1 to WLn.

[0072] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction are connected to drain select lines extending along the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0073] therefore, Figure 5 The circuitry of the memory block BLK1' shown is similar to Figure 4 The circuitry shown for memory block BLK1 differs in that it originates from... Figure 5 The pipe transistor PT has been removed from each of the unit strings shown.

[0074] Figure 6 The graph illustrates the distribution of threshold voltages in memory cells when the threshold voltage window is widened, for example, to improve read margin.

[0075] refer to Figure 6 The illustration shows the first window V W1 The threshold voltage distribution of the memory cells included and in the second window V W2 The threshold voltage distribution of the memory cells included. More specifically, Figure 6 The diagram above illustrates the first window V W1 The threshold voltage distribution of the memory cells included. (Reference) Figure 6 As shown in the above diagram, the first window V W1 Having a first lower limit voltage V LL1 and the first upper limit voltage VUL1 The range between [variable values]. The threshold voltage of the memory cell is distributed within the first window V. W1 Within the voltage range. Figure 6 In this context, the threshold voltages of the three-level cells (TCLs) corresponding to the erase state E and the first to seventh programming states PV1 to PV7 are distributed in the first window V. W1 However, this is only illustrative, and the threshold voltage distribution corresponding to single-level cell (SLC), multi-level cell (MLC), quadruple-level cell (QLC), etc., can also be considered for the first window.

[0076] As the manufacturing process of memory cells improves and the number of bits stored in each memory cell increases, in one embodiment, ensuring read margin is important to improve the reliability of the semiconductor memory device 100. Read margin can represent the interval between erase state E and the first to seventh programming states PV1 to PV7. To ensure read margin, a window corresponding to the range of threshold voltage distribution for the memory cell can be extended.

[0077] Figure 6 The following diagram illustrates the second window V W2 The threshold voltage distribution of the memory cells included. (Reference) Figure 6 The figure below illustrates a window with a size greater than the first window V. W1 The second window of the wide range V W2 Second window V W2 Having a second lower limit voltage V LL2 Second upper limit voltage V UL2 The range between [a certain value]. In one embodiment, the second lower limit voltage V [is defined as follows]. LL2 It can be lower than the first lower limit voltage V LL1 Furthermore, in one embodiment, the second upper limit voltage V UL2 It can be higher than the first upper limit voltage V UL1 . refer to Figure 6 As shown in the figure below, the threshold voltage of the memory cell is distributed in the second window V. W2 Within the voltage range. That is, the threshold voltage of the three-level cell (TLC) corresponding to the erase state E' and the first to seventh programming states PV1' to PV7' is distributed in the second window V. W2 middle.

[0078] like Figure 6 As shown, when the threshold voltage distribution range of the memory cell is from the first window V W1 Expand to the second window V W2At this time, the interval between the erase state E' and the first to seventh programming states PV1' to PV7' is increased. Therefore, in one embodiment, the read margin is increased, and the reliability of the semiconductor memory device is improved.

[0079] Figure 7 The diagram is as shown in the reference. Figure 6 The graph shows the programming voltage change for each programming cycle in incremental step pulse programming when the threshold voltage window is widened.

[0080] refer to Figure 7 The above figure illustrates the interaction with the first window V. W1 The corresponding incremental step pulse programming (ISPP) involves programming and verification voltages applied to the selected memory cells. The programming operation using ISPP comprises multiple programming cycles, each including a programming phase and a verification phase. The programming phase is where a programming voltage is applied to the word line connected to the selected memory cell. A programming voltage is applied to the unselected word line. Through the programming phase, the threshold voltage of at least some memory cells can be increased. The verification phase is where a verification voltage is applied to the word line connected to the selected memory cell. A verification voltage is applied to the unselected word line. Through the verification phase, it is determined whether the threshold voltage of at least some selected memory cells is higher than the verification voltage.

[0081] refer to Figure 7 In the diagram above, a first programming voltage Vp1 is applied to the word line connected to the selected memory cell, i.e., the selected word line in the programming phase of the first programming cycle. The magnitude of the first programming voltage Vp1 corresponds to the programming start voltage V. S1 After the first programming voltage Vp1 is applied to the selected word line, the verification voltage Vr is applied to the selected memory cell during the verification phase of the first programming cycle.

[0082] Subsequently, during the programming phase of the second programming cycle, a second programming voltage Vp2 is applied to the selected word line. The amplitude of the second programming voltage Vp2 becomes a higher step voltage ΔV value than the first programming voltage Vp1. After the second programming voltage Vp2 is applied to the selected word line, a verification voltage Vr is applied to the selected memory cell during the verification phase of the second programming cycle.

[0083] Subsequently, during the programming phase of the third programming cycle, a third programming voltage Vp3 is applied to the selected word line. The amplitude of the third programming voltage Vp3 becomes a higher step voltage ΔV value than the second programming voltage Vp2. After the third programming voltage Vp3 is applied to the selected word line, a verification voltage Vr is applied to the selected memory cell during the verification phase of the third programming cycle.

[0084] In this way, the programming loop can be repeated until the selected memory cell is fully programmed. Figure 7 In this example, only 10 programming loops are illustrated. Meanwhile, although in Figure 7 The diagram illustrates a case where the verification voltage Vr applied to the selected word line during the verification phase has the same amplitude, but this is only illustrative. Verification voltages with different amplitudes and different numbers can be applied to the selected word line according to the programming cycle.

[0085] Now, for reference Figure 7 The following diagram illustrates the interaction with the second window V. W2 The corresponding programming and verification voltages applied to the selected memory cell in incremental step pulse programming (ISPP). (Reference) Figure 7 As shown in the diagram below, a first programming voltage Vp1' is applied to the word line connected to the selected memory cell, i.e., the selected word line in the programming phase of the first programming cycle. The amplitude of the first programming voltage Vp1' corresponds to the programming start voltage V. S2 After the first programming voltage Vp1' is applied to the selected word line, the verification voltage Vr is applied to the selected memory cell during the verification phase of the first programming cycle.

[0086] Subsequently, during the programming phase of the second programming cycle, a second programming voltage Vp2' is applied to the selected word line. The amplitude of the second programming voltage Vp2' becomes a higher step voltage ΔV value than the first programming voltage Vp1'. After the second programming voltage Vp2' is applied to the selected word line, a verification voltage Vr is applied to the selected memory cell during the verification phase of the second programming cycle.

[0087] Subsequently, during the programming phase of the third programming cycle, a third programming voltage Vp3' is applied to the selected word line. The amplitude of the third programming voltage Vp3' becomes a higher step voltage ΔV value than the second programming voltage Vp2'. After the third programming voltage Vp3' is applied to the selected word line, a verification voltage Vr is applied to the selected memory cell during the verification phase of the third programming cycle.

[0088] refer to Figure 6 Due to the second window V W2 The corresponding second lower limit voltage V LL2 Lower than the first window V W1 The corresponding first lower limit voltage V LL1 Therefore, with the second window V W2 Corresponding programming starting voltage V S2 It can also be lower than the first window V W1 Corresponding programming starting voltage V S1Therefore, in relation to the second window V W2 In the corresponding ISPP, the amplitude of some programming voltages (e.g., Vp1' to Vp7') in the initial stage may be lower than that of the first window V. W1 The corresponding ISPP programming start voltage V S1 In other words, in one embodiment, when the threshold voltage distribution window is widened to improve read margin, the initial programming voltage of the ISPP falls within a relatively low range as the programming start voltage decreases. Programming voltages within this relatively low range cause a relatively low increase in the threshold voltage of the memory cell. As a result, in one embodiment, the number of programming loops executed to complete programming increases, leading to an overall decrease in programming speed. In the following, reference will be made to... Figure 8 Let me describe it in detail.

[0089] Figure 8 The diagram is as shown in the reference. Figure 7 The graph depicts the phenomenon that programming speed decreases as the initial programming voltage (i.e., the programming start voltage) decreases.

[0090] Figure 8 The horizontal axis of the graph shown represents the magnitude of the programming voltage (i.e., the programming bias) applied in each programming cycle, and Figure 8 The vertical axis of the graph shown represents the threshold voltage Vth of the memory cell according to the applied programming voltage. Figure 8 In the middle, in relation to the first window V W1 In the corresponding ISSP method, the change in the threshold voltage of the memory cell relative to the programming voltage is indicated by a circle, and is related to the second window V. W2 In the corresponding ISSP method, the change in the threshold voltage of the memory cell relative to the programming voltage is represented by a triangle.

[0091] For reference Figure 7 As mentioned above, in relation to the first window V W1 In the corresponding ISSP method, the first programming voltage Vp1 has the same characteristics as the programming start voltage V. S1 The corresponding voltage values. The second programming voltage Vp2 has a higher step voltage ΔV than the first programming voltage Vp1. The third programming voltage Vp3 also has a higher step voltage ΔV than the second programming voltage Vp2. To clarify this, Figure 8 The scale intervals indicated on the horizontal axis shown correspond to the voltage values ​​of the step voltage ΔV.

[0092] For reference only Figure 8 The circular symbol shown illustrates the relationship between the first window V and the surrounding area. W1The corresponding ISSP method describes the change in the threshold voltage of the memory cell during the first to eighth programming cycles. The threshold voltage of the memory cell in the initial stage has a first lower limit voltage V. LL1 The value is near the threshold voltage. As the first programming voltage Vp1 is applied to the memory cell, the threshold voltage of the memory cell will increase to slightly above the first lower limit voltage V. LL1 The value of .

[0093] like Figure 8 As shown, due to the relationship with the first window V W1 In the corresponding ISSP method, the first programming voltage Vp1 corresponds to a relatively high programming start voltage V. S1 Therefore, when the programming voltage increases by a step voltage ΔV, the threshold voltage shift of the memory cell is relatively wide. In other words, because the threshold voltage of the memory cell increases relatively for each programming cycle, the threshold voltage of the memory cell can reach the target voltage V with only a relatively small number of programming cycles. TRG .exist Figure 8 The diagram illustrates the relationship between the first window V and the second window V. W1 In the corresponding ISSP method, the threshold voltage of the memory cell reaches the target voltage V through 8 programming loops. TRG .

[0094] At the same time, for reference only Figure 8 The triangle symbol shown illustrates the relationship between the second window V and the triangle symbol. W2 The corresponding ISSP method describes the change in the threshold voltage of the memory cell during the first to fifteenth programming cycles. The threshold voltage of the memory cell in the initial stage has a second lower limit voltage V. LL2 The value is near the threshold voltage. As the first programming voltage Vp1' is applied to the memory cell, the threshold voltage of the memory cell will increase to slightly above the second lower limit voltage V. LL2 The value of .

[0095] like Figure 8 As shown, due to the second window V W2 In the corresponding ISSP method, the first programming voltage Vp1' corresponds to a relatively low programming start voltage V. S2 Therefore, the programming voltage applied in some initial programming loops may be lower than that applied in the first window V. W1 Corresponding programming starting voltage V S1 .exist Figure 8 The diagram shows the relationship between the second window V and the second window. W2 The corresponding first to seventh programming voltages VP1' to Vp7' are less than the first window V W1 Corresponding programming starting voltage V S1 .

[0096] When compared with the programming start voltage V S2 To V S1 When the programming voltage corresponding to the voltage interval is applied to the memory cell, the threshold voltage shift of the memory cell is relatively narrow. That is, in relation to the second window V... W2 In the corresponding ISSP method, the programming voltage applied in some initial programming loops (e.g., Vp1' to Vp7') is less than that applied in the first window V. W1 Corresponding programming starting voltage V S1 During the application of the programming voltage, the threshold voltage shift of the memory cell is relatively narrow. However, the programming pulse applied after the eighth programming cycle is higher than that applied during the first window V. W1 Corresponding programming starting voltage V S1 Therefore, the threshold voltage shift of the memory cell can be relatively wide.

[0097] Therefore, since the threshold voltage increment of the memory cell is very small during the initial programming loop, the threshold voltage of the memory cell can reach the target voltage V after a relatively large number of programming loops are executed. TRG .exist Figure 8 The diagram shows the interaction with the second window V. W2 In the corresponding ISSP method, the threshold voltage of the memory cell reaches the target voltage V through 15 programming cycles. TRG This instruction is in conjunction with the first window V. W1 The corresponding ISSP method's programming loop number ratio is in relation to the second window V. W2 The corresponding ISSP method uses a maximum of 7 loops. Therefore, when compared with the first window V... W1 The corresponding ISSP method is applied as is to the first window V. W1 A wider range of second windows V W2 At this time, programming speed may be significantly reduced.

[0098] The semiconductor memory device and its operation method according to embodiments of the present disclosure, in conjunction with a second window V including a relatively wide voltage range. W2 In the corresponding ISSP method, a relatively high step voltage is applied in the initial programming loop, and a relatively low step voltage is applied in subsequent programming loops. Therefore, in one embodiment, even with a second window V including a relatively wide voltage range... W2 In the corresponding ISSP method, the read margin of memory cells can also be improved without significantly reducing programming speed.

[0099] Figure 9 This is a graph illustrating an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0100] refer to Figure 9 The above figure illustrates the interaction with the first window V. W1 The corresponding incremental step pulse programming (ISPP) applies programming and verification voltages to the selected memory cell. Figure 9 The above diagram shown is similar to Figure 7 The above diagrams are essentially the same. Therefore, repeated descriptions will be omitted.

[0101] refer to Figure 9 The figure below illustrates an embodiment, in which the second window V... W2 The corresponding ISSP is executed through the operating method of the semiconductor memory device according to this disclosure. (See reference...) Figure 9 As shown in the diagram below, a first programming voltage Vp1' is applied to the word line connected to the selected memory cell, i.e., the selected word line in the programming phase of the first programming cycle. The amplitude of the first programming voltage Vp1' corresponds to the programming start voltage V. S2 After the first programming voltage Vp1' is applied to the selected word line, the verification voltage Vr is applied to the selected memory cell during the verification phase of the first programming cycle. This is consistent with... Figure 7 The description shown is the same.

[0102] Subsequently, during the programming phase of the second programming cycle, a second programming voltage Vp2' is applied to the selected word line. The amplitude of the second programming voltage Vp2' becomes higher than the first programming voltage Vp1' by the value of a first step voltage ΔV1. The first step voltage ΔV1 is a value higher than the aforementioned step voltage ΔV. Therefore, Figure 9 The second programming voltage Vp2' shown can be changed to be greater than Figure 7 The value of the second programming voltage Vp2' shown.

[0103] Similarly, in the third programming cycle, the third programming voltage Vp3' becomes a value that is a first step voltage ΔV1 higher than the second programming voltage Vp2'. After the third programming voltage Vp3' is applied to the selected word line, the verification voltage Vr is applied to the selected memory cell during the verification phase of the third programming cycle. This process is repeated until the fifth programming cycle.

[0104] During the programming phase of the sixth programming cycle, the sixth programming voltage Vp6' is applied to the selected word line. The amplitude of the sixth programming voltage Vp6' becomes higher than the fifth programming voltage Vp5' by a second step voltage ΔV2. The second step voltage ΔV2 is lower than the first step voltage ΔV1.

[0105] In subsequent programming loops, the programming voltage is calculated using the second step voltage ΔV2, and the programming operation is performed based on the programming voltage.

[0106] In other words, according to embodiments of this disclosure, in conjunction with the second window V W2 In the corresponding ISSP, the programming voltage is determined in some initial programming cycles (e.g., the first to fifth programming cycles) by using a relatively high first step voltage ΔV1, and the programming voltage is determined in subsequent programming cycles (e.g., the sixth programming cycle and thereafter) by using a lower second step voltage ΔV2.

[0107] Therefore, according to embodiments of this disclosure, the threshold voltage distribution of memory cells is narrowly formed by increasing the programming voltage relatively quickly in the initial programming cycle and relatively slowly in subsequent programming cycles. As a result, the threshold voltage distribution of memory cells can be narrowly formed while using a relatively wide programming window without significantly reducing programming speed.

[0108] Figure 10 This is for one embodiment, illustrated as referenced. Figure 9 The graph depicts the increase in programming speed when a step voltage is added at the initial stage of programming.

[0109] Similar to Figure 8 , Figure 10 The horizontal axis of the graph shown represents the magnitude of the programming voltage (i.e., the programming bias) applied in each programming cycle, and Figure 10 The vertical axis of the graph shown represents the threshold voltage Vth of the memory cell according to the applied programming voltage. Figure 10 In the middle, in relation to the first window V W1 In the corresponding ISSP method, the change in the threshold voltage of the memory cell relative to the programming voltage is represented by a circle, and in the second window V W2 In the corresponding ISSP method, the change in the threshold voltage of the memory cell relative to the programming voltage is represented by a triangle.

[0110] For reference only Figure 10 The circular symbol shown illustrates the relationship between the first window V and the surrounding area. W1 The corresponding ISSP method shows the change in the threshold voltage of the memory cell during the first to eighth programming cycles. Figure 10 The position of the circular symbol shown is... Figure 8 The circular symbols are in the same position, and therefore duplicate descriptions will be omitted.

[0111] At the same time, for reference only Figure 8 The triangle symbol shown illustrates the relationship between the second window V and the triangle symbol. W2The corresponding ISSP method describes the change in the threshold voltage of the memory cell during the first to eleventh programming cycles. The threshold voltage of the memory cell in the initial stage has a second lower limit voltage V. LL2 The value is near the threshold voltage. As the first programming voltage Vp1' is applied to the memory cell, the threshold voltage of the memory cell will increase to slightly above the second lower limit voltage V. LL2 The value of .

[0112] like Figure 10 As shown, in relation to the second window V W2 In the corresponding ISSP method, the first programming voltage Vp1' corresponds to a relatively low programming start voltage V. S2 Furthermore, some initial programming cycles (i.e., the programming voltages Vp1' to Vp5' applied to the selected memory cells in the first to fifth programming cycles) are determined based on a relatively high first step voltage ΔV1. Meanwhile, subsequent programming cycles (i.e., the programming voltages Vp6' to Vp11' applied to the selected memory cells in the sixth to eleventh programming cycles) are determined based on a relatively low second step voltage ΔV2.

[0113] Therefore, the threshold voltage of the mobile memory cell has a relatively low efficiency for programming the starting voltage V. S2 To V S1 In the voltage interval, the programming voltage Vp1' to Vp5' is significantly increased by using a relatively high first step voltage ΔV1, and in the subsequent voltage interval, the programming voltage Vp6' to Vp11' can be finely adjusted by using a relatively low second step voltage ΔV2.

[0114] Therefore, it is possible to prevent or mitigate the execution of a relatively large number of programming loops in the initial programming loop. Figure 10 The diagram shows the interaction with the second window V. W2 In the corresponding ISPP, the threshold voltage of the memory cell reaches the target voltage V through 11 programming cycles. TRG . Figure 10 The number of programming loops shown Figure 8 The number of programming loops shown (i.e., 15) is significantly reduced compared to the previous version. In other words, in one embodiment, even when using a relatively wide programming window, a significant decrease in programming speed can be prevented or mitigated.

[0115] Figure 11 This is a flowchart illustrating one aspect of an operation method of a semiconductor memory device according to an embodiment of the present disclosure.

[0116] refer to Figure 11An operation method of a semiconductor memory device according to an embodiment of the present disclosure includes: step S110 of performing a programming operation using a programming voltage determined based on a first step voltage ΔV1 during a first programming period, and step S130 of performing a programming operation using a programming voltage determined based on a second step voltage ΔV2 during a second programming period.

[0117] In step S110, the first programming session may, for example, include the first to fifth programming loops. (See reference...) Figure 9 As described, the programming voltage applied to the selected word line in the first to fifth programming cycles is determined based on the first step voltage ΔV1.

[0118] In step S130, the second programming period may, for example, include a sixth programming loop and subsequent programming loops. (See reference...) Figure 9 As described, the programming voltage applied to the selected word line in the sixth programming cycle and subsequent programming cycles can be determined based on the second step voltage ΔV2.

[0119] In one embodiment, the second step voltage ΔV2 may be a voltage lower than the first step voltage ΔV1. However, the invention is not limited thereto, and the second step voltage ΔV2 may be a voltage higher than the first step voltage ΔV1, as needed.

[0120] exist Figure 9 and Figure 10 The diagram illustrates the first programming period, which includes the first through fifth programming cycles. However, this is merely illustrative, and the number of programming cycles included in the first programming period can be determined differently in the design if desired. That is, the number of programming cycles can be determined based on the programming start voltage V. S2 The threshold voltage ΔV1 is determined by the magnitude of the first step voltage ΔV1 and the length of the period during which increasing the threshold voltage is less efficient. Additionally, the first step voltage ΔV1 can be determined differently in the design if necessary.

[0121] Figure 12 This is a flowchart illustrating another aspect of the operation method of a semiconductor memory device according to an embodiment of the present disclosure. Figure 11 The flowchart shown illustrates that step S110 includes at least one programming loop, and step S130 also includes at least one programming loop. On the other hand, Figure 12 The steps included in the flowchart shown represent a programming loop.

[0122] refer to Figure 12 The operation method of the semiconductor memory device according to embodiments of the present disclosure includes: based on the programming loop number N PLThe steps are: S210, determining a step voltage and determining a programming voltage based on the step voltage; S230, applying the programming voltage to the selected memory cell; S250, performing a verification operation on the selected memory cell; and S270, determining whether the selected memory cell has been fully programmed.

[0123] In step S210, the step voltage is based on the programming cycle number N of the currently executing programming cycle. PL To determine. For example, when the currently executing programming loop is the first programming loop, the programming loop number N is... PL It becomes 1. Additionally, when the currently executing programming loop is the second programming loop, the programming loop number N... PL It becomes 2. In step S210, the step voltage is first based on the current programming cycle number N. PL The programming voltage is determined based on the step voltage. The programming voltage in the current programming cycle can be determined as a value obtained by adding the step voltage to the programming voltage used in previous programming cycles. See later... Figure 13 Here are examples of embodiments for describing step S210.

[0124] In step S230, a programming voltage is applied to the selected memory cell. Specifically, in step S230, a programming enable voltage can be applied to the bit line connected to the programming enable cell within the selected memory cell, and a programming disable voltage can be applied to the bit line connected to the programming disable cell. Furthermore, in step S230, a programming voltage can be applied to the selected word line connected to the selected memory cell, and a programming pass voltage can be applied to other unselected word lines. As step S230 is executed, the threshold voltage of the programming enable cell increases.

[0125] In step S250, a verification operation is performed on the selected memory cells. Specifically, in step S250, a verification voltage can be applied to the selected word line, and a verification pass voltage can be applied to the unselected word line. Through step S250, it can be determined whether the threshold voltage of at least some of the selected memory cells is higher than the verification voltage. In step S250, the verification operation can be performed using only one verification voltage, or it can be performed using two or more verification voltages. Additionally, the verification voltage used in step S250 can be changed when the programming loop is repeatedly executed.

[0126] In step S270, it is determined whether the selected memory cell has been fully programmed. More specifically, in step S270, it can be determined whether the threshold voltage of each of the selected memory cells has been sufficiently increased to be included in the target programming state. When the threshold voltage of each of the selected memory cells has been sufficiently increased to be included in the target programming state (S270: Yes), the programming operation ends. When the threshold voltage of each of the selected memory cells has not been sufficiently increased to be included in the target programming state (S270: No), the semiconductor memory device returns to step S210 to perform a subsequent programming cycle.

[0127] In other words, Figure 12 Steps S210, S230, and S250 shown can constitute a programming loop. After a programming loop is executed, it is determined whether the selected memory cell has been fully programmed (S270). If the selected memory cell has not been fully programmed (S270: No), a subsequent programming loop is executed. When the selected memory cell has been fully programmed (S270: Yes), the programming operation ends.

[0128] Figure 13 It's a diagram. Figure 12 The flowchart shows an example of an embodiment of step S210.

[0129] refer to Figure 13 Based on the number of programming loops N PL Step S210, which involves determining the step voltage and, based on the step voltage, determining the programming voltage, includes: determining the programming cycle number N. PL Is it less than the threshold loop number N? TH Step S211; When the programming loop number N PL The number of cycles N is less than the threshold. TH The steps are: S213, which determines the first voltage as the step voltage; and S217, which determines the value obtained by adding the determined step voltage to the programming voltage of the previous programming cycle as the programming voltage of the current programming cycle.

[0130] In step S211, the programming loop number N corresponding to the current programming loop is determined. PL Is the number of loops less than the predetermined threshold N? TH .exist Figure 9 and Figure 10 In the example shown, the threshold cycle number N TH It is 6. However, this disclosure is not limited to this, and the threshold cycle number N THThe value of a parameter can be determined in various ways as needed. As used herein, the term "predetermined" for parameters such as a predetermined threshold number of loops or a predetermined value means that the value of the parameter is determined before the parameter is used in the process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0131] When the programming loop number N corresponding to the current programming loop PL The number of cycles N is less than the predetermined threshold. TH When (S211: Yes), the first voltage is determined to be a step voltage. The first voltage can be... Figure 9 and Figure 10 The voltage value of the first step voltage ΔV1 shown. Figure 9 and Figure 10 The illustrated embodiment, due to the threshold cycle number N TH The value is 6, so the first voltage can be determined as the step voltage during the first to fifth programming cycles.

[0132] Meanwhile, according to one embodiment of this disclosure, Figure 12 Step S210 shown may include: when the programming loop number N PL Not less than the threshold number of cycles N TH (S211: No) Step S215 determines the second voltage as a step voltage. According to Figure 9 and Figure 10 The embodiment shown has a threshold cycle number N. TH Given a value of 6, the second voltage can be determined as the step voltage in the sixth programming cycle and subsequent programming cycles. The second voltage can be... Figure 9 and Figure 10 The voltage value of the second step voltage ΔV2 is shown.

[0133] In one embodiment, the second voltage may be a value lower than the first voltage. However, this disclosure is not limited thereto, and the second voltage may be a value higher than the first voltage.

[0134] In step S217, the programming voltage to be used in the current programming cycle is determined. Specifically, the value obtained by adding the step voltage determined in step S213 to the programming voltage used in the previous programming cycle can be determined as the programming voltage for the current programming cycle. Figure 9 and Figure 10 The illustrated embodiment, due to the threshold cycle number N THThe programming voltage of the current programming cycle is 6. It can be determined by adding a first voltage to the programming voltage of the previous programming cycle during the first to fifth programming cycles. Additionally, the programming voltage of the current programming cycle can be determined by adding a second voltage to the programming voltage of the previous programming cycle in the sixth programming cycle and subsequent programming cycles.

[0135] For reference Figure 9 and Figure 13 As described, the first step voltage ΔV1 used in the first programming period (i.e., the initial programming cycle of the programming operation) is determined to a predetermined value if necessary. However, when using the semiconductor memory device 100, it is necessary to change the first step voltage ΔV1. The first step voltage ΔV1 is adaptively determined according to the programming speed of the memory cell in the actual initial programming cycle, thereby optimizing the programming operation of the semiconductor memory device. In the following text, this will refer to... Figures 14 to 17 Describe it.

[0136] Figure 14 The illustration shows the determination of one embodiment of the present disclosure. Figure 13 A diagram illustrating the method for specifying the first voltage in step S213.

[0137] According to one embodiment of this disclosure, in order to determine the first voltage, the programming speed of the memory cell can be checked in the first programming cycle of the programming operation. For this purpose, a reference voltage Vx can be used. Figure 14 The diagram above illustrates the initial threshold voltage distribution S0 of the selected memory cell before the programming operation is performed. The initial threshold voltage distribution S0 corresponds to the erase state.

[0138] In the first programming cycle, the programming start voltage V S2 The first programming voltage Vp1' can be applied to the selected word line. Therefore, programming within the selected memory cell allows the threshold voltage of the memory cell to increase. Thus, the initial threshold voltage distribution S0 can be changed to the first distribution S1.

[0139] refer to Figure 14 As shown in the lower figure, as the threshold voltage distribution of the memory cells changes to the first distribution S1, memory cells with threshold voltages higher than the reference voltage Vx appear. Specifically, in Figure 14 In the diagram below, the memory cells with a threshold voltage higher than the reference voltage Vx are the memory cells corresponding to the shaded areas in the first distribution S1. The programming speed of a memory cell can be determined based on the number N1 of memory cells belonging to the first distribution S1 with a threshold voltage higher than the reference voltage Vx.

[0140] For example, when the number N1 of memory cells with a threshold voltage greater than the reference voltage Vx is a relatively small value, it can be determined that the programming speed of the memory cells is slow. The first step voltage ΔV1 used in the first programming period (i.e., the initial programming cycle of the programming operation) can be determined to be a relatively high value.

[0141] Conversely, when the number N1 of memory cells with a threshold voltage greater than the reference voltage Vx is a relatively high value, it can be determined that the memory cell programming speed is fast. The first step voltage ΔV1 used in the first programming period (i.e., the initial programming cycle of the programming operation) can be determined to be a relatively low value.

[0142] The process of calculating the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx can be performed in a manner similar to a verification operation. That is, the reference voltage Vx is applied to the selected word line, and a verification pass voltage is applied to the unselected word line. Bit data indicating whether the threshold voltage of a memory cell is higher than the reference voltage Vx can be stored in latches of page buffers PB1 to PBn corresponding to the respective memory cell. Simultaneously, a current sensing circuit (CSC), widely used in verification operations, can generate a current corresponding to the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx based on the bit data in the latches. The configuration and operation method of the current sensing circuit are well known in the art to which this disclosure pertains, and therefore a detailed description thereof will be omitted. Additionally, the generated current is converted into a digital value by an analog-to-digital converter, making it possible to calculate the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx.

[0143] The semiconductor memory device 100 can store a lookup table for determining the corresponding first step voltage ΔV1 based on the range of the number N1 of memory cells whose threshold voltage is higher than the reference voltage Vx. For example, the lookup table can be configured as shown in Table 1 below.

[0144] Table 1

[0145]

[0146] As shown in Table 1 above, the first step voltage ΔV1 can be determined by a lookup table, which represents voltage values ​​Vx1 to Vxn corresponding to multiple ranges of the number N1 of memory cells with threshold voltages higher than the reference voltage Vx. In one embodiment, the process of determining the first step voltage ΔV1 can be performed in the initial first programming loop, and the programming voltage can be determined in subsequent programming loops using the determined first step voltage ΔV1.

[0147] exist Figure 14The diagram illustrates a reference voltage Vx that is higher than a threshold voltage that is higher than the threshold voltage of all memory cells belonging to the initial threshold voltage distribution S0. However, this is merely illustrative, and the present disclosure is not limited thereto. For example, the reference voltage Vx may be a value that is higher than the threshold voltage of some memory cells belonging to the initial threshold voltage distribution S0 and lower than the threshold voltage of other memory cells.

[0148] Figure 15 The illustration shows the determination of one embodiment of the present disclosure. Figure 13 The flowchart illustrates an embodiment of the first voltage specified in step S213. Specifically, Figure 15 Detailed illustrations are provided for reference. Figure 14 The flowchart describes the method and illustrates the stages included in the first programming loop.

[0149] refer to Figure 15 The method for determining the first voltage in the first programming cycle includes: step S310 of applying a programming voltage to a selected memory cell; step S330 of counting the number N1 of memory cells with a threshold voltage higher than a reference voltage Vx; and step S350 of determining the first voltage based on the counted number N1 of memory cells.

[0150] In step S310, the programming voltage Vp1' is applied to the word line connected to the selected memory cell corresponding to the initial threshold voltage distribution S0. Therefore, the threshold voltage distribution of the selected memory cell changes from the initial threshold voltage distribution S0 to the first distribution S1.

[0151] In step S330, the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx is counted. As described above, the process of counting the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx in step S330 can be performed in a manner similar to a verification operation. That is, the reference voltage Vx is applied to the selected word line, and a verification pass voltage is applied to the unselected word line. Bit data indicating whether the threshold voltage of a memory cell is higher than the reference voltage Vx can be stored in latches of page buffers PB1 to PBn corresponding to the respective memory cell. Simultaneously, the current sensing circuit (CSC) used in the verification operation can generate a current corresponding to the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx based on the bit data in the latches. Additionally, the generated current is converted into a digital value by an analog-to-digital converter, so that the number N1 of memory cells with a threshold voltage higher than the reference voltage Vx can be calculated.

[0152] In step S350, the first voltage can be determined based on the number N1 of memory cells whose threshold voltage is higher than the reference voltage Vx. The first voltage can be determined by referring to a lookup table such as Table 1 above.

[0153] refer to Figure 14 and Figure 15 The first voltage can be determined in the initial first programming cycle and used as a fixed value in subsequent first programming periods (e.g., second to fifth programming cycles). However, this disclosure is not limited thereto, and the first voltage can be determined for each of the plurality of programming cycles belonging to the first programming period. In the following, reference will be made to... Figure 16 and Figure 17 Describe it.

[0154] Figure 16 It is illustrated in Figure 13 A diagram illustrating the method for determining the step voltage in step S213.

[0155] According to one embodiment of this disclosure, in order to determine the first voltage, the programming speed of the memory cell can be checked in each programming cycle within the first programming cycle (e.g., the first to fifth programming cycles). For this purpose, a reference voltage Vx can be used. Figure 16 The first graph shown illustrates the initial threshold voltage distribution S0 of the selected memory cell before the programming operation is performed. The initial threshold voltage distribution S0 corresponds to the erase state.

[0156] In the first programming cycle, the programming start voltage V S2 The first programming voltage Vp1' can be applied to the selected word line. Therefore, programming within the selected memory cell allows the threshold voltage of the memory cell to increase. Thus, the initial threshold voltage distribution S0 can be changed to the first distribution S1.

[0157] refer to Figure 16 The second curve shown illustrates that as the threshold voltage distribution of the memory cells changes to the first distribution S1, memory cells with threshold voltages higher than the reference voltage Vx appear. Specifically, in Figure 16 In the second graph shown, the first voltage to be used in the second programming cycle can be determined based on the number N1 of memory cells whose threshold voltage is higher than the reference voltage Vx. The second programming voltage Vp2' to be used in the second programming cycle is determined based on the determined first voltage. In the second programming cycle, the determined second programming voltage Vp2' can be applied to the selected word line. Therefore, programming in the selected memory cells allows the threshold voltage of the memory cells to increase. Therefore, the first distribution S1 can be changed to the second distribution S2.

[0158] refer to Figure 16The third curve shown illustrates that as the threshold voltage distribution of memory cells changes to the second distribution S2, the number of memory cells with threshold voltages higher than the reference voltage Vx increases. Specifically, in Figure 16 In the third curve shown, the first voltage to be used in the third programming cycle can be determined based on the number N2 of memory cells whose threshold voltage is higher than the reference voltage Vx. The third programming voltage Vp3' to be used in the third programming cycle is determined based on the determined first voltage. In the third programming cycle, the determined third programming voltage Vp3' can be applied to the selected word line. Therefore, programming in the selected memory cells allows the threshold voltage of the memory cells to increase. Therefore, the second distribution S2 can be changed to the third distribution S3.

[0159] refer to Figure 16 The fourth curve shown illustrates that as the threshold voltage distribution of memory cells changes to the third distribution S3, the number of memory cells with threshold voltages higher than the reference voltage Vx increases again. Specifically, in Figure 16 In the fourth graph shown, the first voltage to be used in the fourth programming cycle can be determined based on the number N3 of memory cells whose threshold voltage is higher than the reference voltage Vx. The fourth programming voltage Vp4' to be used in the fourth programming cycle is determined based on the determined first voltage.

[0160] In this way, the first voltage used to determine the programming voltage in each programming cycle can be determined based on the number of memory cells Nx obtained by counting the number of memory cells whose threshold voltage is higher than the reference voltage Vx for each programming cycle.

[0161] Figure 17 It is illustrated in Figure 13 A flowchart illustrating an example of an embodiment of determining the step voltage in step S213 is shown.

[0162] refer to Figure 17 , Figure 13 The step S213 shown includes: a step S410 of counting the number Nx of memory cells with a threshold voltage higher than the reference voltage Vx, and a step S430 of determining the step voltage based on the number Nx of the counted memory cells. Figure 17 Steps S410 and S430 shown can be included Figure 13 In step S213 shown. That is to say, Figure 17 Steps S410 and S430 shown can be repeated for each programming cycle. Therefore, for each programming cycle of the first programming period, the step voltage can be determined by counting the number Nx of memory cells whose threshold voltage is higher than the reference voltage Vx.

[0163] refer to Figure 16 The diagram illustrates that the reference voltage Vx is a fixed value even when the programming cycle is repeated. However, this disclosure is not limited to this, and a different reference voltage Vx can be used each time the programming cycle is repeated.

[0164] Figure 18 The diagram includes Figure 1 The diagram shows a block diagram of a semiconductor memory device's memory system.

[0165] refer to Figure 18 The memory system 1000 includes a semiconductor memory device 100 and a controller 1100. The semiconductor memory device 100 may be a reference. Figure 1 The semiconductor memory device described. Repeated descriptions will be omitted in the following text.

[0166] Controller 1100 is coupled to a host computer and semiconductor memory device 100. Controller 1100 accesses semiconductor memory device 100 in response to requests from the host computer. For example, controller 1100 controls read, write, erase, and background operations of semiconductor memory device 100. Controller 1100 provides an interface between semiconductor memory device 100 and the host computer. Controller 1100 drives firmware for controlling semiconductor memory device 100.

[0167] The controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 is used as at least one of the working memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a cache memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the controller 1100. Additionally, the controller 1100 can temporarily store programming data provided from the host during write operations.

[0168] The host interface 1130 includes protocols for exchanging data between the host and the controller 1100. In one example of an embodiment, the controller 1100 communicates with the host via at least one of a variety of interface protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0169] The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface 1140 may include a NAND interface or a NOR interface.

[0170] Error correction block 1150 detects and corrects errors in data received from semiconductor memory device 100 using error correction codes (ECC). Processing unit 1120 can adjust the read voltage based on the error detection results of error correction block 1150 and control memory device 100 to perform a reread. In one example of an embodiment, error correction block 1150 may be provided as a component of controller 1100.

[0171] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one example of an embodiment, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or MMCmicro), an SD card (SD, miniSD, microSD, or SDHC), or universal flash memory (UFS).

[0172] The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive SSD includes a storage device configured to store data in the semiconductor memory. If the memory system 1000 is used as a semiconductor drive SSD, the operating speed of the host coupled to the memory system 1000 can be significantly improved.

[0173] As another example, the memory system 1000 may be provided as one of various components of an electronic device such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting / receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

[0174] In one example of an embodiment, the semiconductor memory device 100 or memory system 1000 may be packaged in various forms. For example, the semiconductor memory device 100 or memory system 1000 may be packaged in a manner such as: stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle packaged die, wafer-scale die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processing stacked package (WSP).

[0175] Figure 19 It's a diagram. Figure 18 A block diagram illustrating an application example of the memory system.

[0176] refer to Figure 19 The memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes multiple semiconductor memory chips. The multiple semiconductor memory chips are divided into multiple groups.

[0177] exist Figure 19 The diagram illustrates multiple groups communicating with controller 2200 via channels CH1 to CHk, from the first to the kth. Each semiconductor memory chip can communicate with a reference... Figure 1 The semiconductor memory device 100 described is configured and operated in the same manner.

[0178] Each group communicates with controller 2200 through a common channel. Controller 2200 and reference... Figure 18 The controller 1100 described is configured similarly. The controller 2200 controls multiple memory chips of the semiconductor memory device 2100 through multiple channels CH1 to CHk.

[0179] Figure 20 It is illustrated, including references. Figure 19 A block diagram of the computing system describing the memory system.

[0180] refer to Figure 20 The computing system 3000 includes a central processing unit 3100, RAM 3200, user interface 3300, power supply 3400, system bus 3500 and memory system 2000.

[0181] The memory system 2000 is electrically coupled to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0182] exist Figure 20 The diagram illustrates a semiconductor memory device 2100 coupled to the system bus 3500 via a controller 2200. However, the semiconductor memory device 2100 can also be directly coupled to the system bus 3500. The functions of the controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

[0183] exist Figure 20 The diagram in the middle provides a reference. Figure 19 The memory system 2000 is described herein. However, the memory system 2000 can be derived from references. Figure 18 The described memory system 1000 is replaced. In one example of an embodiment, the computing system 3000 may include reference... Figure 18 and Figure 19 The memory systems described are 1000 and 2000.

[0184] According to this disclosure, in one embodiment, a semiconductor memory device with improved programming speed and a method of operating the semiconductor memory device can be provided.

[0185] While this disclosure has been shown and described with reference to certain embodiments thereof, those skilled in the art will understand that various changes may be made to its form and details without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0186] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, those skilled in the art should understand that various modifications can be made based on the technical scope of this disclosure.

[0187] Furthermore, embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, these are merely for explaining the embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can be made within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure, in addition to the embodiments disclosed herein.

Claims

1. A semiconductor memory device, comprising: A memory cell array, comprising multiple memory cells; The peripheral circuitry is configured to perform programming operations on a selected memory cell among the plurality of memory cells; as well as The control logic is configured to control the programming operations of the peripheral circuitry. The control logic described herein: During the first programming period, the peripheral circuitry is controlled to perform the programming operation on the selected memory cell by using a first programming voltage determined based on a first step voltage; as well as During a second programming period following the first programming period, the peripheral circuitry is controlled to perform the programming operation on the selected memory cell using a second programming voltage determined based on a second step voltage, which is different from the first step voltage. The first programming period includes the first programming loop to the kth programming loop, and the second programming period includes the (k+1)th programming loop and the subsequent programming loops. Where k is a natural number of 2 or greater, and The control logic therein determines k based on the programming start voltage applied in the first programming cycle.

2. The semiconductor memory device of claim 1, wherein the first step voltage is greater than the second step voltage.

3. The semiconductor memory device of claim 1, wherein the control logic determines the first step voltage based on the number of memory cells with a threshold voltage greater than a reference voltage as a result of executing the first programming loop.

4. The semiconductor memory device of claim 3, wherein the control logic changes the first step voltage based on the number of memory cells whose threshold voltage is greater than the reference voltage as a result of executing a second programming cycle after the first programming cycle.

5. The semiconductor memory device of claim 3, wherein the semiconductor memory device uses a lookup table to determine a first step voltage value corresponding to the number of memory cells whose threshold voltage is greater than the reference voltage.

6. A method of operating a semiconductor memory device, the method comprising a plurality of programming loops, At least some of the programming loops mentioned above include: The step voltage is determined based on the comparison between the threshold loop number and the current programmed loop number. The programming voltage is determined based on the step voltage; The programming voltage is applied to the selected memory cell; as well as A verification operation is performed on the selected memory cell, and Determining the step voltage includes: determining the threshold cycle number based on the initial programming voltage applied in the first programming cycle among the plurality of programming cycles.

7. The method of claim 6, wherein determining the step voltage further comprises: When the current number of programming cycles is less than the threshold number of cycles, the first voltage is determined as the step voltage; and Determining the programming voltage includes: determining the value obtained by adding the step voltage to the previous programming voltage of the previous programming cycle as the programming voltage of the current programming cycle.

8. The method of claim 7, wherein determining the step voltage further comprises: When the current programming loop number is not less than the threshold loop number, the second voltage, which is different from the first voltage, is determined as the step voltage.

9. The method of claim 8, wherein the second voltage is lower than the first voltage.

10. The method of claim 7, wherein the first programming loop comprises: The initial programming voltage is applied to the selected memory cell; Count the number of memory cells whose threshold voltage is greater than the reference voltage; as well as The first voltage is determined based on the number of memory cells whose threshold voltage is greater than the reference voltage.

11. The method of claim 6, wherein determining the step voltage further comprises: When the current programming loop number is less than the threshold loop number, the number of memory cells with a threshold voltage greater than the reference voltage is counted. as well as The step voltage is determined based on the number of memory cells whose threshold voltage is greater than the reference voltage; and Determining the programming voltage includes: determining the value obtained by adding the step voltage to the previous programming voltage of the previous programming cycle as the programming voltage of the current programming cycle.

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