GaN HEMT devices integrating P-type and N-type and their fabrication methods

Abstract

The application provides a GaN HEMT device integrated with P-type and N-type and a preparation method thereof. The GaN HEMT device integrated with P-type and N-type is prepared based on the same epitaxial structure, and photolithography is performed on the same horizontal line, so that the precision is high, the preparation process is simple, and the repeatability is high, thereby the GaN HEMT device integrated with P-type and N-type and having high performance can be prepared at low cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a GaN HEMT device integrating P-type and N-type and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, has become a widely studied and applied semiconductor material due to its large bandgap (3.4 eV), high breakdown field strength, excellent thermal conductivity, and high electron saturation velocity.

[0003] In existing semiconductor devices, Si-CMOS technology, which integrates both Si N-MOSFETs and Si P-MOSFETs, is widely used. In this process, when the N-type device is on, the P-type device is off, and vice versa. However, unlike Si-based CMOS technology, simultaneously fabricating N-type and P-type GaN HEMTs (High Electron Mobility Transistors) on the same wafer is challenging. It typically requires different epitaxial layer structures to fabricate different device types. For example: one method is to fabricate P-type and N-type devices separately on different wafers and then bond them together using substrate transfer technology; another method is to epitaxially grow different structures in one step, with the upper part being P-type and the lower part N-type, and then etch away the upper P-type epitaxial layer in the area where the N-type device is fabricated to obtain the desired epitaxial structure. This involves epitaxial etching and photolithography at different heights, affecting accuracy; yet another method is to epitaxially grow the desired structure in two separate steps in different regions, and then fabricate P-type and N-type devices based on these. All these fabrication methods are relatively complex and costly.

[0004] Therefore, it is necessary to provide a GaN HEMT device that integrates P-type and N-type and its fabrication method. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an integrated P-type and N-type GaN HEMT device and its fabrication method, so as to solve the problems of complex fabrication process and high cost of integrated P-type and N-type GaN HEMT devices in the prior art.

[0006] To achieve the above and other related objectives, this invention provides a method for fabricating an integrated P-type and N-type GaN HEMT device, comprising the following steps:

[0007] Provide substrate;

[0008] An epitaxial structure is formed on the substrate, the epitaxial structure comprising a first GaN channel layer, an AlGaN barrier layer and a second GaN channel layer stacked from bottom to top;

[0009] A first AlN protective layer is formed on the second GaN channel layer. P-type ion implantation is performed based on the first AlN protective layer. The first AlN protective layer is removed, and a first passivation protective layer is formed on the second GaN channel layer. A first annealing is performed, and the first passivation protective layer is removed to form a P-type region. The P-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer.

[0010] A second AlN protective layer is formed on the second GaN channel layer. N-type ion implantation is performed based on the second AlN protective layer. The second AlN protective layer is removed. A second passivation protective layer is formed on the second GaN channel layer. A second annealing is performed. The second passivation protective layer is removed to form an N-type region. The N-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer.

[0011] A first silicon nitride dielectric layer and a second silicon nitride dielectric layer are formed on the second GaN channel layer from bottom to top, and the refractive index of the first silicon nitride dielectric layer is greater than the refractive index of the second silicon nitride dielectric layer.

[0012] Nitrogen ion implantation is performed to form an isolation structure between the P-type region and the N-type region;

[0013] The first silicon nitride dielectric layer and the second silicon nitride dielectric layer are patterned to form a groove located between the N-type regions and on the AlGaN barrier layer;

[0014] A P-type device source / drain electrode in contact with the P-type region, an N-type device source / drain electrode in contact with the N-type region, a P-type device gate electrode located between the P-type regions and on the second GaN channel layer, and an N-type device gate electrode located in the groove are formed.

[0015] Optionally, the refractive index of the first silicon nitride dielectric layer is 2.4 to 2.5, and the refractive index of the second silicon nitride dielectric layer is 1.9 to 2.0.

[0016] Optionally, a portion of the second GaN channel layer is reserved at the bottom of the formed groove, or the formed groove penetrates the second GaN channel layer.

[0017] Optionally, the step of forming the P-type region includes:

[0018] The steps for forming the P-type region include:

[0019] At 250°C, a first AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample by PEALD.

[0020] Mg ion implantation was performed at an energy of 30–60 keV and a dose of 1–2e¹⁵ / cm². 2 ;

[0021] The first AlN layer was removed using KOH;

[0022] At 350℃, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD.

[0023] Perform the first annealing at a temperature of 1200–1230℃ for 20–30 minutes;

[0024] Use BOE to remove the passivation protective layer;

[0025] The steps for forming the N-type region include:

[0026] At 250°C, a second AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample using PEALD.

[0027] Si ion implantation was performed at an implantation energy of 45–65 keV and a dose of 2–4e¹⁵ / cm². 2 ;

[0028] The second AlN layer was removed using KOH;

[0029] At 350℃, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD.

[0030] Perform a second annealing at a temperature of 1140–1160℃ for 15–30 minutes;

[0031] Use BOE to remove the passivation protective layer.

[0032] Optionally, the same metal is deposited simultaneously to form the source / drain electrode of the P-type device and the gate electrode of the N-type device; the same metal is deposited simultaneously to form the source / drain electrode of the N-type device and the gate electrode of the P-type device.

[0033] Optionally, the N-type region is formed first, followed by the P-type region.

[0034] The present invention also provides a GaN HEMT device integrating P-type and N-type, the GaN HEMT device comprising:

[0035] Substrate;

[0036] An epitaxial structure located on the substrate, the epitaxial structure comprising a first GaN channel layer, an AlGaN barrier layer and a second GaN channel layer stacked from bottom to top;

[0037] The P-type region and the N-type region respectively penetrate the second GaN channel layer and the AlGaN barrier layer and extend to the bottom into the first GaN channel layer;

[0038] An isolation structure is located between the P-type region and the N-type region;

[0039] A first silicon nitride dielectric layer and a second silicon nitride dielectric layer are stacked from bottom to top on the second GaN channel layer, and the refractive index of the first silicon nitride dielectric layer is greater than the refractive index of the second silicon nitride dielectric layer.

[0040] The groove located between the N-type regions and on the AlGaN barrier layer;

[0041] The P-type device source / drain electrode penetrates the first silicon nitride dielectric layer and the second silicon nitride dielectric layer and is in contact with the P-type region; the N-type device source / drain electrode is in contact with the N-type region; the P-type device gate electrode is located between the P-type regions and on the second GaN channel layer; and the N-type device gate electrode is located in the groove.

[0042] Optionally, the refractive index of the first silicon nitride dielectric layer is 2.4 to 2.5, and the refractive index of the second silicon nitride dielectric layer is 1.9 to 2.0.

[0043] Optionally, a portion of the second GaN channel layer is reserved at the bottom of the groove, or the groove penetrates the second GaN channel layer.

[0044] Optionally, the thickness of the first GaN channel layer is 50–200 nm, and the AlGaN barrier layer is Al x Ga 1-x The N layer has a thickness of 5–30 nm (0.2 < x ≤ 1); the second GaN channel layer has a thickness of 20–100 nm; the first silicon nitride dielectric layer has a thickness of 10–20 nm; and the second silicon nitride dielectric layer has a thickness of 10–100 nm.

[0045] As described above, the GaN HEMT device integrating P-type and N-type and its fabrication method of the present invention are fabricated based on the same epitaxial structure, and photolithography is performed on the same horizontal line, which has high precision. Moreover, the fabrication process is simple and highly repeatable, thereby enabling the low-cost fabrication of high-performance GaN HEMT devices that simultaneously integrate P-type and N-type. Attached Figure Description

[0046] Figure 1 The diagram shows a process flow diagram for fabricating GaN HEMT devices in an embodiment of the present invention.

[0047] Figure 2 The diagram shown is a schematic representation of the epitaxial structure in an embodiment of the present invention.

[0048] Figure 3 The diagram shows the structure after the P-type and N-type regions are formed in the embodiment of the invention.

[0049] Figure 4 The diagram shows the structure after the formation of the first silicon nitride dielectric layer and the second silicon nitride dielectric layer in an embodiment of the invention.

[0050] Figure 5 The diagram shown is a schematic representation of the structure after the isolation structure is formed in an embodiment of the invention.

[0051] Figure 6 The diagram shows the structure after the groove is formed in an embodiment of the invention.

[0052] Figure 7 The diagram shows the structure after forming the source / drain electrodes of the P-type device and the gate electrode of the N-type device in an embodiment of the present invention.

[0053] Figure 8 The diagram shows the structure after forming the source / drain electrodes of the N-type device and the gate electrode of the P-type device in an embodiment of the present invention.

[0054] Component designation explanation

[0055] 100 First GaN Channel Layer

[0056] 200 AlGaN barrier layer

[0057] 300 Second GaN Channel Layer

[0058] 400 P-type area

[0059] 500 N-type area

[0060] 601 First silicon nitride dielectric layer

[0061] 602 Second silicon nitride dielectric layer

[0062] 701 P-type device source electrode

[0063] 702 P-type device drain electrode

[0064] 703 P-type device gate electrode

[0065] 704 N-type device source electrode

[0066] 705 N-type device drain electrode

[0067] 706 N-type device gate electrode

[0068] 800 isolation structure

[0069] Steps S1 to S8

[0070] a 2DHG area

[0071] b 2DEG area

[0072] AP type devices

[0073] BN type devices Detailed Implementation

[0074] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0075] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0076] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0077] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0078] like Figure 1 This embodiment provides a method for fabricating a GaN HEMT device integrating P-type and N-type, including the following steps:

[0079] S1: Provides a substrate;

[0080] S2: An epitaxial structure is formed on the substrate, the epitaxial structure comprising a first GaN channel layer, an AlGaN barrier layer and a second GaN channel layer stacked from bottom to top;

[0081] S3: A first AlN protective layer is formed on the second GaN channel layer. P-type ion implantation is performed based on the first AlN protective layer. The first AlN protective layer is removed. A first passivation protective layer is formed on the second GaN channel layer. A first annealing is performed. The first passivation protective layer is removed to form a P-type region. The P-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer.

[0082] S4: A second AlN protective layer is formed on the second GaN channel layer. N-type ion implantation is performed based on the second AlN protective layer. The second AlN protective layer is removed. A second passivation protective layer is formed on the second GaN channel layer. A second annealing is performed. The second passivation protective layer is removed to form an N-type region. The N-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer.

[0083] S5: A first silicon nitride dielectric layer and a second silicon nitride dielectric layer are formed on the second GaN channel layer from bottom to top, and the refractive index of the first silicon nitride dielectric layer is greater than the refractive index of the second silicon nitride dielectric layer.

[0084] S6: Perform nitrogen ion implantation to form an isolation structure between the P-type region and the N-type region;

[0085] S7: Pattern the first silicon nitride dielectric layer and the second silicon nitride dielectric layer to form a groove located between the N-type regions and on the AlGaN barrier layer;

[0086] S8: Form a P-type device source / drain electrode in contact with the P-type region, an N-type device source / drain electrode in contact with the N-type region, a P-type device gate electrode located between the P-type regions and on the second GaN channel layer, and an N-type device gate electrode located in the groove.

[0087] In this embodiment, the GaN HEMT device integrating P-type and N-type is fabricated based on the same epitaxial structure. Photolithography is performed on the same horizontal line, which has high precision and the fabrication process is simple and highly repeatable. Therefore, the GaN HEMT device with high performance and simultaneous integration of P-type and N-type can be fabricated at low cost.

[0088] The following is in conjunction with the instruction manual. Figure 2 ~Attached Figure 8 The fabrication and structure of the GaN HEMT device are described.

[0089] First, refer to Figure 1 and Figure 2 Steps S1 and S2 are performed to provide a substrate (not shown) and form an epitaxial structure on the substrate. The epitaxial structure includes a first GaN channel layer 100, an AlGaN barrier layer 200 and a second GaN channel layer 300 stacked from bottom to top.

[0090] Specifically, the substrate can be a conventional substrate, such as a sapphire substrate, a SiC substrate, a GaN substrate, or a Si substrate, etc. The specific type is not limited here and can be selected as needed.

[0091] Then, the first GaN channel layer 100, the AlGaN barrier layer 200, and the second GaN channel layer 300 are sequentially epitaxially formed on the substrate.

[0092] The first GaN channel layer 100 and the AlGaN barrier layer 200 form an AlGaN / GaN heterojunction to provide a 2DEG region b, which is used as a channel for the N-type device B; the AlGaN barrier layer 200 and the second GaN channel layer 300 form an AlGaN / GaN heterojunction to provide a 2DHG region a, which is used as a channel for the P-type device A.

[0093] As an example, the thickness of the first GaN channel layer 100 can be 50–200 nm, such as 50 nm, 100 nm, 150 nm, 200 nm, etc.; the AlGaN barrier layer 200 can be Al x Ga 1-x N layers, 0.2 < x ≤ 1, such as 0.3, 0.5, 0.6, 1, etc., with a thickness of 5–30 nm, such as 5 nm, 10 nm, 15 nm, 30 nm, etc., and the higher the content of Al component, the more Al... xGa 1-x The thinner the N layer, the better; the thickness of the second GaN channel layer 300 can be 20-100nm, such as 20nm, 40nm, 50nm, 100nm, etc.

[0094] Furthermore, in the epitaxial structure, an Al-like layer may be formed between the substrate and the first GaN channel layer 100. y Ga 1-y An N-buffer layer, wherein 0 < y ≤ 1, and the y-value farther from the substrate is smaller than the y-value of the adjacent substrate, is used to alleviate the problems of lattice mismatch and thermal expansion coefficient mismatch between the substrate and the first GaN channel layer 100. Regarding the Al... y Ga 1-y The specific composition and thickness of the N buffer layer are not specified here.

[0095] Next, refer to Figure 1 and Figure 3 Execute steps S3 and S4 to form P-type region 400 and N-type region 500, including:

[0096] A first AlN protective layer (not shown) is formed on the second GaN channel layer 300. P-type ion implantation is performed based on the first AlN protective layer. The first AlN protective layer is then removed, and a first passivation protective layer (not shown) is formed on the second GaN channel layer 300. A first annealing process is performed, and the first passivation protective layer is removed to form the P-type region 400. The P-type region 400 penetrates the second GaN channel layer 300 and the AlGaN barrier layer 200, and its bottom extends into the first GaN channel layer 100.

[0097] A second AlN protective layer (not shown) is formed on the second GaN channel layer 300. N-type ion implantation is performed based on the second AlN protective layer. The second AlN protective layer is removed, and a second passivation protective layer (not shown) is formed on the second GaN channel layer 300. A second annealing is performed, and the second passivation protective layer is removed to form the N-type region 500. The N-type region 500 penetrates the second GaN channel layer 300 and the AlGaN barrier layer 200 and extends to the bottom of the first GaN channel layer 100.

[0098] Specifically, the P-type region 400 may be formed in the epitaxial structure first, and then the N-type region 500 may be formed. Alternatively, the N-type region 500 may be formed in the epitaxial structure first, and then the P-type region 400 may be formed. The order in which the P-type region 400 and the N-type region 500 are formed is not overly restricted here.

[0099] When forming the P-type region 400 and the N-type region 500, the first AlN protective layer and the second AlN protective layer cover the surface to prevent amorphization and roughening of the surface of the topmost second GaN channel layer 300 due to ion implantation damage, thereby reducing implantation damage.

[0100] As an example, the first passivation protection layer may include a SiO2 passivation protection layer or a Si3N4 passivation protection layer; the second passivation protection layer may include a SiO2 passivation protection layer or a Si3N4 passivation protection layer; the first passivation protection layer and the second passivation protection layer can suppress the surface decomposition of GaN material during the high-temperature annealing process.

[0101] The step of forming the P-type region 400 may include:

[0102] At 250°C, a first AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample using PEALD (plasma-enhanced atomic layer deposition).

[0103] Mg ion implantation is performed at energies of 30–60 keV, such as 30 keV, 50 keV, and 60 keV, with a dose of 1–2e¹⁵ / cm². 2 , such as 1e15 / cm 2 1.5e15 / cm 2 2e15 / cm 2 wait;

[0104] The first AlN layer was removed using KOH;

[0105] At 350°C, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD (plasma-enhanced chemical vapor deposition) or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD.

[0106] The first annealing is carried out at a temperature of 1200-1230℃, such as 1200℃, 1210℃, 1220℃, 1230℃, etc., and for a time of 20min-30min, such as 20min, 25min, 30min, etc.

[0107] The passivation protective layer is removed using BOE (buffered oxide etching).

[0108] The steps for forming the N-type region may include:

[0109] At 250°C, a second AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample using PEALD (plasma-enhanced atomic layer deposition).

[0110] Si ion implantation is performed at energies of 45–65 keV, such as 45 keV, 50 keV, and 65 keV, with a dose of 2–4e15 / cm². 2 , such as 2e15 / cm 2 3e15 / cm 2 4e15 / cm 2 wait;

[0111] The second AlN layer was removed using KOH;

[0112] At 350°C, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD (plasma-enhanced chemical vapor deposition) or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD.

[0113] Perform a second annealing at a temperature of 1140–1160℃, such as 1140℃, 1150℃, 1160℃, etc., for a time of 15 min–30 min, such as 15 min, 25 min, 30 min, etc.

[0114] The passivation protective layer is removed using BOE (buffered oxide etching).

[0115] Next, refer to Figure 1 and Figure 4 In step S5, a first silicon nitride dielectric layer 601 and a second silicon nitride dielectric layer 602 are formed on the second GaN channel layer 300 from bottom to top, wherein the refractive index of the first silicon nitride dielectric layer 601 is greater than the refractive index of the second silicon nitride dielectric layer 602.

[0116] Specifically, a bilayer silicon nitride dielectric layer can be prepared using PECVD (plasma-enhanced chemical vapor deposition). The lower layer is a Si-rich first silicon nitride dielectric layer 601 with a thickness of 10nm to 20nm, such as 10nm, 15nm, or 20nm. During the deposition process, SiH4 and NH3 can be used as precursor gases, and the SiH4:NH3 ratio is relatively high, such as 400:2sccm. The upper layer is a silicon nitride dielectric layer with a conventional ratio and a thickness of 10nm to 100nm, such as 10nm, 25nm, 50nm, or 100nm. During the deposition process, SiH4 and NH3 can be used as precursor gases, and the SiH4:NH3 ratio is relatively low, such as 100:2sccm. This forms a Si-rich first silicon nitride dielectric layer 601 with a high refractive index at the bottom, and a conventional second silicon nitride dielectric layer 602 with a lower refractive index at the top. By passivating the double-layer dielectric, especially the passivation of the first silicon nitride dielectric layer 601 rich in Si at the bottom, the interface trap revival / release process can be effectively improved, thereby effectively suppressing the current collapse effect.

[0117] As an example, the refractive index of the first silicon nitride dielectric layer 601 formed can be 2.4 to 2.5, such as 2.4, 2.45, 2.5, etc., and the refractive index of the second silicon nitride dielectric layer 602 formed can be 1.9 to 2.0, such as 1.9, 1.95, 2.0, etc.

[0118] Next, refer to Figure 1 and Figure 5 Step S6 is executed to perform nitrogen ion implantation, forming an isolation structure 800 between the P-type region 400 and the N-type region 500.

[0119] Specifically, during the formation of the high-resistivity isolation structure 800 through nitrogen ion implantation, the surface of the epitaxial structure can be protected by the stacked first silicon nitride dielectric layer 601 and second silicon nitride dielectric layer 602 to prevent damage to the surface material. The formed isolation structure 800 penetrates both the 2DHG region a and the 2DEG region b, thereby providing electrical isolation between the P-type device A and the N-type device B. The energy and dosage of the nitrogen ion implantation are not limited here.

[0120] Next, refer to Figure 1 and Figure 6 In step S7, the first silicon nitride dielectric layer 601 and the second silicon nitride dielectric layer 602 are patterned to form a groove 301 located between the N-type regions 500 and on the AlGaN barrier layer 200.

[0121] As an example, the bottom of the formed groove 301 may have a portion of the second GaN channel layer 300 reserved, or the formed groove 301 may penetrate the second GaN channel layer 300.

[0122] For details, please refer to Figure 6 In this embodiment, the bottom of the formed groove 301 preferably has a portion of the second GaN channel layer 300 reserved, so that the reserved portion of the second GaN channel layer 300 serves as the cap layer of the N-type device B, thereby improving gate reliability. Of course, if necessary, the groove 301 may also penetrate through the second GaN channel layer 300.

[0123] In this embodiment, the step of preparing the groove 301 may include:

[0124] The gate region of the N-type device B is defined using photolithography;

[0125] The first silicon nitride dielectric layer 601 and the second silicon nitride dielectric layer 602 at the gate region are removed by ICP (inductively coupled plasma) dry etching to expose the second GaN channel layer 300.

[0126] Most of the second GaN channel layer 300 is removed by ICP dry etching, leaving a second GaN channel layer 300 with a thickness of 1 to 5 nm, such as 1 nm, 2 nm, 3 nm, 5 nm, etc.

[0127] The second GaN channel layer 300 after ICP dry etching is further treated with 25% TMAH (tetramethylammonium hydroxide) at 80°C for 10 minutes to eliminate ion damage during the ICP dry etching process and make the etched surface smooth.

[0128] Next, refer to Figure 1 , Figure 7 and Figure 8 Step S8 is executed to form a P-type device source electrode 701 in contact with the P-type region 400, a P-type device drain electrode 702 in contact with the P-type region 400, an N-type device source electrode 704 in contact with the N-type region 500, an N-type device drain electrode 705 in contact with the N-type region 500, a P-type device gate electrode 703 located between the P-type regions 400 and on the second GaN channel layer 300, and an N-type device gate electrode 706 located in the groove 301.

[0129] As an example, the same metal is deposited simultaneously to form the source electrode 701 of the P-type device, the drain electrode 702 of the P-type device, and the gate electrode 706 of the N-type device; the same metal is deposited simultaneously to form the source electrode 704 of the N-type device, the drain electrode 705 of the N-type device, and the gate electrode 703 of the P-type device.

[0130] Specifically, such as Figure 7 After forming the groove 301, the source and drain electrode regions of the P-type device A can be defined using photolithography. Then, a double-layer silicon nitride dielectric layer located in the source and drain electrode regions of the P-type device A is etched. Next, using photolithography, the same metal, such as Ni / Au, is simultaneously deposited to form the P-type device source electrode 701, the P-type device drain electrode 702, and the N-type device gate electrode 706; and as... Figure 8 The source and drain electrode regions of the N-type device B and the gate electrode region of the P-type device A are defined by photolithography. Then, a double-layer silicon nitride dielectric layer is simultaneously etched, followed by simultaneous deposition of the same metal, such as Ti / Au or Ti / Al / Ni / Au, to form the source electrode 704, drain electrode 705, and gate electrode 703 of the N-type device. In this embodiment, to simplify the process, it is preferable to simultaneously deposit the same metal to form the source electrode 701, drain electrode 702, and gate electrode 706 of the P-type device, and simultaneously deposit the same metal to form the source electrode 704, drain electrode 705, and gate electrode 703 of the N-type device. In another embodiment, the source, drain, and gate electrodes of different types of devices can, of course, be fabricated separately; this is not an overly restrictive approach.

[0131] See Figure 8 This embodiment also provides a GaN HEMT device integrating P-type and N-type, the GaN HEMT device comprising:

[0132] Substrate (not shown);

[0133] An epitaxial structure located on the substrate, the epitaxial structure comprising a first GaN channel layer 100, an AlGaN barrier layer 200 and a second GaN channel layer 300 stacked from bottom to top;

[0134] P-type region 400 and N-type region 500, respectively, both the P-type region 400 and the N-type region 500 penetrate the second GaN channel layer 300 and the AlGaN barrier layer 200 and extend to the bottom into the first GaN channel layer 100.

[0135] An isolation structure 800 is located between the P-type region 400 and the N-type region 500;

[0136] A first silicon nitride dielectric layer 601 and a second silicon nitride dielectric layer 602 are stacked from bottom to top on the second GaN channel layer 300, and the refractive index of the first silicon nitride dielectric layer 601 is greater than the refractive index of the second silicon nitride dielectric layer 602.

[0137] The groove located between the N-type regions 500 and on the AlGaN barrier layer 200;

[0138] The P-type device source electrode 701 and P-type device drain electrode 702 penetrate the first silicon nitride dielectric layer 601 and the second silicon nitride dielectric layer 602 and are in contact with the P-type region 400; the N-type device source electrode 704 and N-type device drain electrode 705 are in contact with the N-type region 500; the P-type device gate electrode 703 is located between the P-type regions 400 and on the second GaN channel layer 300; and the N-type device gate electrode 706 is located in the groove.

[0139] The GaN HEMT device described in this embodiment can be fabricated using the above-described fabrication method, but is not limited to the above fabrication process. The GaN HEMT device in this embodiment is directly fabricated using the above-described fabrication method, and therefore, information regarding the materials and fabrication of the GaNHEMT device can be found in the above-described fabrication method.

[0140] As an example, the refractive index of the first silicon nitride dielectric layer 601 is 2.4 to 2.5, and the refractive index of the second silicon nitride dielectric layer 602 is 1.9 to 2.0.

[0141] Specifically, the stacked silicon nitride dielectric layers effectively improve the interface trap reactivation / release process, thereby effectively suppressing the current collapse effect. The refractive index of the first silicon nitride dielectric layer 601 can be 2.4–2.5, such as 2.4, 2.45, 2.5, etc., and the refractive index of the second silicon nitride dielectric layer 602 can be 1.9–2.0, such as 1.9, 1.95, 2.0, etc. The thickness of the first silicon nitride dielectric layer 601 can be 10 nm–20 nm, such as 10 nm, 15 nm, 20 nm, etc., and the thickness of the second silicon nitride dielectric layer 602 can be 10 nm–100 nm, such as 10 nm, 25 nm, 50 nm, 100 nm, etc.

[0142] As an example, the bottom of the groove may have a portion of the second GaN channel layer 300 reserved, or the groove may extend through the second GaN channel layer 300.

[0143] Specifically, in this embodiment, as follows: Figure 8The bottom of the groove has a portion of the second GaN channel layer 300 reserved, which serves as a cap layer for the N-type device B to improve gate reliability. Alternatively, the groove can extend through the second GaN channel layer 300 as needed.

[0144] As an example, the thickness of the first GaN channel layer 100 can be 50–200 nm, such as 50 nm, 100 nm, 150 nm, 200 nm, etc.; the AlGaN barrier layer 200 can be Al x Ga 1-x N layers, 0.2 < x ≤ 1, such as 0.3, 0.5, 0.6, 1, etc., with a thickness of 5–30 nm, such as 5 nm, 10 nm, 15 nm, 30 nm, etc., and the higher the content of Al component, the more Al... x Ga 1-x The thinner the N layer, the better; the thickness of the second GaN channel layer 300 can be 20-100nm, such as 20nm, 40nm, 50nm, 100nm, etc.

[0145] Furthermore, in the epitaxial structure, an Al-like layer may be formed between the substrate and the first GaN channel layer 100. y Ga 1-y An N-buffer layer, wherein 0 < y ≤ 1, and the y-value farther from the substrate is smaller than the y-value of the adjacent substrate, is used to alleviate the problems of lattice mismatch and thermal expansion coefficient mismatch between the substrate and the first GaN channel layer 100. Regarding the Al... y Ga 1-y The specific composition and thickness of the N buffer layer are not specified here.

[0146] As an example, the substrate may include a sapphire substrate, a SiC substrate, a GaN substrate, or a Si substrate, etc. The specific type is not limited here and can be selected as needed.

[0147] In summary, the GaN HEMT device integrating P-type and N-type structures and its fabrication method of the present invention fabricate the GaN HEMT device integrating P-type and N-type structures based on the same epitaxial structure, perform photolithography on the same horizontal line, achieve high precision, and have a simple fabrication process with high repeatability. Therefore, it is possible to fabricate the high-performance GaN HEMT device that integrates P-type and N-type structures at low cost.

[0148] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an integrated P-type and N-type GaN HEMT device, characterized in that, Includes the following steps: Provide substrate; An epitaxial structure is formed on the substrate, the epitaxial structure comprising a first GaN channel layer, an AlGaN barrier layer and a second GaN channel layer stacked from bottom to top; A first AlN protective layer is formed on the second GaN channel layer. P-type ion implantation is performed based on the first AlN protective layer. The first AlN protective layer is removed, and a first passivation protective layer is formed on the second GaN channel layer. A first annealing is performed, and the first passivation protective layer is removed to form a P-type region. The P-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer. A second AlN protective layer is formed on the second GaN channel layer. N-type ion implantation is performed based on the second AlN protective layer. The second AlN protective layer is removed. A second passivation protective layer is formed on the second GaN channel layer. A second annealing is performed. The second passivation protective layer is removed to form an N-type region. The N-type region penetrates the second GaN channel layer and the AlGaN barrier layer and extends to the bottom of the first GaN channel layer. A first silicon nitride dielectric layer and a second silicon nitride dielectric layer are formed on the second GaN channel layer from bottom to top, and the refractive index of the first silicon nitride dielectric layer is greater than the refractive index of the second silicon nitride dielectric layer. Nitrogen ion implantation is performed to form an isolation structure between the P-type region and the N-type region; The first silicon nitride dielectric layer and the second silicon nitride dielectric layer are patterned to form a groove located between the N-type regions and on the AlGaN barrier layer; A P-type device source / drain electrode in contact with the P-type region, an N-type device source / drain electrode in contact with the N-type region, a P-type device gate electrode located between the P-type regions and on the second GaN channel layer, and an N-type device gate electrode located in the groove are formed.

2. The method for fabricating a GaN HEMT device according to claim 1, characterized in that: The refractive index of the first silicon nitride dielectric layer is 2.4 to 2.5, and the refractive index of the second silicon nitride dielectric layer is 1.9 to 2.

0.

3. The method for fabricating a GaN HEMT device according to claim 1, characterized in that: The bottom of the formed groove has a portion of the second GaN channel layer reserved, or the formed groove penetrates the second GaN channel layer.

4. The method for fabricating a GaN HEMT device according to claim 1, characterized in that: The steps for forming the P-type region include: At 250°C, a first AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample by PEALD. Mg ion implantation was performed at an energy of 30–60 keV and a dose of 1–2e¹⁵ / cm². 2 ; The first AlN layer was removed using KOH; At 350℃, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD. Perform the first annealing at a temperature of 1200–1230℃ for 20–30 minutes; Use BOE to remove the passivation protective layer; The steps for forming the N-type region include: At 250°C, a second AlN layer with a thickness of 20 nm was deposited on the entire surface of the sample using PEALD. Si ion implantation was performed at an implantation energy of 45–65 keV and a dose of 2–4e¹⁵ / cm². 2 ; The second AlN layer was removed using KOH; At 350℃, a 200 nm thick SiO2 passivation protective layer was deposited on the sample by PECVD or a 200 nm thick Si3N4 passivation protective layer was deposited on the sample by LPCVD. Perform a second annealing at a temperature of 1140–1160℃ for 15–30 minutes; BOE is used to remove the passivation protective layer.

5. The method for fabricating a GaN HEMT device according to claim 1, characterized in that: Simultaneously depositing the same metal to form the source / drain electrode of the P-type device and the gate electrode of the N-type device; simultaneously depositing the same metal to form the source / drain electrode of the N-type device and the gate electrode of the P-type device.

6. The method for fabricating a GaN HEMT device according to claim 1, characterized in that: The N-type region is formed first, and then the P-type region is formed.

7. A GaN HEMT device integrating P-type and N-type, characterized in that, The GaN HEMT device includes: Substrate; An epitaxial structure located on the substrate, the epitaxial structure comprising a first GaN channel layer, an AlGaN barrier layer and a second GaN channel layer stacked from bottom to top; The P-type region and the N-type region respectively penetrate the second GaN channel layer and the AlGaN barrier layer and extend to the bottom into the first GaN channel layer; An isolation structure is located between the P-type region and the N-type region; A first silicon nitride dielectric layer and a second silicon nitride dielectric layer are stacked from bottom to top on the second GaN channel layer, and the refractive index of the first silicon nitride dielectric layer is greater than the refractive index of the second silicon nitride dielectric layer. The groove located between the N-type regions and on the AlGaN barrier layer; The P-type device source / drain electrode penetrates the first silicon nitride dielectric layer and the second silicon nitride dielectric layer and is in contact with the P-type region; the N-type device source / drain electrode is in contact with the N-type region; the P-type device gate electrode is located between the P-type regions and on the second GaN channel layer; and the N-type device gate electrode is located in the groove.

8. The GaN HEMT device according to claim 7, characterized in that: The refractive index of the first silicon nitride dielectric layer is 2.4 to 2.5, and the refractive index of the second silicon nitride dielectric layer is 1.9 to 2.

0.

9. The GaN HEMT device according to claim 7, characterized in that: The bottom of the groove has a portion of the second GaN channel layer reserved, or the groove penetrates the second GaN channel layer.

10. The GaN HEMT device according to claim 7, characterized in that: The thickness of the first GaN channel layer is 50–200 nm, and the AlGaN barrier layer is Al x Ga 1-x The N layer has a thickness of 5–30 nm (0.2 < x ≤ 1); the second GaN channel layer has a thickness of 20–100 nm; the first silicon nitride dielectric layer has a thickness of 10–20 nm; and the second silicon nitride dielectric layer has a thickness of 10–100 nm.

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