Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a protective material layer on the initial second device layer, the gate opening sidewall and bottom surface, and the initial via sidewall and bottom surface; forming a patterned layer covering the protective material layer, the patterned layer having a first opening on the initial via; forming a shielding layer on the first opening sidewall, the shielding layer having a second opening, the second opening having a second projection on the first dielectric layer surface, the second projection being within the range of the first projection; and etching the protective material layer and the first dielectric layer at the bottom of the initial via with the shielding layer as a mask to form a via exposing the top surface of the first gate in the first dielectric layer, the shielding layer facilitating obtaining a smaller width of the via.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] With the further development of semiconductor technology, transistor dimensions have shrunk to below a few nanometers. The size of FinFETs has already reached its limit, and limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing extremely challenging, even making the physical structure impossible to achieve. Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET.

[0003] As chip area shrinks further, the need for even smaller cell heights necessitates smaller spacing between nFETs and pFETs within a standard cell. However, for fin field-effect devices and gate-all-around devices, process limitations restrict the spacing between these n and p devices. Complementary FETs (CFETs) vertically stack nFETs and pFETs, significantly reducing chip area and achieving integration. CFETs represent a potential technological trend following fin field-effect devices and gate-all-around devices.

[0004] However, the existing fabrication techniques for complementary field-effect devices still need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a first substrate, the first substrate having a first device layer, the first device layer having a first gate; forming a first dielectric layer and an initial second device layer located on the first dielectric layer on the first substrate, the initial second device layer having a gate opening, the gate opening exposing a portion of the first dielectric layer; forming an initial via in the first dielectric layer, the initial via communicating with the bottom of the gate opening, the initial via having a first projection on the surface of the first dielectric layer; forming an initial via on the initial second device layer, the gate opening having a first projection; and forming an initial via in the first dielectric layer, the initial via communicating with the bottom of the gate opening, the initial via having a first projection on the surface of the first dielectric layer; and forming a first via on the initial second device layer, the gate opening having a first projection; and forming a first via in the first dielectric layer, the first via communicating with the bottom of the gate opening, the initial via having a first projection on the surface of the first dielectric layer; and forming a first via in the first dielectric layer, the first via communicating with the bottom of the gate opening, the first ... communicating with the bottom of A protective material layer is formed on the sidewall and bottom surface of the gate and the sidewall and bottom surface of the initial via. A patterned layer is formed covering the protective material layer, the patterned layer having a first opening located on the initial via. A shielding layer is formed on the sidewall of the first opening, the shielding layer having a second opening, the second opening having a second projection on the surface of the first dielectric layer, the second projection being within the range of the first projection. Using the shielding layer as a mask, the protective material layer and the first dielectric layer at the bottom of the initial via are etched to form a via exposing the top surface of the first gate within the first dielectric layer. A conductive layer is formed within the via.

[0007] Optionally, the patterning layer includes: a planarization layer located on the initial second device layer, within the gate opening and within the initial via, and a patterned photoresist layer located on the planarization layer.

[0008] Optionally, before etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask, the method further includes: using the patterned photoresist layer and the shielding layer as masks to etch away the planarization layer within the initial via.

[0009] Optionally, the protective layer material layer includes a second dielectric material layer and a third dielectric material layer located on the second dielectric material layer.

[0010] Optionally, the material of the second dielectric material layer is a high-K dielectric material; the material of the third dielectric material layer includes a nitrogen-containing material.

[0011] Optionally, the method of etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask includes: after removing the planarization layer in the initial via, etching the protective material layer using the shielding layer as a mask to remove the protective material layer in the initial via, forming a second dielectric layer with the second dielectric material layer, and forming a third dielectric layer with the third dielectric material layer; after forming the second dielectric layer and the third dielectric layer, etching the first dielectric at the bottom of the initial via to form the via.

[0012] Optionally, the process for removing the second dielectric material layer within the initial via includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes one of boron-containing gas, oxygen-containing gas, or chlorine-containing gas.

[0013] Optionally, the process for removing the third dielectric material layer within the initial via includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas.

[0014] Optionally, after forming the via and before forming the conductive layer, the method further includes removing the planarization layer and the third dielectric layer on the initial second device layer and within the gate opening.

[0015] Optionally, the process for removing the third dielectric layer includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas.

[0016] Optionally, the planarization layer includes a first photolithography layer and a second photolithography layer located on the first photolithography layer; the material of the first photolithography layer includes an organic material, the organic material including amorphous carbon; the material of the second photolithography layer includes silicon oxide.

[0017] Optionally, the formation process of the first photolithography layer includes a spin coating process; the formation process of the second photolithography layer includes a spin coating process.

[0018] Optionally, the method of forming the masking layer includes: forming a masking material layer on the surface of the patterned layer, as well as on the first opening sidewall and bottom; and etching back the masking material layer until the surface of the patterned layer is exposed.

[0019] Optionally, the thickness of the shielding material layer ranges from 0.5 nanometers to 5 nanometers.

[0020] Optionally, the etching process for the bottom of the initial via includes a dry etching process, which includes an atomic layer etching process; the process parameters for the atomic layer etching process include: the etching gas includes a fluorine-containing gas.

[0021] Optionally, the aspect ratio of the through hole ranges from 10:1 to 50:1.

[0022] Optionally, the method further includes: after forming the conductive layer, forming a second gate within the gate opening to form a second device with the initial second device.

[0023] Optionally, the first transistor device includes a fin field-effect transistor device or a gate-all-around device; the second transistor device includes a fin field-effect transistor device or a gate-all-around device.

[0024] Optionally, a barrier layer is further provided between the first dielectric layer and the first gate; the barrier layer is made of a dielectric material layer, and the dielectric material layer is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0025] Optionally, the first substrate has opposing first and second surfaces, the first surface exposing the top surface of the first gate; the method of forming the first dielectric layer and the initial second device layer includes: providing a second substrate, the second substrate having opposing third and fourth surfaces, the second substrate having a dummy gate device structure including a dummy gate, the third surface exposing the top surface of the dummy gate; forming a first bonding layer on the first surface of the first substrate; forming a second bonding layer on the third surface of the second substrate; bonding the first substrate and the second substrate together with the first bonding layer and the second bonding layer to form the first dielectric layer; after the bonding process, planarizing the second substrate from the fourth surface of the second substrate until the dummy gate is exposed; after the planarization process, removing the dummy gate to form a gate opening, and forming the initial second device layer with the dummy gate device structure.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the semiconductor structure formation method provided by the present invention, a protective material layer is formed on the initial second device layer, the sidewall and bottom surface of the gate opening, and the sidewall and bottom surface of the initial via. A patterned layer covering the protective material layer is formed, the patterned layer filling the gate opening and the initial via, and the patterned layer having a first opening located on the initial via. A shielding layer is formed on the sidewall of the first opening, and the shielding layer has a second opening. The second opening has a second projection on the surface of the first dielectric layer. Since the second projection is within the range of the first projection, when etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask, the protective material layer on the first dielectric layer is retained to form a protective layer. The shielding layer can reduce the etching damage to the protective layer during the etching process. The protective layer further protects the first dielectric layer on the sidewall of the initial via, which is beneficial for obtaining a via with a smaller width.

[0028] Furthermore, the protective layer material layer includes a second dielectric material layer and a third dielectric material layer located on the second dielectric material layer. The second dielectric material layer is used to form the second dielectric layer. The second dielectric layer is disposed on the surface of the first dielectric layer on the sidewall of the conductive layer. The shielding layer can reduce the lateral etching amount of the second dielectric layer, improve the quality of the second dielectric layer, and help reduce leakage current of the formed device and improve the performance of the device. In addition, the third dielectric material layer can protect the second dielectric material layer, reduce the damage to the second dielectric material layer during the etching process, and improve the performance of the formed second dielectric layer.

[0029] Furthermore, the process for removing the third dielectric layer includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas. The dry etching process not only has a high selectivity ratio for both the third and second dielectric layers, but the treatment of the second dielectric layer surface with the fluorine-containing gas can improve the performance of the formed second dielectric layer, thereby helping to reduce low-frequency noise in the formed device and thus improving device performance.

[0030] Furthermore, the etching process for the bottom of the initial via includes a dry etching process, which includes an atomic layer etching process. The atomic layer etching process helps to improve the flatness of the formed via surface, thereby further improving the performance of the formed conductive layer. Attached Figure Description

[0031] Figures 1 to 6 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0032] Figures 7 to 16 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation

[0033] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0034] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. A method for forming a semiconductor structure will now be explained and analyzed.

[0035] Figures 1 to 6 This is a cross-sectional schematic diagram of the semiconductor structure formation process.

[0036] Please refer to Figure 1A first substrate 101 and a second substrate 201 are provided, the second substrate 201 is located on the first substrate 101, and the first substrate 101 and the second substrate 201 are bonded by an oxide layer 200. The first substrate 101 has a first device channel layer 102 and a first gate 103 surrounding the first device channel 102, and the second substrate 201 has a second device channel layer 202 and a second dummy gate 203 surrounding the second device channel 202.

[0037] Please refer to Figure 2 The second dummy gate 203 is removed, and a gate recess 204 is formed in the second substrate 201, the gate recess 204 exposing the surface of the second device channel 202; a gate oxide layer (not shown in the figure) is formed on the gate recess and the surface of the second device channel 202; a high-K dielectric layer 206 and a protective material layer 207 located on the surface of the high-K dielectric layer 206 are formed on the surface of the gate oxide layer.

[0038] Please refer to Figure 3 After the protective material layer 207 is formed, a spin-coated carbon layer 208 is formed in the gate groove 204; a patterned layer 209 is formed on the surface of the spin-coated carbon layer 208, and the patterned layer exposes part of the spin-coated carbon layer 208 on the first gate 103.

[0039] Please refer to Figure 4 Using the patterned layer 209 as a mask, the spin-coated carbon layer 208, the protective material layer 207, the high-K dielectric layer 206, the gate oxide layer and the oxide layer 200 are etched until the surface of the first gate 103 is exposed, forming a via 210 in the oxide layer 200 and an opening 211 in the spin-coated carbon layer 208.

[0040] Please refer to Figure 5 An initial conductive layer 212 is formed within the through hole 210 and the opening 211.

[0041] Please refer to Figure 6 The initial conductive layer 212, the spin-coated carbon layer 208, and the spin-coated carbon layer 208 are etched back until the protective material layer 207 on the surface of the oxide layer 200 is exposed, and a conductive layer 213 is formed from the initial conductive layer 212; after the conductive layer 213 is formed, the spin-coated carbon layer 208 and the protective material layer 207 are removed to expose the gate groove 204; after the protective material layer 207 is removed, a second gate 214 is formed in the gate groove 204.

[0042] The above method is used to form complementary field-effect devices (CFDs), where the conductive layer 213 connects the first gate 103 of the lower device and the second gate 214 of the upper device. As device feature sizes continue to shrink, the conductive layer 213 is required to have a smaller feature size, thus requiring the via 210 to have a smaller opening width. However, due to the large depth-to-width ratio of the via 210, the etching time in the photolithography process is long. The shoulder A between the top of the sidewall of the via 210 and the top surface of the oxide layer 200 is easily etched laterally relative to the bottom of the via 210, thereby increasing the size of the via 210 along the oxide layer surface direction, making it difficult for the via 210 to meet the low feature size requirement. In summary, existing via 210 formation techniques are insufficient to meet the requirements of complementary field-effect devices.

[0043] To address the aforementioned problems, the present invention provides a semiconductor structure formation method in which a protective material layer is formed on the initial second device layer, the sidewall and bottom surface of the gate opening, and the sidewall and bottom surface of the initial via. After forming the protective material layer, a patterned layer is formed on the initial second device layer and within the gate opening. The patterned layer has a first opening located on the initial via. A shielding layer is formed on the sidewall of the first opening. The shielding layer has a second opening. The second opening has a second projection on the surface of the first dielectric layer. Since the second projection is within the range of the first projection, when etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask, the protective material layer on the first dielectric layer remains to form a protective layer. The shielding layer can reduce etching damage to the protective layer during the etching process. The protective layer further protects the first dielectric layer on the sidewall of the initial via, which is beneficial for obtaining a via with a smaller width.

[0044] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Figures 7 to 16 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0046] Please refer to Figure 7 and Figure 8 , Figure 7 This is a structural diagram. Figure 8 yes Figure 7A cross-sectional structural schematic diagram along the EE1 direction shows a first substrate 301 having a first device layer (not shown) within the first substrate 301, the first device layer having a first gate 302; a first dielectric layer 400 and an initial second device layer (not shown) located on the first dielectric layer 400 are formed on the first substrate 301, the initial second device layer having a gate opening 401 that exposes a portion of the first dielectric layer 400.

[0047] The first substrate 301 has a first side (not shown) and a second side (not shown) opposite each other, with the first side exposing the top surface of the first gate 302.

[0048] The method for forming the first dielectric layer 400 and the initial second device layer includes: providing a second substrate (not shown), the second substrate having opposing third surfaces (not shown) and fourth surfaces (not shown), the second substrate having a dummy gate device structure (not shown), the dummy gate device structure including a dummy gate (not shown), the third surface exposing the top surface of the dummy gate; forming a first bonding layer (not shown) on the first surface of the first substrate 301; forming a second bonding layer (not shown) on the third surface of the second substrate; bonding the first substrate 301 and the second substrate (not shown) together with the first bonding layer facing the second bonding layer to form the first dielectric layer 400; after the bonding process, planarizing the second substrate from the fourth surface of the second substrate until the dummy gate is exposed; after the planarization process, removing the dummy gate to form a gate opening 401, and forming the initial second device layer with the dummy gate device structure.

[0049] The gate opening 401 is used to form the gate.

[0050] The first transistor device includes a finned field-effect transistor (FET) or a gate-all-around (GAA) device. In this embodiment, the first transistor device is a finned field-effect transistor.

[0051] In this embodiment, the fin field-effect transistor device further includes a fin 303, and the gate 302 spans the fin 303 and is located on a portion of the sidewall and top surface of the fin 303.

[0052] The initial second device layer is used to form a second transistor device, which includes a finned field-effect transistor (FET) or a gate-all-around (GAA) device. In this embodiment, the second transistor device is a GAA device.

[0053] In this embodiment, the initial second device layer further includes a plurality of nanowires 402 stacked perpendicular to the surface of the first dielectric layer 400.

[0054] In this embodiment, a barrier layer 403 is further provided between the first dielectric layer 400 and the first gate 302; the barrier layer 403 is made of a dielectric material layer, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride. The barrier layer 403 is used to block ion diffusion within the first gate 302.

[0055] It should be noted that the sidewalls and top surfaces of the fin 303 and the sidewalls of the gate 302 have a first interlayer dielectric layer, and the sidewalls of the gate opening 401 and the partial surfaces of the plurality of nanowires 403 have a second interlayer dielectric layer. Figure 7 The first interlayer dielectric layer and the second interlayer dielectric layer are omitted.

[0056] Please refer to Figure 9 An initial via 404 is formed in the first dielectric layer 400. The initial via 404 communicates with the bottom of the gate opening 401. The initial via 404 has a first projection on the surface of the first dielectric layer 400. A protective material layer is formed on the initial second device layer, the sidewall and bottom surface of the gate opening 401, and the sidewall and bottom surface of the initial via 404.

[0057] The protective material layer is used to protect the sidewalls of the initial via 404 during the etching process, reduce the lateral etching of the sidewalls of the initial via 404, and thus reduce the size of the formed via.

[0058] The thickness of the protective material layer is less than 5 nanometers. The thickness refers to the dimension along the normal direction of the surface of the first dielectric layer 400.

[0059] In this embodiment, the protective layer material layer includes a second dielectric material layer 405 and a third dielectric material layer 406 located on the second dielectric material layer 405.

[0060] The formation process of the protective material layer includes atomic layer deposition (ALD). ALD is beneficial for improving the surface smoothness of the formed protective material layer.

[0061] In this embodiment, the method for forming the protective material layer includes: forming a second dielectric material layer 405 on the initial second device layer, the sidewall and bottom surface of the gate opening 401, and the sidewall and bottom surface of the initial through hole 404; and forming a third dielectric material layer 406 on the surface of the second dielectric material layer 405.

[0062] The material of the second dielectric material layer 405 is a high-K dielectric material; the material of the third dielectric material layer 406 includes nitrogen-containing materials.

[0063] The second dielectric material layer 405 is used to form the second dielectric layer.

[0064] The thickness of the second dielectric material layer 405 is less than 50 angstroms. The thickness refers to the dimension along the direction normal to the surface of the first dielectric layer 400.

[0065] Please refer to Figure 10 A patterned layer is formed covering the protective material layer, the patterned layer having a first opening 410 located on the initial through hole 404.

[0066] In this embodiment, the patterned layer fills the gate opening 401 and the initial via 404.

[0067] In this embodiment, the patterning layer includes: a planarization layer located on the initial second device layer, inside the gate opening 401 and inside the initial via, and a patterned photoresist layer 409 located on the planarization layer.

[0068] Specifically, the planarization layer fills the gate opening and the initial via.

[0069] The method for forming the patterned layer includes: forming a planarization layer on the protective material layer; and forming a patterned photoresist layer 409 on the planarization layer.

[0070] In this embodiment, the planarization layer includes a first photolithography layer 407 and a second photolithography layer 408 located on the first photolithography layer 407; the material of the first photolithography layer 407 includes an organic material, the organic material including amorphous carbon; the material of the second photolithography layer 408 includes silicon oxide.

[0071] Specifically, in this embodiment, the first photolithography layer 407 fills the initial via.

[0072] The formation process of the patterned photoresist layer 409 includes: forming a photoresist layer (not shown in the figure) on the planarization layer; and patterning the photoresist layer.

[0073] The formation process of the first photolithographic layer 407 includes a spin coating process; the formation process of the second photolithographic layer 408 also includes a spin coating process. The spin coating process is beneficial for forming a flat material film and for improving the accuracy of photolithography.

[0074] Please refer to Figure 11A shielding layer 411 is formed on the sidewall of the first opening 410. The shielding layer 411 has a second opening 500. The second opening 500 has a second projection on the surface of the first medium layer 400. The second projection is within the range of the first projection.

[0075] Along the surface direction of the first dielectric layer 400, the second opening 500 has a second width, and the initial via 404 has a first width. The difference between the second width and the first width is less than 10 nanometers. Specifically, the second width is greater than or equal to 5 nanometers. This range is chosen because the second width cannot be too small; otherwise, incomplete removal of the planarization layer within the initial via 404 may occur.

[0076] The shielding layer 411 has a second opening 500, which has a second projection on the surface of the first dielectric layer 400. Since the second projection is within the range of the first projection, when the shielding layer 411 is used as a mask to etch the protective material layer and the first dielectric layer at the bottom of the initial via, the protective material layer on the first dielectric layer 400 is retained to form a protective layer (not shown in the figure). The shielding layer 411 can reduce the etching damage to the protective layer during the etching process. The protective layer further protects the first dielectric layer 400 on the sidewall of the initial via 404, which is beneficial to obtaining a via with a smaller width.

[0077] Furthermore, the protective material layer includes a second dielectric material layer and a third dielectric material layer located on the second dielectric material layer. During subsequent etching, the third dielectric material layer can protect the second dielectric material layer and the sidewall of the initial via 404, reduce damage to the second dielectric material layer during etching, and improve the performance of the formed second dielectric layer. At the same time, the third dielectric material layer helps to reduce lateral etching at the top of the sidewall of the initial via 404, which is beneficial for forming a via with a smaller width.

[0078] The method of forming the shielding layer 411 includes: forming a shielding material layer (not shown in the figure) on the surface of the patterned layer, as well as the sidewall and bottom of the first opening 410; and etching the shielding material layer back until the surface of the patterned layer is exposed.

[0079] Specifically, the method for forming the shielding layer 411 includes: forming a shielding material layer (not shown in the figure) on the surface of the patterned photoresist layer 409, as well as on the sidewalls and bottom of the first opening 410; and etching back the shielding material layer until the surface of the patterned photoresist layer 409 is exposed.

[0080] The thickness of the shielding material layer ranges from 0.5 nanometers to 5 nanometers. The thickness refers to the dimension along the normal direction of the surface of the first dielectric layer 400.

[0081] The material of the shielding material layer includes silicon oxide.

[0082] The process for forming the shielding material layer includes atomic layer deposition (ALD); the process parameters for ALD include a process temperature below 350 degrees Celsius.

[0083] The patterned photoresist layer 409 comprises a hydroxyl polyimide-based photoresist material or a hexafluoroisopropyl-containing photoresist material. Because the photoresist material has high temperature resistance, the impact of the process temperature during the formation of the shielding material layer on the patterned photoresist layer 409 can be reduced.

[0084] Subsequently, after forming the shielding layer 411, the protective material layer and the first dielectric layer 400 at the bottom of the initial via 404 are etched using the shielding layer as a mask, forming a via exposing the top surface of the first gate 302 within the first dielectric layer 400. In this embodiment, before etching the protective material layer and the first dielectric layer 400 at the bottom of the initial via 404 using the shielding layer as a mask, please refer to... Figure 12 .

[0085] Please refer to Figure 12 Using the patterned photoresist layer 409 and the masking layer 411 as masks, the planarization layer inside the initial via 404 is etched away.

[0086] The process for removing the planarization layer within the initial via 404 includes a dry etching process.

[0087] In the process of removing the planarization layer within the initial via 404, an etching process with a large selectivity ratio between the planarization layer and the protective material layer can be selected to reduce damage to the protective material layer during etching, thereby protecting the sidewall of the initial via 404, reducing lateral etching of the sidewall 404 of the initial via 404, and facilitating the formation of a via with a smaller width.

[0088] In this embodiment, the method for etching the protective material layer and the first dielectric layer 400 at the bottom of the initial via 404 using the shielding layer 411 as a mask is described in the following reference. Figures 13 to 14 .

[0089] Please refer to Figure 13After removing the planarization layer within the initial via 404, the protective material layer is etched using the shielding layer 411 as a mask to remove the protective material layer within the initial via 404. The second dielectric material layer 405 is used to form the second dielectric layer 412, and the third dielectric material layer 406 is used to form the third dielectric layer 413.

[0090] When the protective material layer is etched using the shielding layer 411 as a mask, the shielding layer can reduce the lateral etching of the second dielectric layer 412 and the third dielectric layer 413, thereby reducing the lateral etching of the top sidewall of the initial via 404, which is beneficial to obtaining a via with a smaller width.

[0091] The process for removing the second dielectric material layer within the initial via 404 includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes one of boron-containing gas, oxygen-containing gas, or chlorine-containing gas.

[0092] In this embodiment, the process parameters of the dry etching process include: the etching gas includes BCl3 and N2.

[0093] The process for removing the third dielectric material layer within the initial via 404 includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas.

[0094] In this embodiment, the process parameters of the dry etching process include: the etching gas includes CF4, O2 and N2.

[0095] Please refer to Figure 14 After forming the second dielectric layer 412 and the third dielectric layer 413, the first dielectric layer 400 at the bottom of the initial via 404 is etched to form the via 414.

[0096] The etching process for the bottom of the initial via 404 includes a dry etching process, which includes atomic layer etching (ALT). In this embodiment, the dry etching process is an ALT. The ALT process helps to improve the flatness of the surface of the formed via 414, thereby further improving the performance of the formed conductive layer.

[0097] The process parameters for the atomic layer etching process include: the etching gas includes a fluorine-containing gas. In this embodiment, the process parameters for the atomic layer etching process include: the etching gas includes CF4, NH3, Cl2, and HBr.

[0098] During the etching of the first dielectric layer 400 at the bottom of the initial via 404, the surface of the first dielectric layer 400 is covered by the second dielectric layer 412 and the third dielectric layer 413. The etching time of the first dielectric layer 400 at the bottom of the initial via 404 is shorter than the time to form a via in the first dielectric layer by etching once, which reduces the lateral etching of the top sidewall of the initial via 404, thereby facilitating the obtaining of a via with a smaller width.

[0099] In this embodiment, after removing the protective material layer within the initial via 404 and before etching the bottom of the initial via 404, the method further includes removing the patterned photoresist layer 409. In another embodiment, the photoresist layer 409 may be removed simultaneously during the etching process of removing the protective material layer within the initial via 404.

[0100] In this embodiment, after removing the protective material layer inside the initial through hole 404 and before etching the bottom of the initial through hole 404, the shielding layer 411 is also removed.

[0101] In another embodiment, the shielding layer 411 may not be removed after the protective material layer inside the initial via 404 is removed and before the bottom of the initial via 404 is etched.

[0102] In another embodiment, the first dielectric layer at the bottom of the initial via is etched using the shielding layer as a mask. Since the second opening within the shielding layer is smaller than the width of the initial via, when the first dielectric layer at the bottom of the initial via is etched using the shielding layer as a mask, the shielding layer can reduce the lateral etching at the top of the sidewall of the initial via, thereby obtaining a via with a smaller width.

[0103] In this embodiment, the through hole 414 is also located within the barrier layer 403.

[0104] The aspect ratio of the through hole 414 ranges from 10:1 to 50:1.

[0105] Subsequently, a conductive layer is formed within the through-hole 414.

[0106] Please refer to Figure 15 After the via 414 is formed, and before the conductive layer is formed, the planarization layer and the third dielectric layer 413 on the initial second device layer and within the gate opening 401 are removed.

[0107] The process for removing the planarization layer on the initial second device layer and within the gate opening 401 includes one or both of dry etching and wet etching processes.

[0108] The process for removing the third dielectric layer 413 includes a dry etching process. The process parameters for this dry etching process include that the etching gas contains a fluorine-containing gas. This dry etching process not only has a high selectivity for both the third and second dielectric layers, but the treatment of the second dielectric layer 412 surface with the fluorine-containing gas can also improve the performance of the formed second dielectric layer 412, thereby helping to reduce low-frequency noise in the formed device and thus improving device performance.

[0109] Please refer to Figure 16 A conductive layer 415 is formed inside the through hole 412.

[0110] The conductive layer 415 is made of metal. In this embodiment, the conductive layer 415 is made of tungsten.

[0111] The second dielectric layer 412 is located on the surface of the first dielectric layer 400 on the sidewall of the conductive layer 415. Due to the reduction in the lateral etching amount of the second dielectric layer 412, the quality of the second dielectric layer 412 is improved, which helps to reduce leakage current of the formed device and improve the performance of the device.

[0112] In this embodiment, after forming the conductive layer 415, a second gate (not shown in the figure) is also formed in the gate opening 401 to form a second device with the initial second device.

[0113] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A first substrate is provided, wherein the first substrate has a first device layer and the first device layer has a first gate; A first dielectric layer and an initial second device layer are formed on the first substrate, wherein the initial second device layer has a gate opening that exposes a portion of the first dielectric layer. An initial via is formed in the first dielectric layer, the initial via is connected to the bottom of the gate opening, and the initial via has a first projection on the surface of the first dielectric layer. A protective material layer is formed on the initial second device layer, the gate opening sidewall and bottom surface, and the initial via sidewall and bottom surface; A patterned layer is formed covering the protective material layer, the patterned layer having a first opening located on the initial through-hole; A shielding layer is formed on the sidewall of the first opening, and a second opening is provided within the shielding layer. The second opening has a second projection on the surface of the first dielectric layer, and the second projection is within the range of the first projection. Using the shielding layer as a mask, the protective material layer and the first dielectric layer at the bottom of the initial via are etched to form a via that exposes the top surface of the first gate in the first dielectric layer; A conductive layer is formed inside the through hole.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The patterning layer includes: a planarization layer located on the initial second device layer, inside the gate opening and inside the initial via, and a patterned photoresist layer located on the planarization layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, Before etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask, the method further includes: using the patterned photoresist layer and the shielding layer as masks to etch away the planarization layer within the initial via.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The protective material layer includes a second dielectric material layer and a third dielectric material layer located on the second dielectric material layer.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The material of the second dielectric material layer is a high-K dielectric material; the material of the third dielectric material layer includes nitrogen-containing materials.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of etching the protective material layer and the first dielectric layer at the bottom of the initial via using the shielding layer as a mask includes: after removing the planarization layer in the initial via, etching the protective material layer using the shielding layer as a mask to remove the protective material layer in the initial via, forming a second dielectric layer with the second dielectric material layer, and forming a third dielectric layer with the third dielectric material layer; after forming the second dielectric layer and the third dielectric layer, etching the first dielectric layer at the bottom of the initial via to form the via.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the second dielectric material layer within the initial via includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes one of boron-containing gas, oxygen-containing gas, or chlorine-containing gas.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the third dielectric material layer within the initial via includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the via and before forming the conductive layer, the method further includes: removing the planarization layer and the third dielectric layer on the initial second device layer and within the gate opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for removing the third dielectric layer includes a dry etching process, wherein the process parameters of the dry etching process include: the etching gas includes a fluorine-containing gas.

11. The method for forming a semiconductor structure as described in claim 2, characterized in that, The planarization layer includes a first photolithography layer and a second photolithography layer located on the first photolithography layer; the material of the first photolithography layer includes an organic material, the organic material including amorphous carbon; the material of the second photolithography layer includes silicon oxide.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The formation process of the first photolithography layer includes a spin coating process; the formation process of the second photolithography layer includes a spin coating process.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the shielding layer includes: forming a shielding material layer on the surface of the patterned layer, as well as on the first opening sidewall and bottom; and etching back the shielding material layer until the surface of the patterned layer is exposed.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The thickness of the shielding material layer ranges from 0.5 nanometers to 5 nanometers.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for the bottom of the initial via includes a dry etching process, which includes an atomic layer etching process; the process parameters for the atomic layer etching process include: the etching gas includes a fluorine-containing gas.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The aspect ratio of the through hole ranges from 10:1 to 50:

1.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method further includes: after forming the conductive layer, forming a second gate in the gate opening, and forming a second device with the initial second device.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The first device layer is used to form a first transistor device, which includes a fin field-effect transistor device or a gate-all-around device; the initial second device layer is used to form a second transistor device, which includes a fin field-effect transistor device or a gate-all-around device.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, A barrier layer is further provided between the first dielectric layer and the first gate; the barrier layer is made of a dielectric material layer, which is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first substrate has opposing first and second surfaces, the first surface of which exposes the top surface of the first gate; The method for forming the first dielectric layer and the initial second device layer includes: providing a second substrate having opposing third and fourth surfaces, the second substrate having a dummy gate device structure including a dummy gate, the third surface exposing the top surface of the dummy gate; forming a first bonding layer on the first surface of the first substrate; forming a second bonding layer on the third surface of the second substrate; bonding the first substrate and the second substrate together by aligning the first bonding layer with the second bonding layer, thereby forming the first dielectric layer; after the bonding process, planarizing the second substrate from the fourth surface of the second substrate until the dummy gate is exposed; after the planarization process, removing the dummy gate to form a gate opening, and forming the initial second device layer with the dummy gate device structure.

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