Method for manufacturing a semiconductor integrated circuit

Abstract

The application discloses a manufacturing method of semiconductor integrated circuit, comprising the following steps: growing a hard mask medium layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer; forming a first groove and a second groove on the semiconductor substrate by using a photoetching and etching process with the hard mask medium layer as a barrier layer; removing the hard mask medium layer, growing a second silicon oxide, silicon nitride and a third silicon oxide; removing the third silicon oxide on the upper surface of the silicon nitride by using a chemical mechanical polishing process; removing the third silicon oxide in the area outside the first groove by using a photoetching and etching process with photoresist as a barrier layer, retaining the third silicon oxide at the bottom and sidewall of the first groove, and then removing the photoresist; the manufacturing method of semiconductor integrated circuit disclosed by the application has the advantages of completely eliminating the high step problem existing in the traditional manufacturing method and the like.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and more particularly to a method for manufacturing semiconductor integrated circuits. Background Technology

[0002] With the technological development of semiconductor integrated circuits, people have higher requirements for the performance of semiconductor devices. However, electrostatic discharge occurs in various stages of semiconductor integrated circuit packaging, transportation, and use, causing devices to fail due to electrostatic breakdown. Therefore, it is very important for semiconductor devices to have built-in electrostatic protection functions.

[0003] For trench semiconductor devices, such as trench MOSFETs, SGTs, and IGBTs, a typical manufacturing method with built-in ESD protection is to fabricate back-to-back diodes within the trench semiconductor device. Taking a trench MOSFET as an example, a relatively thick dielectric layer is typically fabricated outside the MOSFET's cell region, and then a polysilicon diode is fabricated on top of the dielectric layer. This method is characterized by a relatively simple process structure, but its disadvantage is the significant height difference between the cell region and the polysilicon diode region, i.e., a high step, which increases the difficulty of planarization and contact hole fabrication, and reduces the device's integration density.

[0004] Because of the above problems, a new manufacturing method has emerged: fabricating polycrystalline silicon diodes in trenches, with the top of the diode essentially flush with the silicon plane. This solves the height difference problem and significantly improves device integration. However, this method also faces many technological challenges, the main one being the isolation between the polycrystalline silicon diode and the cell region. Various approaches have been proposed to address these issues, but some shortcomings remain in practical application. Taking the already granted invention patent 201310347156.2 as an example, at least the following problems exist:

[0005] (1) The patent describes "depositing silicon dioxide in the trench and etching it back to form a thick gate oxide at the bottom of the trench, which serves as an insulating layer between the subsequently formed electrostatic discharge protection circuit and the trench-type power device, allowing the electrostatic discharge protection circuit to be placed in the trench, wherein the thickness of the thick gate oxide is 3000-4000 angstroms", which corresponds to the schematic diagram of invention patent 201310347156.2. Figure 5 Step B is not feasible in practical processes because the area of ​​the electrostatic discharge protection circuit usually exceeds 100*100 micrometers, that is, the size of the trench where the electrostatic discharge protection circuit is located is greater than 100*100 micrometers. After the silicon dioxide is deposited, the thickness of the silicon dioxide in the area outside the trench and the area at the bottom of the trench is the same. According to the above steps, it is not possible to selectively remove all the silicon dioxide outside the trench while retaining 3000-4000 angstroms of silicon dioxide in the trench.

[0006] (2) The "deposition of undoped polysilicon, first polysilicon implantation, coating of photoresist in the area to be formed of the electrostatic discharge protection circuit, second polysilicon implantation, and etch-back to remove the polysilicon above the trench, forming the gate polysilicon and the electrostatic discharge protection circuit polysilicon respectively" described in the patent corresponds to the schematic diagram of invention patent 201310347156.2. Figure 5 Steps C to 3F present structural problems in practical applications because the boron ions implanted in the second polysilicon implantation are only distributed on the surface of the polysilicon. During the etching-back step to remove the polysilicon above the trench, all the polysilicon above the trench in the area not covered by photoresist is etched away (see illustration in patent 201310347156.2). Figure 5 F), that is, the polysilicon surface layer doped with boron ions is etched away, so the doping purpose of the gate polysilicon cannot be achieved. In other words, the gate polysilicon remaining in the trench is not actually doped, and the MOSFET cannot work properly.

[0007] (3) After the process step of "etching back to remove the polysilicon above the trench to form the gate polysilicon and the electrostatic discharge protection circuit polysilicon" described in the patent, the corresponding invention patent 201310347156.2 is shown in the diagram. Figure 5 F. In the electrostatic protection circuit, the polysilicon forms a very high step in the trench, that is, there is a large height difference between the polysilicon surface in the trench and the surface of the insulating layer. In other words, this manufacturing method does not fundamentally solve the problem of height difference, but only transfers the step from outside the trench to inside the trench. It still poses great difficulties for subsequent platformization processes, and there is still a risk of metal residue at the step position.

[0008] In conclusion, invention patent 201310347156.2 is completely meaningless for practical production. Similarly, other published technical documents and patent information also have some problems and have not fundamentally solved the high-step problem in the manufacturing method of trench semiconductor devices with built-in electrostatic protection.

[0009] This case proposes a new manufacturing method to address the above problems. Summary of the Invention

[0010] This invention provides a method for manufacturing semiconductor integrated circuits, which has the advantages of completely eliminating the high step problem existing in traditional manufacturing methods and solving the high step problem existing in the original trench semiconductor device manufacturing method.

[0011] The method for manufacturing a semiconductor integrated circuit according to the embodiments of this application includes the following steps:

[0012] A hard mask dielectric layer is grown on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer;

[0013] Using a hard mask dielectric layer as a barrier layer, a first trench and a second trench are formed on a semiconductor substrate using photolithography and etching processes.

[0014] Remove the hard mask dielectric layer and grow a second silicon oxide, silicon nitride, and a third silicon oxide;

[0015] A chemical mechanical polishing process is used to remove the third silicon oxide that protrudes above the upper surface of the silicon nitride;

[0016] The photolithography and etching process is used, with photoresist as a barrier layer, to remove the third silicon oxide in the area outside the first trench, while retaining the third silicon oxide at the bottom and sidewalls of the first trench, and then the photoresist is removed.

[0017] The silicon nitride outside the first trench is removed by etching process, the second silicon oxide outside the first trench is removed, and the fourth silicon oxide, i.e. the gate oxide layer, is grown by thermal oxidation process.

[0018] Polysilicon is deposited, and the polysilicon is first doped by ion implantation to form first-doped polysilicon.

[0019] The process involves photolithography and ion implantation, with photoresist as a barrier layer, to perform a second ion implantation doping on a portion of the polysilicon to form second-doped polysilicon.

[0020] Remove the photoresist and anneal at high temperature to allow the dopants from the first and second ion implantation to diffuse towards the bottom of the polysilicon, thus permeating the polysilicon.

[0021] A chemical mechanical polishing process is used to remove the first doped polysilicon and the second doped polysilicon that protrude above the upper surface of the fourth silicon oxide, while retaining the polysilicon in the first trench (first doped polysilicon) and the polysilicon in the second trench (second doped polysilicon).

[0022] Ion implantation followed by annealing forms a bulk region;

[0023] The source region is formed by photolithography, ion implantation, and annealing, and the third doped polysilicon is formed simultaneously in a designated area of ​​the first doped polysilicon.

[0024] Preferably, the depth of the first trench and the second trench is 0.8 to 1.6 micrometers, the width of the first trench is 100 to 400 micrometers, and the width of the second trench is 0.1 to 0.5 micrometers.

[0025] Preferably, the thicknesses of the second silicon oxide and the silicon nitride are 200–800 angstroms, and the thickness of the third silicon oxide is 1200–6000 angstroms, wherein the thickness of the third silicon oxide is much greater than the thickness of the second silicon oxide.

[0026] Preferably, the etching process is used to remove silicon nitride outside the first trench. The etching process is selective, and the silicon nitride at the bottom and sidewalls of the first trench will not be etched due to the obstruction of the third silicon oxide, while the silicon nitride in the areas not blocked by the third silicon oxide will be completely etched away.

[0027] Preferably, the etching process is used to remove the second silicon oxide in the area outside the first trench. The etching process is selective, and the second silicon oxide at the bottom and sidewalls of the first trench will not be etched due to the blockage of silicon nitride, while the second silicon oxide in the area not blocked by silicon nitride will be completely etched away.

[0028] Preferably, the process employs thermal oxidation to grow a fourth silicon oxide, the thickness of which is greater than or equal to the thickness of the second silicon oxide. In the etching process, due to the isotropic nature of the etching process, a portion of the second silicon oxide at the top of the sidewall of the first trench is easily etched away, forming a small cavity. The width of the cavity is equal to the thickness of the second silicon oxide. Since the process thickness of the fourth silicon oxide is greater than or equal to the thickness of the second silicon oxide, it can be ensured that this cavity is repaired in this thermal oxidation step.

[0029] Preferably, the first and second ion implantation doping of the polycrystalline silicon are of opposite types, and the dosage of the second ion implantation doping is greater, specifically:

[0030] The first ion implantation of polycrystalline silicon is boron doping, with a dose of 1E14 to 5E14 ions / cm. 2 The second ion implantation of polycrystalline silicon was phosphorus doped at a dose of 2E15–2E16 ions / cm². 2 The resulting first-doped polysilicon is P-type, and the second-doped polysilicon is N-type; or,

[0031] The first ion implantation of polycrystalline silicon is phosphorus doping, with a dose of 1E14 to 5E14 ions / cm. 2 The second ion implantation of polycrystalline silicon was boron doped at a dose of 2E15–2E16 ions / cm². 2 The resulting first doped polysilicon is N-type, and the second doped polysilicon is P-type.

[0032] Preferably, after removing the first and second doped polycrystalline silicon that protrude above the upper surface of the fourth silicon oxide using a chemical mechanical polishing process, a fifth silicon oxide is grown on the polycrystalline silicon surface using a thermal oxidation process.

[0033] Preferably, the thickness of the fifth silicon oxide is greater than the thickness of the silicon nitride.

[0034] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0035] 1. The polycrystalline silicon diode formed by the present invention is completely located in the trench, and the top of the polycrystalline silicon diode is close to the same horizontal plane as the upper surface of the silicon substrate in the cell region. This completely eliminates the high step problem existing in the traditional manufacturing method, thereby reducing the difficulty of process steps such as planarization, reducing process risks, and improving the integration of the chip.

[0036] 2. The isolation layer fabricated between the polycrystalline silicon diode and the cell region in this invention, namely the second silicon oxide, silicon nitride and third silicon oxide (the total thickness of the three is greater than 2000 angstroms) on the sidewall and bottom of the first trench, has uniform thickness and no voids, and is a very safe and reliable isolation layer.

[0037] 3. The manufacturing method disclosed in this invention is based on practice and is formed after repeated research and demonstration of all steps. It is not a simple combination of processes based on imagination. Compared with the manufacturing methods of forming polycrystalline silicon diodes in trenches disclosed in existing literature and patents, this invention has more practical significance and feasibility. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic flowchart of the semiconductor integrated circuit manufacturing method of the present invention;

[0040] Figure 2 This is a schematic flowchart of the semiconductor integrated circuit manufacturing method of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of step S1 of the present invention;

[0042] Figure 4 This is a schematic diagram of the structure of step S2 of the present invention;

[0043] Figure 5 This is a schematic diagram of the structure of step S3 of the present invention;

[0044] Figure 6 This is a schematic diagram of the structure of step S4 of the present invention;

[0045] Figures 7-8 This is a schematic diagram of the structure of step S5 of the present invention;

[0046] Figure 9 This is a schematic diagram of the structure of step S6 of the present invention;

[0047] Figure 10 This is a schematic diagram of the structure of step S7 of the present invention;

[0048] Figure 11 This is a schematic diagram of the structure of step S8 of the present invention;

[0049] Figures 12-13 This is a schematic diagram of the structure of step S9 of the present invention;

[0050] Figure 14 This is a schematic diagram of the structure of step S10 of the present invention;

[0051] Figure 15 This is a schematic diagram of the structure of step S11 of the present invention;

[0052] Figure 16 This is a schematic diagram of the structure of step S12 of the present invention;

[0053] Figure 17 This is a schematic diagram of the structure of the present invention;

[0054] Figure 18 This is a schematic diagram of the structure of step S13 of the present invention;

[0055] Figure 19 This is a schematic diagram of the structure of step S14 of the present invention;

[0056] Figure 20 This is a schematic diagram of the MOSFET integrated circuit structure of the present invention;

[0057] Figure 21 This is a schematic diagram of the MOSFET integrated circuit structure of the present invention. Detailed Implementation

[0058] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0060] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0061] Please see Figures 1 to 2 The present invention provides a method 100 for manufacturing a semiconductor integrated circuit, comprising the following steps:

[0062] Step S1: Grow a hard mask dielectric layer on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate 1 and a lightly doped epitaxial layer 2 (see...) Figure 3 );

[0063] Step S2: Using a hard mask dielectric layer as a barrier layer, the first trench 4 and the second trench 5 are formed on the semiconductor substrate using photolithography and etching processes (see...). Figure 4 );

[0064] Step S3: Remove the hard mask dielectric layer; grow the second silicon oxide 6, silicon nitride 7, and third silicon oxide 8 (see...) Figure 5 );

[0065] Step S4: Using a chemical mechanical polishing process, remove the third silicon oxide 8 that protrudes above the upper surface of the silicon nitride 7 (see...). Figure 6 );

[0066] Step S5: Use photolithography (see...) Figure 7 The etching process uses photoresist 9 as a barrier layer to remove the third silicon oxide 8 outside the first trench 4, retaining the third silicon oxide 8 at the bottom and sidewalls of the first trench 4, and then removing the photoresist 9 (see...). Figure 8 );

[0067] Step S6: Use an etching process to remove silicon nitride 7 from the area outside the first trench 4 (see...) Figure 9 );

[0068] Step S7: Use an etching process to remove the second silicon dioxide 6 in the area outside the first trench 4 (see...) Figure 10 );

[0069] Step S8: Using a thermal oxidation process, grow silicon 4 oxide 10, i.e., the gate oxide layer (see...). Figure 11 );

[0070] Step S9: Deposit polycrystalline silicon 11 (see...) Figure 12 The polysilicon 11 was first ion implanted and doped to form the first doped polysilicon 11.1 (see...). Figure 13 );

[0071] Step S10: Using photolithography and ion implantation, with photoresist 12 as a barrier layer, a second ion implantation doping is performed on a portion of the polysilicon 11 to form second-doped polysilicon 11.2 (see [reference]). Figure 14 );

[0072] Step S11: Remove photoresist 12, perform high-temperature annealing, allowing the dopants from the first and second ion implantation doping to diffuse towards the bottom of the polysilicon, thus permeating the polysilicon (see...). Figure 15 );

[0073] In step S11, before high-temperature annealing, the first doped polycrystalline silicon 11.1 and the second doped polycrystalline silicon 11.2 are only distributed on the surface of the polycrystalline silicon. After high-temperature annealing, the dopants are distributed throughout the entire depth region from the surface of the polycrystalline silicon to the bottom.

[0074] Step S12: Using a chemical mechanical polishing process, remove the first doped polysilicon 11.1 and the second doped polysilicon 11.2 that protrude above the upper surface of the fourth silicon oxide 10, retaining the polysilicon in the first trench 4 (first doped polysilicon 11.1) and retaining the polysilicon in the second trench 5 (second doped polysilicon 11.2). (See reference) Figure 16 ).

[0075] In step S12, the first doped polysilicon 11.1 is the subsequent polysilicon diode region, i.e., the electrostatic protection circuit region, and the second doped polysilicon 11.2 is the polysilicon gate of the MOSFET.

[0076] Step S13: Ion implantation followed by annealing to form region 14 (see) Figure 18 ).

[0077] Step S14: Using photolithography, ion implantation, and annealing processes, source region 15 is formed, and simultaneously, third-doped polysilicon 11.3 is formed in a designated region of the first-doped polysilicon 11.1 (see...). Figure 19 ).

[0078] The subsequent process steps are standard and will not be described in detail here.

[0079] It is understood that in this embodiment, the hard mask dielectric layer is first silicon oxide 3 with a thickness of 2000-5000 angstroms;

[0080] Please see Figure 4It can be understood that in this embodiment, the depth of the first trench 4 and the second trench 5 is 0.8 to 1.6 micrometers, the width W1 of the first trench is 100 to 400 micrometers, and the width of the second trench W2 is 0.1 to 0.5 micrometers. (The area of ​​the first trench is the area where polysilicon diodes are pre-arranged, and the area where the second trench is located is the pre-arranged MOSFET cell region. The cell region contains a plurality of second trenches. The schematic diagram only shows two second trenches.)

[0081] It is understood that in this embodiment, the thicknesses of the second silicon oxide 6 and the silicon nitride 7 are 200-800 angstroms, and the thickness of the third silicon oxide 8 is 1200-6000 angstroms (i.e. 0.12-0.6 micrometers), wherein the thickness of the third silicon oxide 8 is much greater than the thickness of the second silicon oxide 6 (the thickness ratio is 5:1 or more).

[0082] It is understood that in this embodiment, the process of growing silicon nitride 7 and growing third silicon oxide 8 is chemical vapor deposition. The second trench 5 is relatively small in width and is filled with third silicon oxide 8. The first trench 4 is relatively large in width and is uniformly covered by silicon nitride 7 and third silicon oxide 8 at the bottom and sidewalls of the second trench.

[0083] Preferably, after growing the silicon nitride 7 and silicon oxide 8 using chemical vapor deposition, the silicon nitride and silicon oxide are densified by high-temperature annealing to improve their pressure resistance, reduce defects, and lower their corrosion rate. The high-temperature annealing temperature is 950–1100 degrees Celsius.

[0084] It is understood that in this embodiment, the chemical mechanical polishing is performed from top to bottom, ultimately stopping at the upper surface of the silicon nitride 7. Because chemical mechanical polishing is selective, therefore... Figure 6 As shown, the third silica 8 at the bottom and sidewalls of the first trench 4 is preserved.

[0085] It is understood that in this embodiment, the etching process is used to remove silicon nitride 7 outside the first trench 4. The etching process is selective. The silicon nitride at the bottom and sidewalls of the first trench 4 will not be etched because of the barrier of the third silicon oxide 8. The silicon nitride in the area not blocked by the third silicon oxide 8 is completely etched away (therefore, this etching process does not require photoresist as a barrier layer, that is, it does not require an additional photolithography process, thus saving costs).

[0086] It is understood that in this embodiment, the etching process is used to remove the second silicon oxide 6 outside the first trench 4. The etching process is selective. The second silicon oxide 6 at the bottom and sidewalls of the first trench 4 will not be etched because of the blockage of silicon nitride 7. The second silicon oxide 6 in the area not blocked by silicon nitride 7 will be completely etched away. (Therefore, this etching process does not require photoresist as a blocking layer, that is, it does not require an additional photolithography process, thus saving costs.)

[0087] In this etching process, a portion of the third silicon oxide 8 at the bottom and sidewalls of the first trench 4 will be etched away. However, since the thickness of the third silicon oxide 8 is much greater than the thickness of the second silicon oxide 6 (the thickness ratio is 5:1 or more), as long as the etching process time is properly controlled (by adding about 15% over-etching on the basis of ensuring that the second silicon oxide 6 in the area outside the first trench 4 is completely etched away), most of the third silicon oxide 8 at the bottom and sidewalls of the first trench 4 can be retained. Typically, it is required that after this process, the total thickness of the second silicon oxide 6, silicon nitride 7, and third silicon oxide 8 at the bottom (and sidewalls) of the first trench 4 is greater than 2000 angstroms in order to safely and effectively isolate the polysilicon diode from the cell region.

[0088] It is understood that in this embodiment, the thermal oxidation process is used to grow the fourth silicon oxide 10, i.e., the gate oxide layer: the thickness of the fourth silicon oxide 10 is greater than or equal to the thickness of the second silicon oxide 6. In step S7 (corresponding to...) Figure 10 Because of the isotropic nature of the etching process, a portion of the second silicon oxide 6 at the top of the sidewall of the first trench 4 is easily etched away, forming a small cavity. The width of the cavity is equal to the thickness of the second silicon oxide 6. If the process thickness of the fourth silicon oxide 10 is greater than or equal to the thickness of the second silicon oxide 6, it can be ensured that the cavity is repaired in this thermal oxidation process (i.e., the oxide layer grown on the sidewall of the trench at the cavity location can fill the cavity).

[0089] It is understood that in this embodiment, the first and second ion implantation doping of polycrystalline silicon are of opposite types, and the dosage of the second ion implantation doping is greater, specifically:

[0090] The first ion implantation of polycrystalline silicon is boron doping, with a dose of 1E14 to 5E14 ions / cm. 2 The second ion implantation of polycrystalline silicon was phosphorus doped at a dose of 2E15–2E16 ions / cm². 2 Thus, the first doped polysilicon 11.1 formed is P-type, and the second doped polysilicon 11.2 is N-type; or,

[0091] The first ion implantation of polycrystalline silicon is phosphorus doping, with a dose of 1E14 to 5E14 ions / cm.2 The second ion implantation of polycrystalline silicon was boron doped at a dose of 2E15–2E16 ions / cm². 2 Thus, the first doped polysilicon 11.1 formed is N-type, and the second doped polysilicon 11.2 is P-type.

[0092] The diagram is shown after step S11. Figure 15 As shown, the region of the first doped polysilicon 11.1 completely covers and is larger than the region where the first trench 4 is located, and the region of the second doped polysilicon 11.2 completely covers and is larger than the region where the second trench 5 is located.

[0093] Preferably, after removing the first doped polysilicon 11.1 and the second doped polysilicon 11.2 that protrude above the upper surface of the fourth silicon oxide 10 using a chemical mechanical polishing process, a fifth silicon oxide 13 is grown on the polysilicon surface using a thermal oxidation process, as illustrated in the diagram. Figure 17 .

[0094] On the one hand, during the growth of silicon oxide using the thermal oxidation process, silicon atoms on the surface of polycrystalline silicon are oxidized to form silicon oxide. During this process, the interface between polycrystalline silicon and silicon oxide at the top (mainly focusing on the top of the first doped polycrystalline silicon 11.1) gradually moves downward, so that this interface is preferably slightly lower than the silicon plane (for example, 300 to 1500 angstroms lower).

[0095] On the other hand, in step S6 (corresponding to) Figure 9 Because of the isotropic nature of the etching process, a portion of the silicon nitride 7 at the top of the sidewall of the first trench 4 is easily etched away, forming a small cavity. The width of the cavity is equal to the thickness of the silicon nitride. This cavity is formed after step S8 (corresponding to...) Figure 11 It still exists after ) in step S9 (corresponding to Figure 12 This void will be filled with deposited polysilicon. Because the void is located below the upper surface of the fourth silicon oxide 10, chemical mechanical polishing (CMP) in step S12 will have difficulty removing the polysilicon from this void, resulting in polysilicon residue at the void location. Figure 16 As shown; in this thermal oxidation process, the polycrystalline silicon remaining in the voids is simultaneously oxidized to form silicon oxide, as shown. Figure 17 As shown.

[0096] Preferably, the thickness of the fifth silicon oxide 13 is greater than the thickness of the silicon nitride 7. In this way, the above-mentioned voids are completely filled by the silicon oxide generated in this step.

[0097] From the results of the above two aspects, it can be seen that the first doped polysilicon 11.1 that ultimately remains in the first trench 4 effectively isolates itself from the silicon region in both the bottom and side directions, especially at the top of the sidewall of the first trench 4, where double protection is provided:

[0098] 1. The cavities at the top of the sidewall of the first trench 4 (and its vicinity) are completely filled with silicon oxide, and there is no conductor (such as polysilicon residue), so there is no leakage path.

[0099] 2. The top plane of the first doped polysilicon 11.1 in the first trench 4 has been moved down below the silicon plane, avoiding the topmost region where voids are most likely to occur in the horizontal direction, thus reducing the risk of leakage from the side to the cell region.

[0100] It is understood that in this embodiment, the photolithography, ion implantation, and annealing form the source region. The dopant in this ion implantation step is of the same type as the dopant in the second ion implantation of polycrystalline silicon, that is, the opposite type to the dopant in the first ion implantation of polycrystalline silicon, and the dose of ion implantation in this step is greater than the dose of ion implantation in the first ion implantation of polycrystalline silicon. Specifically:

[0101] The first ion implantation of polycrystalline silicon is boron doping, with a dose of 1E14 to 5E14 ions / cm. 2 The source region is doped with phosphorus or arsenic by ion implantation at a dose of 2E15–8E15 ions / cm. 2 The resulting third-doped polysilicon 11.3 is N-type;

[0102] Alternatively, the first ion implantation of polycrystalline silicon may be phosphorus-doped at a dose of 1E14–5E14 ions / cm. 2 The source region is doped with boron ions at a dose of 2E15–8E15 ions / cm. 2 The resulting third-doped polysilicon 11.3 is P-type.

[0103] Furthermore, it has the following important characteristics:

[0104] The third doped polycrystalline silicon 11.3 is formed in a predetermined region, which consists of several regions spaced apart. Figure 19 The example shown consists of three regions arranged in a centrally symmetrical, spaced-out pattern (corresponding to a planar diagram). Figure 21 The regions between the spaced-out third-doped polysilicon layers 11.3 are the first-doped polysilicon layers 11.1. The doping types of these two layers are opposite, forming an alternating structure of NPNPN... or PNPNP..., thus creating a back-to-back polysilicon diode (a polysilicon diode consisting of a forward PN junction and a reverse PN junction connected in series). In subsequent process steps, first contact holes 16.1 and second contact holes 16.2 are fabricated to bring out the two ends of the back-to-back polysilicon diodes. Figure 20 and Figure 21 As shown, the electrodes are connected to the gate and source of the MOSFET respectively, thus forming a MOSFET integrated circuit with built-in electrostatic protection.

[0105] The technical solutions provided in this application embodiment may include the following beneficial effects:

[0106] 1. The polycrystalline silicon diode formed by the present invention is completely located in the trench, and the top of the polycrystalline silicon diode is close to the same horizontal plane as the upper surface of the silicon substrate in the cell region. This completely eliminates the high step problem existing in the traditional manufacturing method, thereby reducing the difficulty of process steps such as planarization, reducing process risks, and improving the integration of the chip.

[0107] 2. The isolation layer fabricated between the polycrystalline silicon diode and the cell region in this invention, namely the second silicon oxide, silicon nitride and third silicon oxide (the total thickness of the three is greater than 2000 angstroms) on the sidewall and bottom of the first trench, has uniform thickness and no voids, and is a very safe and reliable isolation layer.

[0108] 3. The manufacturing method disclosed in this invention is based on practice and is formed after repeated research and demonstration of all steps. It is not a simple combination of processes based on imagination. Compared with the manufacturing methods of forming polycrystalline silicon diodes in trenches disclosed in existing literature and patents, this invention has more practical significance and feasibility.

[0109] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor integrated circuit, characterized in that, Includes the following steps: A hard mask dielectric layer is grown on a semiconductor substrate, the semiconductor substrate comprising a heavily doped semiconductor substrate and a lightly doped epitaxial layer; Using a hard mask dielectric layer as a barrier layer, a first trench and a second trench are formed on a semiconductor substrate using photolithography and etching processes. Remove the hard mask dielectric layer and grow a second silicon oxide, silicon nitride, and a third silicon oxide; A chemical mechanical polishing process is used to remove the third silicon oxide that protrudes above the upper surface of the silicon nitride; The photolithography and etching process is used, with photoresist as a barrier layer, to remove the third silicon oxide in the area outside the first trench, while retaining the third silicon oxide at the bottom and sidewalls of the first trench, and then the photoresist is removed. The silicon nitride outside the first trench is removed by etching process, the second silicon oxide outside the first trench is removed, and the fourth silicon oxide, i.e. the gate oxide layer, is grown by thermal oxidation process. Polysilicon is deposited, and the polysilicon is first doped by ion implantation to form first-doped polysilicon. The process involves photolithography and ion implantation, with photoresist as a barrier layer, to perform a second ion implantation doping on a portion of the polysilicon to form second-doped polysilicon. Remove the photoresist and anneal at high temperature to allow the dopants from the first and second ion implantation to diffuse towards the bottom of the polysilicon, thus permeating the polysilicon. A chemical mechanical polishing process is used to remove the first doped polysilicon and the second doped polysilicon that protrude above the upper surface of the fourth silicon oxide, while retaining the polysilicon in the first trench (first doped polysilicon) and the polysilicon in the second trench (second doped polysilicon). Ion implantation followed by annealing forms a bulk region; The source region is formed by using photolithography, ion implantation, and annealing processes, and the third doped polysilicon is simultaneously formed in a designated area of ​​the first doped polysilicon.

2. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The depth of the first trench and the second trench is 0.8 to 1.6 micrometers, the width W1 of the first trench is 100 to 400 micrometers, and the width W2 of the second trench is 0.1 to 0.5 micrometers.

3. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The thickness of the second silicon oxide is 200–800 angstroms, the thickness of the silicon nitride is 200–800 angstroms, and the thickness of the third silicon oxide is 1200–6000 angstroms, wherein the thickness of the third silicon oxide is much greater than the thickness of the second silicon oxide.

4. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The etching process is used to remove silicon nitride outside the first trench. The etching process is selective. The silicon nitride at the bottom and sidewalls of the first trench will not be etched because it is blocked by the third silicon oxide. The silicon nitride in the area not blocked by the third silicon oxide will be completely etched away.

5. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The etching process is used to remove the second silicon oxide in the area outside the first trench. The etching process is selective. The second silicon oxide at the bottom and sidewalls of the first trench will not be etched because of the barrier of silicon nitride. The second silicon oxide in the area not blocked by silicon nitride will be completely etched away.

6. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The process employs thermal oxidation to grow a fourth silicon oxide, the thickness of which is greater than or equal to the thickness of the second silicon oxide. During the etching process, due to the isotropic nature of the etching process, a portion of the second silicon oxide at the top of the sidewall of the first trench is easily etched away, forming a small cavity. The width of the cavity is equal to the thickness of the second silicon oxide. Since the process thickness of the fourth silicon oxide is greater than or equal to the thickness of the second silicon oxide, it can be ensured that this cavity is repaired in this thermal oxidation step.

7. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, The first and second ion implantation doping of polycrystalline silicon are of opposite types, and the dosage of the second ion implantation doping is greater, specifically: The first ion implantation doping of polycrystalline silicon is boron, with a dose of 1E14–5E14 ions / cm². The second ion implantation doping of polycrystalline silicon is phosphorus, with a dose of 2E15–2E16 ions / cm². The resulting first-doped polycrystalline silicon is P-type, and the second-doped polycrystalline silicon is N-type; or... The first ion implantation doping of polycrystalline silicon is phosphorus, with a dose of 1E14 to 5E14 ions / CM2. The second ion implantation doping of polycrystalline silicon is boron, with a dose of 2E15 to 2E16 ions / CM2. The resulting first-doped polycrystalline silicon is N-type, and the second-doped polycrystalline silicon is P-type.

8. The method for manufacturing a semiconductor integrated circuit according to claim 1, characterized in that, After removing the first and second doped polycrystalline silicon that protrude above the upper surface of the fourth silicon oxide using a chemical mechanical polishing process, a fifth silicon oxide is grown on the polycrystalline silicon surface using a thermal oxidation process.

9. The method for manufacturing a semiconductor integrated circuit according to claim 8, characterized in that, The thickness of the fifth silicon oxide is greater than the thickness of the silicon nitride.

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