A system level interconnect structure for multiple homogeneous chips

Abstract

The application relates to the technical field of semiconductor manufacturing, and discloses a system-level interconnection structure for multiple same-chip systems, which comprises a substrate, a conversion board arranged on the substrate, and multiple chips arranged on the conversion board, wherein the multiple chips are interconnected through hybrid bonding. The structure realizes high-speed inter-chip interconnection through the conversion board, greatly reduces the number of input / output channels for external connection, reduces the wiring length of power supply channels through a vertical power supply module, and realizes efficient heat dissipation near a heat source through multiple heat dissipation modules used at different positions.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor manufacturing technology. Specifically, this invention relates to a system-level interconnect structure for multiple homogeneous chips. Background Technology

[0002] Wafer-level packaging (WLP) refers to a packaging technology where most or all of the packaging and testing procedures are performed directly on the wafer before dicing (singulation) to form individual chip components. Wafer-level packaging has the advantages of small package size and good electrical performance, and is currently widely used in the packaging of low-pin-count consumer integrated circuits (ICs).

[0003] In the prior art, Chinese patent "CN114823592A" discloses a system-on-a-chip (SoC) structure and its fabrication method. This structure includes a wafer substrate, integrated chips, a system configuration board, and a system heat dissipation module. The wafer substrate and integrated chips are bonded together via a wafer microbump array on the upper surface of the wafer substrate and a chip microbump array on the lower surface of the integrated chips. The wafer substrate and the system configuration board are bonded together via a copper pillar array on the wafer substrate and pads on the lower surface of the system configuration board. A molding compound layer is provided between the wafer substrate and the system configuration board to encapsulate the wafer substrate, integrated chips, and copper pillar array. The integrated chips are electrically connected to each other via a redistribution layer disposed on the top of the wafer substrate. The system configuration board is electrically connected to the integrated chips via the redistribution layer and the copper pillar array. The system heat dissipation module is attached to the lower surface of the wafer substrate.

[0004] However, existing technologies still have the following problems: the number of connections between multiple wafer-level chips is limited; the number of interconnects between wafer-level chips is limited; the bandwidth between wafer-level chips is limited; the communication path between wafer-level chips is long, so it is necessary to use an interposer, substrate or printed circuit board (PCB) for communication, which has a long power supply path and poor heat dissipation. Summary of the Invention

[0005] To at least partially address the aforementioned problems in the prior art, this invention proposes a system-level interconnect structure for multiple homogeneous chips, comprising:

[0006] substrate;

[0007] Adapter plate, which is arranged on the substrate; and

[0008] Multiple chips are arranged on the adapter board, wherein the multiple chips are interconnected by hybrid bonding.

[0009] In one embodiment of the present invention, the plurality of chips are connected to a first surface of the adapter plate via microbumps; and / or

[0010] The second side of the adapter plate is connected to the first side of the substrate via a C4 protrusion.

[0011] In one embodiment of the present invention, the system-level interconnect structure for multiple homogeneous chips further includes:

[0012] Multiple first printed circuit boards are arranged around the adapter board and the substrate.

[0013] In one embodiment of the invention, the adapter board is configured such that microbumps are exposed on at least a portion of the plurality of chips, and the chips are connected to a first side of the first printed circuit board via wire bonding.

[0014] In one embodiment of the present invention, the chip includes a plurality of homogeneous chips and / or a plurality of bare chips, wherein the homogeneous chips include a computing chip, an interface chip, and a storage chip.

[0015] In one embodiment of the present invention, the system-level interconnect structure for multiple homogeneous chips further includes a vertical power supply module connected to a second side of the first printed circuit board, the vertical power supply module comprising:

[0016] DC input terminal;

[0017] A voltage regulation circuit board, which is connected to the DC input terminal;

[0018] A power connector that connects to the voltage regulation circuit board;

[0019] A secondary power supply module is connected to the second side of the first printed circuit board module.

[0020] In one embodiment of the present invention, a plurality of vertical power supply modules are connected to the second side of the substrate, wherein a second printed circuit board is provided between the secondary power supply modules and power connectors of the plurality of vertical power supply modules, the plurality of power connectors are connected to the second side of the second printed circuit board, and the plurality of secondary power supply modules are connected to the first side of the second printed circuit board, wherein the second printed circuit board is configured to increase mechanical strength.

[0021] In one embodiment of the present invention, the system-level interconnect structure for multiple homogeneous chips further includes:

[0022] A first heat dissipation module is arranged on the plurality of chips, and the first heat dissipation module is connected to the first side of the first printed circuit board through a mechanical support member.

[0023] The second heat dissipation module is arranged among multiple vertical power supply modules; and

[0024] The third heat dissipation module is connected to the second side of the first printed circuit board.

[0025] In one embodiment of the present invention, the second heat dissipation module and / or the third heat dissipation module are an integrated heat sink and mechanical support.

[0026] In one embodiment of the present invention, the system-level interconnect structure for multiple homogeneous chips further includes:

[0027] An input / output connector is disposed on the second side of the first printed circuit board and is configured to connect to an external circuit board.

[0028] This invention offers at least the following advantages: It proposes a system-level interconnect structure for multiple homogeneous chips, where high-speed inter-chip interconnection is achieved through an interposer, significantly reducing the number of external input / output (IO) paths. This structure integrates a vertical power supply module, which, in addition to conventional chip functions, integrates devices to improve power integrity. The structure features multiple heat dissipation modules, effectively cooling the chips themselves and the power supply module, which consume over kilowatts. The structure integrates input / output connectors around the interposer, separating outward-fanning IO paths from power supply paths, further facilitating system interconnection. The input / output connectors can be connected to external PCB daughter cards via high-speed cables that meet signal integrity requirements. For IO or high-speed signals requiring fan-out, the interposer and PCB can be directly interconnected via wire bonding, reducing signal attenuation of high-speed signals on the substrate. Attached Figure Description

[0029] To further illustrate the advantages and other features of the various embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by the same or similar reference numerals for clarity.

[0030] Figure 1 A schematic planar diagram of a system-level interconnect structure for multiple homogeneous chips is shown in one embodiment of the present invention.

[0031] Figure 2 A cross-sectional schematic diagram of a system-level interconnect structure for multiple homogeneous chips is shown in one embodiment of the present invention. Detailed Implementation

[0032] It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0033] In this invention, unless otherwise specified, "arranged on," "arranged above," and "arranged on" do not exclude the possibility of an intermediate element between them. Furthermore, "arranged on or above" merely indicates the relative positional relationship between two components, and in certain cases, such as when the product orientation is reversed, it can also be converted to "arranged below or under," and vice versa.

[0034] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0035] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0036] It should also be noted that, in the embodiments of the present invention, only a portion of the components or parts may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, necessary components or parts can be added as needed for specific scenarios. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0037] It should also be noted that, within the scope of this invention, the terms "same," "equal," and "equal to" do not imply that the two values ​​are absolutely equal, but rather allow for a certain reasonable margin of error. In other words, the terms also encompass "substantially the same," "substantially equal," and "substantially equal to." Similarly, in this invention, the directional terms "perpendicular to," "parallel to," etc., also encompass the meanings of "substantially perpendicular to" and "substantially parallel to."

[0038] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0039] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1 A schematic planar view of a system-level interconnect structure for multiple homogeneous chips is shown in one embodiment of the present invention. Figure 1As shown, the wafer-level integrated structure includes multiple first printed circuit boards (PCBs) 101, interposers 102, dies 103, connectors 104, and a substrate 105. The interposers 102 are disposed on the substrate 105, and the multiple dies 103 are disposed on the interposers 102. The multiple first printed circuit boards 101 are disposed around the interposers 102 and the substrate 105, and the connectors 104 are disposed on the first printed circuit boards 101.

[0041] Figure 2 This diagram shows a cross-sectional schematic of a system-level interconnect structure for multiple homogeneous chips according to one embodiment of the present invention. The following is a detailed description in conjunction with... Figure 2 Further explanation of this structure. For example... Figure 2 As shown, multiple chips 103 can be connected to the first side of the adapter plate 102 via microbumps, and the adapter plate 102 is provided with through-silicon vias (TSVs). The second side of the adapter plate 102 can be connected to the first side of the substrate 105 via C4 bumps.

[0042] The chip 103 may include multiple homogeneous chips and / or diced, tested, but unpackaged bare chips with different functions. The homogeneous chips may be, for example, compute dies, interface dies, and memory chips (HBM or DDR). Multiple chips 103 can be interconnected via hybrid bonding, where "hybrid bonding" refers to simultaneously bonding the Cu electrodes and dielectric layers on the chip. Hybrid bonding eliminates the need for microbumps, reducing the interconnect pitch to below 10 μm. This reduction in interconnect width and pitch significantly increases interconnect density, thereby improving interconnect bandwidth.

[0043] The substrate 105 is used to bring out the power supply of the chip and the power control I / O related to the power supply to the central region of the structure so as to connect with the secondary power module 2044.

[0044] The edge of the adapter board 102 can be cut to expose the microbumps on the chip 103 that need to be fanned out, and the bonding pads on the chip 103 can be connected to the first side of the first printed circuit board 101 via wire bonding. The second side of the first printed circuit board 101 can be connected to the vertical power supply module and the connector 104. The connector 104 can be an input / output connector, which can be directly or via a cable connected to the external device 206. The external device 206 can be a low-speed general-purpose input / output (GPIO) PCB, or a high-speed double data rate (DDR) PCB, peripheral component interconnect express (PCIE) PCB, Ethernet PCB, or other external daughter cards or devices.

[0045] The vertical power supply module may include a DC input terminal (DC lN) 2041, a voltage regulation circuit board (VR PCB) 2042, a power connector 2043, and a secondary power module (MCM, Multi-Chip Module) 2044.

[0046] The DC input terminal 2041 is connected to the voltage regulation circuit board 2042. The voltage regulation circuit board 2042 is equipped with a voltage regulator module (VRM) and an inductor-capacitor filter module (LC). The voltage regulation circuit board 2042 is connected to the power connector 2043. The power connector 2043 is connected to the secondary power module 2044.

[0047] The second side of the substrate 105 can be connected to multiple vertical power supply modules. A second printed circuit board 205 can be disposed between the secondary power supply modules 2044 and the power connectors 2043 of the multiple vertical power supply modules. The power connectors 2043 are connected to the second side of the second printed circuit board 205, and the multiple secondary power supply modules 2044 are connected to the first side of the second printed circuit board 205. The second printed circuit board 205 is used to increase mechanical strength and is provided with copper pillars 2051. The copper pillars 2051 can provide a current path between the first-level circuit (voltage regulation circuit board 2042) and the second-level circuit (secondary power supply module 2044).

[0048] Multiple heat dissipation modules can be arranged on this structure. A first heat dissipation module (Top Thermal Module) 2031 can be arranged on the chip 103, and the first heat dissipation module 2031 can be connected to the first surface of the first printed circuit board 101 via a mechanical element (ME) 207. Second heat dissipation modules 2032 can be arranged between the multiple vertical power supply modules. A third heat dissipation module 2033 can be arranged on the second surface of the first printed circuit board 101. The second heat dissipation module 2032 and the third heat dissipation module 2033 can be integrated radiators and mechanical support components, meaning that the second heat dissipation module 2032 and the third heat dissipation module 2033 can simultaneously serve the functions of heat dissipation and mechanical support.

[0049] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A system-level interconnect structure for multiple homogeneous chips, characterized in that, include: substrate; An adapter plate, which is arranged on the substrate; Multiple chips are arranged on the adapter board, wherein the multiple chips are interconnected by hybrid bonding, wherein the multiple chips are connected to a first side of the adapter board by microbumps, and / or the second side of the adapter board is connected to the first side of the substrate by C4 bumps; Multiple first printed circuit boards are arranged around the adapter plate and the substrate; as well as A vertical power supply module is connected to the second side of the first printed circuit board, the vertical power supply module comprising: DC input terminal; A voltage regulation circuit board, which is connected to the DC input terminal; A power connector, which connects to the voltage regulation circuit board; and A secondary power supply module is connected to the second side of the first printed circuit board module; Multiple vertical power supply modules are connected to the second side of the substrate, and a second printed circuit board is provided between the secondary power supply modules and power connectors of the multiple vertical power supply modules. Multiple power connectors are connected to the second side of the second printed circuit board, and multiple secondary power supply modules are connected to the first side of the second printed circuit board, wherein the second printed circuit board is configured to increase mechanical strength.

2. The system-level interconnect structure for multiple homogeneous chips according to claim 1, characterized in that, The adapter board is configured such that microbumps are exposed on at least a portion of the plurality of chips, and the chips are connected to a first side of the first printed circuit board via wire bonding.

3. The system-level interconnect structure for multiple homogeneous chips according to claim 2, characterized in that, The chip includes multiple homogeneous chips and / or multiple bare chips, and the homogeneous chips include computing chips, interface chips, and storage chips.

4. The system-level interconnect structure for multiple homogeneous chips according to claim 1, characterized in that, Also includes: A first heat dissipation module is arranged on the plurality of chips, and the first heat dissipation module is connected to the first side of the first printed circuit board through a mechanical support member. The second heat dissipation module is arranged among multiple vertical power supply modules; as well as The third heat dissipation module is connected to the second side of the first printed circuit board.

5. The system-level interconnect structure for multiple homogeneous chips according to claim 4, characterized in that, The second and / or third heat dissipation modules are integrated heat sinks and mechanical support components.

6. The system-level interconnect structure for multiple homogeneous chips according to claim 1, characterized in that, Also includes: An input / output connector is disposed on the second side of the first printed circuit board and is configured to connect to an external circuit board.

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