Semiconductor device having a doped gate dielectric layer and method of forming the same

Abstract

Semiconductor devices having doped gate dielectric layers and methods of forming the same are disclosed. In embodiments, a semiconductor device is provided that includes a first doped gate dielectric layer and a second doped gate dielectric layer, where the first and second doped gate dielectric layers include a high-k material doped with a dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than a second concentration of the dipole dopant of the second doped gate dielectric layer, and the concentration of the dipole dopant in the first doped gate dielectric layer peaks at a greater depth than the concentration of the dipole dopant in the second doped gate dielectric layer. A first gate electrode is over the first doped gate dielectric layer, and a second gate electrode of the same width as the first gate electrode is over the second doped gate dielectric layer.

Description

Technical Field

[0001] This application relates to semiconductor devices having a doped gate dielectric layer and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to a first aspect of this disclosure, a semiconductor device is provided, comprising: a first channel region in a first device region, wherein the first device region has a first conductivity type; a second channel region in a second device region, wherein the second device region has the first conductivity type; a third channel region in a third device region, wherein the third device region has a second conductivity type different from the first conductivity type; a first doped gate dielectric layer disposed over the first channel region, wherein the first doped gate dielectric layer comprises a high-k material doped with a first dipole dopant, wherein the first doped gate dielectric layer has a first concentration of the first dipole dopant, wherein the first doped gate dielectric layer has a first concentration distribution of the first dipole dopant, wherein the first concentration distribution has a first distance from a first concentration peak of the first dipole dopant to the first channel region, wherein the first dipole dopant is an n-type dipole dopant; and a second doped gate dielectric layer disposed over the second channel region, wherein the second doped gate dielectric layer comprises a high-k material doped with the first dipole dopant. The third channel region comprises: a second doped gate dielectric layer having a second concentration of the first dipole dopant; a third doped gate dielectric layer disposed above the third channel region; a third doped gate dielectric layer comprising a high-k material doped with a second dipole dopant different from the first dipole dopant; a first gate electrode disposed above the first doped gate dielectric layer; a second gate electrode disposed above the second doped gate dielectric layer; and a third gate electrode disposed above the third doped gate dielectric layer; the third gate electrode comprising a second conductive layer and a first filling layer disposed above the first conductive layer; a second gate electrode disposed above the second doped gate dielectric layer; and a third gate electrode disposed above the third doped gate dielectric layer; the third gate electrode comprising a second conductive layer and a second filling layer disposed above the second conductive layer; wherein the first filling layer and the second filling layer have the same width.

[0005] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first gate dielectric layer over a first channel region in a first device region, a second channel region in a second device region, and a third channel region in a third device region, wherein the first device region and the second device region have a first conductivity type, and wherein the third device region has a second conductivity type different from the first conductivity type; forming a first dipole layer including a first dipole dopant over the first gate dielectric layer in the first device region; performing a first annealing process to convert the first gate dielectric layer in the first device region into a first doped gate dielectric layer including the first dipole dopant, wherein the first annealing process has a first thermal budget; removing a remaining portion of the first dipole layer; and after removing the remaining portion of the first dipole layer, forming a second dipole layer including the first dipole dopant over the first gate dielectric layer in the second device region, wherein the... The thickness of the second dipole layer is thinner than that of the first dipole layer; a second annealing process is performed to convert the first gate dielectric layer in the second device region into a second doped gate dielectric layer including the first dipole dopant, wherein the second annealing process has a second thermal budget different from the first thermal budget; the remaining portion of the second dipole layer is removed; the first gate dielectric layer in the third device region is converted into a third doped gate dielectric layer, wherein the third doped gate dielectric layer includes a second dipole dopant different from the first dipole dopant; and a first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode includes a conductive layer and a fill layer filling the conductive layer, wherein each of the fill layers has a substantially the same width.

[0006] According to a third aspect of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a first gate dielectric layer over a first channel region in a first p-type region, over a second channel region in a second p-type region, and over a third channel region in an n-type region; performing a first doping cycle to convert the first gate dielectric layer in the first p-type region into a first doped gate dielectric layer, wherein the first doping cycle comprises: forming a first dipole layer over the first gate dielectric layer in the first p-type region, wherein the first dipole layer includes a first dipole dopant and has a first thickness; and performing a first annealing; and after the first doping cycle, performing a second doping cycle to convert the first gate dielectric layer in the second p-type region into a second doped gate dielectric layer. The second doping cycle includes: forming a second dipole layer over a first gate dielectric layer in the second p-type region, wherein the second dipole layer includes the first dipole dopant and has a second thickness different from the first thickness; and performing a second annealing; performing a third doping cycle to convert the first gate dielectric layer in the n-type region into a third doped gate dielectric layer, wherein the third doping cycle includes: forming a third dipole layer, the third dipole layer including a second dipole dopant different from the first dipole dopant; and performing a third annealing; and forming a first gate electrode over the first doped gate dielectric layer, forming a second gate electrode over the second doped gate dielectric layer, and forming a third gate electrode over the third doped gate dielectric layer. Attached Figure Description

[0007] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27A , Figure 27B , Figure 28A , Figure 28B , Figure 29A , Figure 29B , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B , Figure 31C , Figure 32A , Figure 32B , Figure 32C , Figure 33A , Figure 33B , Figure 34A , Figure 34B , Figure 35A and Figure 35B This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments.

[0010] Figure 21C and Figure 24C The dipole dopant concentration distribution along the thickness direction of the gate dielectric layer is shown according to some embodiments.

[0011] Figure 36 This is a flowchart of a doping loop in which a dipole dopant is doped into a gate dielectric layer according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, this document may use spatially relevant terms (e.g., "below," "under," "lower," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0014] As discussed in more detail below, the embodiments shown in this disclosure provide a semiconductor device including a doped gate dielectric layer. Specifically, the doped dielectric layer is doped with one or more dipole dopants to influence the threshold voltage of the gate structure and to give the gate structure different threshold voltages in different regions. In some embodiments, each dipole dopant material can be doped into the gate dielectric layer by separate doping cycles. Therefore, the concentration and concentration distribution of each dipole dopant in one or more doped gate dielectric layers can be controlled individually.

[0015] The embodiments are described below in a specific context (e.g., including a die containing a nanoFET). However, various embodiments can be applied to dies that replace or are combined with nanoFETs to include other types of transistors (e.g., fin field-effect transistors (FinFETs), or planar transistors, etc.).

[0016] Figure 1An example of a nanoFET 10 (e.g., a nanowire FET, or a nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nanoFET 10 includes nanostructures 55 (e.g., nanosheets, or nanowires, etc.) situated above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 act as channel regions of the nanoFET. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above these adjacent isolation regions 68. Although the isolation regions 68 are described / shown as separated from the substrate 50, as used herein, the term "substrate" may refer only to the semiconductor substrate or to a combination of the semiconductor substrate and the isolation regions. Furthermore, although the bottom portion of the fin 66 is shown as being of a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0017] A gate dielectric layer 142 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. A gate electrode 153 is located above the gate dielectric layer 142. An epitaxial source / drain region 92 is disposed on the fin 66, located on the opposite side of the gate dielectric layer 142 and the gate electrode 153.

[0018] Figure 1 Reference cross sections used in the following figures are also shown. Cross section A-A' is along the longitudinal axis of the gate electrode 153 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in a direction, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain regions of the nanoFET. These reference cross sections are referenced in the following figures for clarity.

[0019] Some embodiments discussed herein are discussed in the context of nanoFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs or FinFETs.

[0020] Figures 2 to 32C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET 10 according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A and Figure 32A It shows Figure 1 The reference section A-A' is shown. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B and Figure 32B It shows Figure 1 The reference section B-B' is shown. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 30C , Figure 31C and Figure 32C It shows Figure 1 The reference section C-C' shown in the figure. Figures 2 to 15B , Figure 30C , Figure 31C and Figure 32CFeatures in the first region 50A, the second region 50B, or the third region 50C are shown.

[0021] exist Figure 2 In this embodiment, a substrate 50 is provided for forming a nano-FET 10. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, and may be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0022] In addition, Figure 2 In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). The first semiconductor material and the second semiconductor material can be materials that have high etch selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51. For illustrative purposes and as discussed in more detail below, the first semiconductor layer 51 will be removed, and the second semiconductor layer 53 will be patterned to form the channel region of the nanoFET 10. However, in some embodiments, the second semiconductor layer 53 will be removed, and the first semiconductor layer 51 can be patterned to form the channel region of the nanoFET 10.

[0023] For illustrative purposes, the multilayer stack 64 is shown as comprising three layers each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0024] refer to Figure 3According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50 by etching trenches in multilayer stack 64 and substrate 50, respectively. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-52C (collectively referred to as first nanostructures 52) from second semiconductor layer 53, and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) from first semiconductor layer 51. First nanostructures 52 and second nanostructures 54 can be further collectively referred to as nanostructure 55.

[0025] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes (including dual patterning or multiple patterning processes) can be used to pattern the fins 66 and nanostructures 55. Typically, dual or multiple patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with a pitch, for example, smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66 and nanostructures 55.

[0026] Figure 3 It is shown that each of the fins 66 and nanostructures 55 always has a consistent width. In some embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 increases in the direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and trapezoidal shape.

[0027] exist Figure 4In the substrate 50, shallow trench isolation (STI) regions 68 are formed adjacent to the fins 66. The STI regions 68 can be formed by depositing an insulating material on the substrate 50, fins 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, a liner (not shown separately) can be formed first along the surfaces of the substrate 50, fins 66, and nanostructure 55. A filler material, such as those discussed above, can then be formed on the liner.

[0028] Then, a removal process is applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes such as chemical mechanical polishing (CMP), etch-back processes, or combinations thereof can be used. The planarization process exposes the nanostructure 55 so that the top surfaces of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0029] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in the first region 50A and the second region 50B protrude between adjacent STI regions 68. Furthermore, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface (e.g., a dish shape), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or concave by appropriate etching. The STI region 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than etching the material of the fins 66 and the nanostructure 55). For example, oxide removal can be performed using dilute hydrofluoric acid (dHF).

[0030] The above is about Figures 2 to 4The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure can include the alternating semiconductor materials described above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxial growth material can be in-situ doped during growth, which can avoid prior and / or subsequent implantation, but in-situ and implantation doping can be used together.

[0031] In addition, Figure 4 In this process, suitable wells (not shown separately) can be formed in the fin 66 and nanostructure 55, and / or substrate 50. The wells can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type and p-type regions. In some embodiments, a p-type well is formed in the n-type region, and an n-type well is formed in the p-type region. In some embodiments, either a p-type well or an n-type well is formed in both the n-type and p-type regions. An n-type well can be formed by performing n-type impurity implantation. The n-type impurity can be at a concentration of 10... 13 cm -3 Up to 10 14 cm -3 Phosphorus, arsenic, antimony, etc., are injected into the region at concentrations within a certain range. A p-type trap can be formed by implanting p-type impurities. The p-type impurities can be at concentrations of 10... 13 cm -3 Up to 10 14 cm -3 Boron, boron fluoride, indium, etc., are implanted into the region at concentrations within the specified range. After implantation, an annealing process can be performed to repair damage and activate the implanted p-type and / or n-type impurities. In some embodiments for epitaxial growth of fin 66 and nanostructure 55, the grown material can be in-situ doped during growth, which avoids implantation; however, in-situ and implantation doping can be used together.

[0032] exist Figure 5In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed on the dummy dielectric layer 70, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 72 can be deposited on the dummy dielectric layer 70, and then planarized, for example, by chemical mechanical polishing (CMP). The mask layer 74 can be deposited on the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, etc. It should be noted that, for illustrative purposes only, the dummy dielectric layer 70 is shown as covering only the fin 66 and nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0033] Figures 6A to 32C Various additional steps for fabricating the nanoFET 10 according to some embodiments are illustrated. Figure 6A and Figure 6B In this process, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see [link]). Figure 5 A mask 78 is formed. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover the respective channel regions of the fins 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from its adjacent dummy gates 76. The dummy gates 76 may also have a longitudinal orientation substantially perpendicular to the longitudinal direction of the respective fins 66.

[0034] exist Figure 7A and Figure 7B In the middle, the first spacer layer 80 and the second spacer layer 82 are respectively formed in Figure 6A and Figure 6B Above the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7BIn this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68, along the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78, and along the sidewalls of the dummy gate 76 and dummy gate dielectric 71. A second spacer layer 82 is deposited on top of the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0035] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. Appropriate types of impurities (e.g., n-type or p-type) can be implanted into the fin 66 and / or nanostructure 55. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The LDD region can have a density of 10... 15 cm -3 Up to 10 19 cm -3 The range of impurity concentrations. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0036] exist Figure 8A and Figure 8B In the process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 serve to self-align the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), an anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and that the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, an anisotropic etching process can be used to etch the second spacer layer 82, wherein the first spacer layer 80 acts as an etching stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As shown. Subsequently, when the exposed portion of the first spacer layer 80 is etched, the second spacer 83 acts as a mask, thereby forming the first spacer 81, as... Figure 8A As shown.

[0037] like Figure 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0038] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, etc. Furthermore, different structures and steps can be used to form n-type and p-type devices.

[0039] exist Figure 9A and Figure 9B In some embodiments, a first recess 86 is formed in the fin 66, nanostructure 55, and substrate 50. An epitaxial source / drain region is then formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate 50. Figure 9A As shown, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first recess 86 is set below the top surface of the STI region 68; and so on. The first recess 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first recess 86, a first spacer 81, a second spacer 83, and a mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after it has reached a desired depth.

[0040] exist Figure 10A and Figure 10B In this process, the layer of nanostructure 55 formed from a first semiconductor material (e.g., first nanostructure 52) is etched to form a sidewall recess 88 by etching the sidewall portion exposed by the first recess 86. Although in Figure 10BThe sidewall of the first nanostructure 52 in the sidewall recess 88 is illustrated as straight, but the sidewall can be concave or convex. The sidewall can be etched using an isotropic etching process (e.g., wet etching).

[0041] exist Figures 11A-11C In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figure 10A and Figure 10B An internal spacer layer is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 will be replaced by the corresponding gate structure.

[0042] The internal spacer layer can be deposited using a conformal deposition process (e.g., CVD, ALD, etc.). The internal spacer layer can comprise materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, such as a low-k material with a k-value less than about 3.5. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54 in the first region 50A and the second region 50B, the outer wall of the first internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54.

[0043] Furthermore, although the outer wall of the first internal spacer 90 is in Figure 11B The figure shows a straight line, but the outer wall of the first inner spacer 90 can be concave or convex. As an example, Figure 11C An embodiment is illustrated in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer is recessed from the sidewalls of the first nanostructure 52. The internal spacer layer can be etched using an anisotropic etching process (e.g., RIE, NBE, etc.). The first internal spacer 90 can be used to prevent interference with the source / drain regions subsequently formed by subsequent etching processes (e.g., etching processes for forming gate structures) (e.g., hereinafter referred to as...). Figures 12A-12C The discussion concerns the damage to the epitaxial source / drain region (92).

[0044] exist Figures 12A-12C In the first recess 86, an epitaxial source / drain region 92 is formed. One or more source / drain regions may individually or collectively refer to a source or drain, depending on the context. In some embodiments, the epitaxial source / drain region 92 may apply stress to the second nanostructure 54, thereby improving performance. Figure 12BAs shown, epitaxial source / drain regions 92 are formed in the first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance such that the epitaxial source / drain regions 92 are not short-circuited with the subsequently formed gate of the resulting nanoFET 10.

[0045] The epitaxial source / drain region 92 may include any acceptable material, such as materials suitable for n-type or p-type devices. For example, when forming an n-type device, the epitaxial source / drain region 92 may include a material that applies tensile strain to the channel region, such as silicon, SiC, SiCP, SiIP, etc. Similarly, when forming a p-type device, the epitaxial source / drain region 92 may include a material that applies compressive strain to the channel region, such as SiGe, SiGeB, Ge, GeSn, etc.

[0046] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the process discussed earlier for forming lightly doped source / drain regions, followed by an annealing process. The source / drain region can have a size between approximately 1 × 10⁻⁶. 19 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0047] As a result of the epitaxial process used to form the epitaxial source / drain regions 92, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets merge adjacent epitaxial source / drain regions 92 of the same device, such as... Figure 12A As shown. In other embodiments, such as Figure 12C As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 12A and Figure 12CIn the illustrated embodiment, a first spacer 81 may be formed on the top surface of the STI region 68 to block or limit lateral epitaxial growth. In some other embodiments, the first spacer 81 may cover a portion of the sidewall of the nanostructure 55 to further block epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material, thereby allowing the epitaxial growth region to extend to the surface of the STI region 68.

[0048] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0049] Figure 12D An embodiment is shown in which the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first internal spacer 90 are concave, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. Figure 12D As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90 and can extend through the sidewalls of the second nanostructure 54.

[0050] exist Figures 13A-13C In the middle, the first interlayer dielectric (ILD) 96 is deposited on respectively Figure 6A , Figure 12B and Figure 12A Above the structure shown ( Figures 7A-12D The process remains unchanged. Figure 6A(See the cross-section shown). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and first spacer 81. CESL 94 may include a dielectric material having an etch rate different from that of the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0051] exist Figure 14A and Figure 14B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76 and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0052] exist Figure 15A and Figure 15B In one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form the second recess 98. A portion of the dummy gate dielectric 71 in the second recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlays a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The portions of the nanostructure 55 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer while the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate 76.

[0053] exist Figure 16A and Figure 16B In the process, the first nanostructure 52 is removed, thereby forming an opening 99 between the second nanostructure 54 and / or the fin 66. The first nanostructure 52 can be removed by an isotropic etching process (e.g., wet etching, etc.) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In some embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52. In some embodiments where the first nanostructure 52 comprises, for example, Si or SiC and the second nanostructure 54 comprises, for example, SiGe, hydrogen fluoride, another fluorine-based etchant, etc., can be used to remove the first nanostructure 52.

[0054] The above process can be used to form various types of devices (e.g., transistors) in different regions of a substrate. For example, in Figure 17A and Figure 17BThe diagram illustrates three device regions of substrate 50, such as a first region 50A, a second region 50B, and a third region 50C, in which three different types of devices are formed, as discussed in more detail below. In some embodiments, the first region 50A and the second region 50B have the same conductivity type, such as p-type. For example, in one embodiment, both the first region 50A and the second region 50B are used to form p-type devices, such as PMOS transistors (e.g., p-type nanoFETs), or n-type devices, such as NMOS transistors (e.g., n-type nanoFETs). In some embodiments, the first region 50A and the second region 50B are used to form different devices and have the same conductivity type. In such embodiments, the first region 50A may be a logic device region, and the second region 50B may be an I / O device region. Alternatively, both the first region 50A and the second region 50B may be logic device regions or I / O regions with different functional circuitry and the same conductivity type. In some embodiments, the third region 50C may have a different conductivity type than the first region 50A and the second region 50B. For example, when the first region 50A and the second region 50B are used to form a p-type device, the third region 50C is used to form an n-type device. Alternatively, the third region 50C is used to form a p-type device, while the first region 50A and the second region 50B are used to form an n-type device. The first region 50A, the second region 50B, and the third region 50C can be physically separated from each other, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed therebetween. Although one first region 50A, one second region 50B, and one third region 50C are shown, any number of first regions 50A, second regions 50B, and third regions 50C can be provided. Note that, as Figures 2-16B The device shown can be implemented in any of the first region 50A, the second region 50B, and the third region 50C.

[0055] A replacement gate is formed in the second recess 98 and the opening 99. Figure 17A and Figure 17BIn some embodiments, an interface layer 100 is formed over the exposed surfaces of the second nanostructure 54 and fin 66 in the first region 50A, the second region 50B, and the third region 50C. The interface layer 100 may include silicon oxide. The interface layer 100 may have a thickness of about 10 angstroms to about 30 angstroms. In some embodiments, chemical oxidation is performed using an oxidant such as SPM (a mixture of H2SO4 and H2O2), SCl (a mixture of NH4OH and H2O2), or ozone-deionized water (a mixture of O3 and deionized water) to oxidize the outer portions of the second nanostructure 54 and fin 66. In some embodiments, to form the interface layer 100, thermal oxidation is performed by treating (e.g., immersing) the second nanostructure 54 and fin 66 in an oxygen-containing gas source, wherein, as an example, the oxygen-containing gas source includes, for example, a mixture of N2O, O2, N2O and H2, or a mixture of O2 and H2. Thermal oxidation may be performed at a temperature between about 500°C and about 1000°C. Note that in the illustrated embodiment, the interface layer 100 is formed by oxidizing the outer portions of the second nanostructure 54 and the fin 66 into oxides. Therefore, the interface layer 100 is selectively formed on the exposed surfaces of the second nanostructure 54 and the fin 66, but not on other surfaces, such as the sidewalls of the first internal spacer 90 and the first spacer 81.

[0056] exist Figure 18A and Figure 18B In some embodiments, a first gate dielectric layer 104 is formed in the second recess 98 and opening 99 in the first region 50A, the second region 50B, and the third region 50C. The first gate dielectric layer 104 may be deposited over the interface layer 100 (e.g., surrounding the second nanostructure 54), along the sidewalls of the first spacer 81, and along the upper surface of the first ILD 96. In exemplary embodiments, the first gate dielectric layer 104 may be, for example, a high-k material having a dielectric constant greater than 7.0, and may comprise metal oxides or metal silicates. For example, the first gate dielectric layer 104 may comprise oxides or silicates of Hf, Zr, etc., or combinations thereof. The first gate dielectric layer 104 may have a thickness T of about 5 angstroms to about 30 angstroms. Methods for forming the first gate dielectric layer 104 may include molecular beam deposition (MBD), ALD, PECVD, etc. In some embodiments, the first gate dielectric layer 104 is formed by ALD at a temperature between about 200°C and about 400°C.

[0057] Next, one or more doping cycles can be performed (e.g., one or more cycles can be performed). Figure 36The doping cycle shown is used to dope one or more dipole dopant materials into individual gate dielectric layers in one or more device regions. The dipole dopant materials can create a difference in the potential of the gate structure and thus can affect the threshold voltage Vt of the gate structure.

[0058] refer to Figures 19A to 21C A first doping cycle is performed to form a first doped gate dielectric layer 112 in the first region 50A (see below). Figure 21A and Figure 21B ).exist Figure 19A and Figure 19B In the middle, execute step S302 (see Figure 36 According to some embodiments, a first dipole layer 106 is formed (e.g., conformally) over a first gate dielectric layer 104 in a first region 50A, a second region 50B, and a third region 50C. The first dipole layer 106 may be an oxide or nitride of a first dipole dopant. In some embodiments where the first region 50A and the second region 50B are used to form a p-type device (e.g., a PMOS transistor), the first dipole layer 106 may include La₂O₃, MgO, SrO, Y₂O₃, etc., and the first dipole dopant in the first dipole layer 106 may be an n-type dipole dopant material, such as La, Mg, Sr, Y, or elements with a stronger oxygen attraction than Si. The dipole dopant material doped in the gate dielectric layer can form a dipole moment with the material of the interface layer 100, thereby creating a potential difference across the entire gate structure, thus allowing adjustment of the threshold voltage Vt of the gate structure. The n-type dipole dopant can reduce the threshold voltage Vt of the gate structure (for NMOS or PMOS devices). The first dipole layer 106 can be formed by any suitable deposition method (e.g., ALD or CVD). The thickness of the first dipole layer 106 can be in the range of 1 nm to 10 nm. For example, the first dipole layer 106 can be formed by ALD with 2 to 20 deposition cycles.

[0059] exist Figure 20A and Figure 20B In the middle, execute step S304 (see Figure 36According to some embodiments, a patterned mask 110 is formed to cover a first region 50A and expose a second region 50B and a third region 50C, and to remove a first dipole layer 106 in the second region 50B and the third region 50C. For example, the patterned mask 110 is formed and patterned to expose the first dipole layer 106 in the second region 50B and the third region 50C, while masking (e.g., protecting) the first dipole layer 106 in the first region 50A so that it is not removed. In some embodiments, the patterned mask 110 is formed by covering a mask layer of the first dipole layer 106 in the first region 50A, the second region 50B, and the third region 50C and removing the mask layer to expose the first dipole layer 106 in the second region 50B and the third region 50C. The mask layer can be patterned by using a photoresist layer formed on top of the mask layer, and patterning the photoresist layer such that portions of the photoresist layer disposed in the second region 50B and the third region 50C are removed to expose portions of the mask layer in the second region 50B and the third region 50C. These portions of the mask layer in the second region 50B and the third region 50C are then etched to form a shape as shown in the image. Figure 20A and Figure 20B The patterned mask 110 is shown. After removing the mask layer in the second region 50B and the third region 50C by an ashing process and / or a wet cleaning process, the photoresist layer is removed. The patterned mask 110 may include an oxide layer (e.g., TiO2, SiO2, Al2O3), a nitride layer (e.g., TiN), an organic undercoat antireflective coating (BARC), or a combination thereof. In some embodiments, the patterned mask 110 may be a patterned photoresist layer.

[0060] The first dipole layer 106 in the second region 50B and the third region 50C is removed by a suitable etching process (e.g., wet etching). After the first dipole layer 106 in the second region 50B and the third region 50C is removed, the patterned mask 110 can be removed by a suitable process (e.g., by a wet etching process) using an etchant that has a higher etching rate on the material of the patterned mask 110 than on the materials of the first gate dielectric layer 104 and the first dipole layer 106.

[0061] exist Figure 21A and Figure 21B In the middle, execute step S306 (see Figure 36According to some embodiments, a first annealing process is performed to diffuse a first dipole dopant in the first dipole layer 106 into the first gate dielectric layer 104, thereby forming a first doped gate dielectric layer 112 in the first region 50A. In some embodiments, the first annealing process is soak annealing. Soak annealing may include applying a fixed temperature of about 450°C to about 950°C for about 5 seconds to 300 seconds in an ambient environment of N2, NH3, O2, N2O, or combinations thereof. In some embodiments, the first annealing process may be spike annealing. Spike annealing may include applying a fixed temperature of about 450°C to about 750°C for about 5 seconds to about 120 seconds, rapidly increasing the temperature to a peak temperature of about 1050°C, maintaining the peak temperature for a short period of time, for example, about 0.5 seconds to about 5 seconds, after which the temperature rapidly decreases.

[0062] The first dipole dopant is dispersed in the first doped gate dielectric layer 112. Figure 21C The diagram illustrates the concentration distribution of the first dipole dopant along the thickness direction of the first doped gate dielectric layer 112. In some embodiments, a sufficient amount of first dipole dopant may be present in the first doped gate dielectric layer 112, provided that the thickness of the first dipole layer 106 is sufficient and the thermal budget of the first annealing process is adequate. In some embodiments, the first doped gate dielectric layer 112 may have approximately 1E12 atoms / cm². 3 Approximately 1E16 atoms / cm 3 The average atomic concentration of the first dipole dopant. In some embodiments, the distance D1 from the peak concentration of the first dipole dopant in the first doped gate dielectric layer 112 along its thickness direction to the bottom surface of the first doped gate dielectric layer 112 is greater than half or 2 / 3 of the thickness T of the first doped gate dielectric layer 112, and the peak concentration can be offset from the upper surface of the first doped gate dielectric layer 112.

[0063] After applying the first annealing process, the remaining portion of the first dipole layer 106 in the first region 50A is removed. The first dipole layer 106 can be removed by a suitable etching method, such as a wet etching process that etches the first dipole layer 106 at a faster rate than the first doped gate dielectric layer 112 in the first region 50A and the first gate dielectric layer 104 in the second region 50B and the third region 50C.

[0064] Next reference Figures 22A to 24C According to some embodiments, a second dipole cycle is performed (e.g., as...). Figure 36Steps S302-S306 shown are used to form a second doped gate dielectric layer 118 in the second region 50B (see below). Figure 24A and Figure 24B ).exist Figure 22A and Figure 22B In this process, a second dipole layer 114 can be formed over the first doped gate dielectric layer 112 in the first region 50A and the first gate dielectric layer 104 in the second region 50B and the third region 50C. The second dipole layer 114 can be an oxide or nitride of the first dipole dopant (e.g., an n-type dipole dopant). In some embodiments, the second dipole layer 114 is formed of the same material as the first dipole layer 106 and has a thickness different from that of the first dipole layer 106, for example, thinner than the first dipole layer. For example, the second dipole layer 114 can have a thickness of 1 nm to 8 nm, which can be 0.05 to 0.99 times or equal to the thickness of the first dipole layer 106. In some embodiments, the second dipole layer 114 can be formed by ALD, for example, by 2 to 16 ALD deposition cycles.

[0065] exist Figure 23A and Figure 23B In this process, a patterned mask layer 116 is formed to cover the second region 50B and expose the first region 50A and the third region 50C. Exposed portions of the second dipole layer 114, such as the second dipole layer 114 in the first region 50A and the third region 50C, can be removed. The patterned mask layer 116 can be formed using the same or similar formation methods and from the same or similar materials as the patterned mask 110. A suitable etching process (e.g., wet etching) can be performed to remove the second dipole layer 114 in the first region 50A and the third region 50C, while the patterned mask layer 116 masks (e.g., protects) the second region 50B from the etching process. After removing the second dipole layer 114 in the second region 50B, the patterned mask layer 116 can be removed by a suitable process, such as a wet etching process using an etchant that has a higher etching rate for the material of the patterned mask layer 116 than for the materials of the second dipole layer 114, the first doped gate dielectric layer 112 and the first gate dielectric layer 104.

[0066] exist Figure 24A and Figure 24BIn some embodiments, a second annealing process is then performed to diffuse the first dipole dopant in the second dipole layer 114 into the first gate dielectric layer 104 in the second region 50B, thereby forming a second doped gate dielectric layer 118 in the second region 50B. The second annealing process can be immersion annealing or spike annealing. In some embodiments, the second annealing process is the same as the first annealing process, for example, one of the same immersion annealing or spike annealing as the first annealing, having the same temperature, time, and thermal budget. In some embodiments, the second annealing process may have a lower temperature and / or a shorter time period compared to the first annealing process, so as to have a smaller impact on the first dipole dopant in the first doped gate dielectric layer 112. When the second annealing process provides a low thermal budget, a sufficient amount of the first dipole dopant can diffuse into the first gate dielectric layer 104 to form the second doped gate dielectric layer 118 because the second dipole layer 114 is thin. In some embodiments, the second annealing process is an immersion annealing process, which may include applying a fixed temperature of about 450°C to about 900°C for about 5 seconds to 300 seconds in an ambient environment of N2, NH3, O2, N2O, or a combination thereof, or applying a fixed temperature of about 400°C to about 750°C for about 3 seconds to 200 seconds. In some embodiments, the first annealing process is a spike annealing process, which may include applying a fixed temperature of about 450°C to about 750°C for about 5 seconds to about 120 seconds, rapidly raising the temperature to a peak temperature of about 1050°C or about 900°C, maintaining the peak temperature for a short time (e.g., about 0.5 seconds to about 5 seconds or about 3 seconds), and then rapidly decreasing the temperature.

[0067] Figure 24C The diagram illustrates the concentration distribution of the first dipole dopant in the first doped gate dielectric layer 112 and the second doped gate dielectric layer 118 along their thickness directions after a second annealing process, according to some embodiments. In some embodiments, after the second annealing process, the concentration peak of the first dipole dopant shifts toward the interface layer 100 and the corresponding nanostructures 54A-54C (e.g., toward the bottom surface of the first doped gate dielectric layer 112). For example, after the second annealing process, the distance D2 from the concentration peak of the first dipole dopant in the first doped gate dielectric layer 112 to the bottom surface of the first doped gate dielectric layer 112 is less than the distance D1, where distance D1 is the distance from the concentration peak of the first dipole dopant to the bottom surface of the first doped gate dielectric layer 112 before the second annealing process. Furthermore, the distance D2 is also smaller than the distance D3 from the peak concentration of the first dipole dopant in the second doped gate dielectric layer 118 to the bottom surface of the second doped gate dielectric layer 118, because the first dipole dopant in the first doped gate dielectric layer 112 is annealed by both the first annealing process and the second annealing process.

[0068] refer to Figures 25A to 27B According to some embodiments, a third doping cycle is performed (e.g., as...). Figure 36 Steps S302-S306 shown are used to form a third doped gate dielectric layer 126 in the third region 50C (see below). Figure 27A and Figure 27B ).exist Figure 25A and Figure 25B In this process, a third dipole layer 120 can be formed over the first doped gate dielectric layer 112 in the first region 50A, the second doped gate dielectric layer 118 in the second region 50B, and the first gate dielectric layer 104 in the third region 50C. The third dipole layer 120 can be an oxide or nitride of the second dipole dopant, such as TiO2, Al2O3, AlN, Ga2O3, In2O3, Nb2O5, ZnO2, etc. The second dipole dopant can be different from the first dipole dopant. For example, the second dipole dopant can be a different type of dipole dopant than the first dipole dopant, such as an n-type dipole dopant, but the second dipole dopant can be of the same type as the first dipole dopant. In some embodiments, the third dipole layer 120 includes a p-type dipole dopant, such as, but not limited to, Ti, Al, Ga, In, Nb, Zn, or elements with a weaker oxygen attraction than Si. In some embodiments, when the first dipole dopant is La, the second dipole dopant may have a greater diffusivity than the first dipole dopant, such as Y, Lu, or Sr. Thus, a sufficient amount of the second dipole dopant can diffuse into the first gate dielectric layer 104 in the third region 50C with a limited thermal budget, without significantly affecting the first dipole dopant in the first doped gate dielectric layer 112 and the second doped gate dielectric layer 118. The thickness of the third dipole layer 120 may be the same as or different from the thickness of the first dipole layer 106 or the second dipole layer 114.

[0069] exist Figure 26A and Figure 26BIn this process, a patterned mask layer 122 is formed to cover the third region 50C and expose the first region 50A and the second region 50B. Exposed portions of the third dipole layer 120, such as the third dipole layer 120 in the first region 50A and the second region 50B, can be removed. The patterned mask layer 122 can be formed using the same or similar formation methods and from the same or similar materials as the patterned mask 110. A suitable etching process (e.g., wet etching) can be performed to remove the third dipole layer 120 in the first region 50A and the second region 50B, while the patterned mask layer 122 masks (e.g., protects) the third region 50C from the etching process. After the third dipole layer 120 in the second region 50B is removed, the patterned mask layer 122 can be removed by a suitable process, such as a wet etching process using an etchant that has a higher etching rate for the material of the patterned mask layer 122 than for the materials of the third dipole layer 120, the first doped gate dielectric layer 112, and the second doped gate dielectric layer 118.

[0070] exist Figure 27A and Figure 27B In some embodiments, a third annealing process is performed to diffuse the third dipole dopant in the third dipole layer 120 into the first gate dielectric layer 104 in the third region 50C, thereby forming a third doped gate dielectric layer 126 in the third region 50C. The third annealing process can be immersion annealing or spike annealing. The third annealing process can be controlled independently. In some embodiments, the third annealing process can be the same as or similar to the first or second annealing process, for example, one of immersion annealing or spike annealing that is the same as or similar to the first or second annealing process, having the same temperature, time, and thermal budget. In some embodiments, the thermal budget of the third annealing process can be smaller than the first thermal budget (e.g., a shorter time period or a lower temperature), or even smaller than the second thermal budget, so as to have a smaller impact on the first dipole dopant in the first doped gate dielectric layer 112 and the second doped gate dielectric layer 118. When the thermal diffusivity of the second dipole dopant is greater than that of the first dipole dopant, a sufficient amount of the second dipole dopant can diffuse into the first gate dielectric layer 104 to form the third doped gate dielectric layer 126. In some embodiments, the third doped gate dielectric layer 126 has 1E12 atoms / cm². 3 Up to 1E16 atoms / cm 3 The average atomic concentration of the second dipole dopant. After the third annealing process, the distances D2 and D3 can be reduced, and the distance D2 can still be less than the distance D3 because the first dipole dopant in the first doped gate dielectric layer 112 has been annealed more times than the first dipole dopant in the second doped gate dielectric layer 118.

[0071] According to some embodiments, after applying the third annealing process, the remaining portion of the third dipole layer 120 in the third region 50C is removed. The third dipole layer 120 can be removed by a suitable etching method, such as a wet etching process that etches the third dipole layer 120 at a faster rate than the first doped gate dielectric layer 112 in the first region 50A and the second doped gate dielectric layer 118 in the second region 50B.

[0072] It should be understood that although the first, second, and third doping cycles are executed sequentially in the above embodiments, the order of the first, second, and third doping cycles is not limited thereto, as each of the first, second, and third doping cycles can be executed and controlled independently. For example, when the dipole dopant is some heavy atoms, the order of executing the first, second, and third doping cycles can be changed in any way, as these heavy atoms may have low thermal diffusivity and not be thermally sensitive. In such an embodiment, the first doping cycle may be executed after the second or third doping cycle. Furthermore, although only three doping cycles are shown in the above embodiments, more doping cycles can be executed to dope other dipole dopant into the doped region or other regions.

[0073] In some embodiments, a second gate dielectric layer (not shown) is formed over the first doped gate dielectric layer 112, the second doped gate dielectric layer 118, and the third doped gate dielectric layer 126. The second gate dielectric layer may comprise the same high-k material as the first gate dielectric layer 104, which may be free of dipole dopants. The second gate dielectric layer is an undoped gate dielectric layer, for example, free of both the first and second dipole dopants. In some embodiments, the second gate dielectric layer has a thickness similar to that of the first gate dielectric layer. The first doped gate dielectric layer 112, the second doped gate dielectric layer 118, the third doped gate dielectric layer 126, and the second gate dielectric layer (if present) may be collectively referred to as gate dielectric layer 142 (see [link to documentation]). Figure 1 In some embodiments, the second gate dielectric layer may increase the capacitance equivalent thickness (CET) of the gate dielectric layer 142.

[0074] Figures 28A-29B The formation of gate electrodes 153A-153C is shown. Gate electrodes 153A-153C may each include a conductive layer and a filling layer. For example, in... Figure 28A and Figure 28BIn this process, a conductive layer 150 is deposited over the first doped gate dielectric layer 112, the second doped gate dielectric layer 118, and the third doped gate dielectric layer 126 and along the first recess 86. In some embodiments, the conductive layer 150 comprises TiN, TiAlN, TiAlC, TaN, or combinations thereof. In some embodiments, the conductive layer 150 is a single layer, such as a single TiN layer. In some embodiments, the conductive layer 150 is a composite layer, such as a TiN / TaN bilayer structure. Because the threshold voltage of the gate structure in the first region 50A, the second region 50B, and the third region 50C can be tuned by a dipole dopant, the conductive layer 150 can have a uniform thickness in the first region 50A, the second region 50B, and the third region 50C, rather than forming conductive layers of different materials and / or thicknesses separately in each of the different regions. In some embodiments, the conductive layer 150 can function as an adhesive layer, a work function layer, and / or a barrier layer.

[0075] exist Figure 29A and Figure 29B In this process, the fill layer 152 fills the remaining portions of the second recess 98 and the opening 99. The fill layer 152 may include tungsten, cobalt, ruthenium, aluminum, or combinations thereof. After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 142, the conductive layer 150, and the fill layer 152 (e.g., the portion above the top surface of the first ILD 96), thereby forming the conductive layer 150A and the fill layer 152A in the first region 50A, the conductive layer 150B and the fill layer 152B in the second region 50B, and the conductive layer 150C and the fill layer 152C in the third region 50C. A corresponding conductive layer among the conductive layers 150A-150C and a corresponding fill layer among the fill layers 152A-152C may be collectively referred to as gate electrode 153A, 153B, or 153C, respectively. Gate electrodes 153A, 153B, and 153C may be collectively referred to as gate electrode 153 (see, for example, see...). Figure 1 In some embodiments, the device in the first region 50A and the device in the third region 50C may have a threshold voltage difference greater than 300mV.

[0076] exist Figures 30A-30CIn this process, the gate electrode 153 and the gate dielectric layer 142 (e.g., a first doped gate dielectric layer 112, a second doped gate dielectric layer 118, and a third doped gate dielectric layer 126) are recessed, such that a recess is formed directly above the gate electrode 153 and the gate dielectric layer 142 and between opposing portions of the first spacer 81. A gate mask 156 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recess, followed by a planarization process to remove excess dielectric material extending over the first ILD 96. A gate contact (e.g., contact 172, referred to below) is subsequently formed. Figures 32A-32B (Discussion) Penetrates the gate mask 156 to contact the top surface of the recessed gate electrode 153.

[0077] like Figures 30A-30C As further shown, the second ILD 160 is deposited over the first ILD 96 and the gate mask 156. In some embodiments, the second ILD 160 is a flowable film formed by FCVD. In some embodiments, the second ILD 160 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0078] exist Figures 31A-31C In this process, the second ILD 160, the first ILD 96, CESL 94, and the gate mask 156 are etched to form a third recess 162 that exposes the surfaces of the epitaxial source / drain regions 92 and / or the gate electrode 153. The third recess 162 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 162 can be etched through the second ILD 160 and the first ILD 96 using a first etching process; it can be etched through the gate mask 156 using a second etching process; and then it can be etched through the CESL 94 using a third etching process. A mask (e.g., a photoresist) can be formed and patterned over the second ILD 160 to shield portions of the second ILD 160 from the first and second etching processes. In some embodiments, the etching process may over-etch, so that the third recess 162 extends into the epitaxial source / drain region 92 and / or gate electrode 153, and the bottom of the third recess 162 may be flush with the epitaxial source / drain region 92 and / or gate electrode 153 (e.g., at the same level, or at the same distance from the substrate), or lower than the epitaxial source / drain region 92 and / or gate electrode 153 (e.g., closer to the substrate). Although Figure 31BThe third recess 162 is shown to expose the epitaxial source / drain region 92 and the gate electrode 153 in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and the gate electrode 153 may be exposed in different cross sections, thereby reducing the risk of short circuits in subsequently formed contacts. After forming the third recess 162, a silicide region 164 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 164 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 over the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, and then performing a thermal annealing process to form the silicide region 164. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 164 is referred to as a silicide region, the silicide region 164 may also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicide and germanide). In one embodiment, the silicide region 164 comprises TiSi and has a thickness in the range of about 2 nm to about 10 nm.

[0079] Next, in Figures 32A-32C In this embodiment, contacts 170 and 172 (also referred to as contact plugs) are formed in the third recess 162. Contacts 170 and 172 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 170 and 172 each include a barrier layer and a conductive material, and are electrically coupled to underlying conductive features (e.g., gate electrode 153 and / or silicide region 164 in the illustrated embodiment). Contact 172 is electrically coupled to gate electrode 153 (e.g., filler layer 152 and conductive layer 150), and contact 172 may be referred to as a gate contact; contact 170 is electrically coupled to silicide region 164, and contact 170 may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 160.

[0080] Figures 33A to 35B A cross-sectional view of an intermediate stage in the fabrication of a nanoFET 20 according to some embodiments is shown. The fabrication of the nanoFET 20 is similar to that of the nanoFET 10, wherein the same reference numerals denote the same elements. For example, as Figures 33A-35B The process assumptions for manufacturing the nanoFET 20 shown are as follows. Figures 2 to 27B The process shown was performed first. Therefore, refer to the above. Figures 2 to 27BAfter the discussion, the process can proceed to... Figure 33A and Figure 33B .

[0081] In some embodiments, one or more dipole doping cycles may be performed on at least one of the first region 50A, the second region 50B, and the third region 50C, or other regions. Any number of additional doping cycles may be performed on at least one of the first region 50A, the second region 50B, and the third region 50C, and are not limited by the narrow space between the nanostructures 55, since each dipole layer is removed in each dipole cycle. For example, refer to... Figures 33A-35B According to some embodiments, a third dipole dopant, different from the first and second dipole dopants, can be doped into the first doped gate dielectric layer 112 to fine-tune the gate threshold voltage of the gate structure in the first region 50A. The third dipole dopant can be an n-type or p-type dipole dopant. A fourth doping cycle can include forming a fourth dipole layer 190 over the first doped gate dielectric layer 112, the second doped gate dielectric layer 118, and the third doped gate dielectric layer 126. The fourth dipole layer 190 can be patterned using a patterning mask 192. A fourth annealing process can be performed to diffuse the third dipole dopant into the first doped gate dielectric layer 112. A low concentration of the third dipole dopant in the first doped gate dielectric layer 112 can be sufficient to help fine-tune the operating characteristics. The third dipole layer 120 can have a thin thickness, for example, thinner than the first dipole layer 106, or even thinner than the second dipole layer 114. The heat budget for the fourth annealing process can be less than that for the first annealing process, or even less than that for the second and third annealing processes. Next, it can be determined based on... Figures 28A to 32C The fabrication process is similar to that described above. The resulting structure of the nano-FET 20 can be similar to... Figures 32A-32C The nano FET 10 shown has a first doped gate dielectric layer 112' doped with a first dipole dopant and a third dipole dopant.

[0082] According to embodiments of this disclosure, a semiconductor device including a gate dielectric layer doped with a dipole dopant material and a method for forming the semiconductor device are provided. The dipole dopant material doped in the gate dielectric layer can adjust the threshold voltage of the gate structure including the gate dielectric layer. In some embodiments, one or more dipole dopant materials are doped into the gate dielectric layer through one or more separate doping cycles, and each of the doping cycles includes a separate dipole layer formation and a separate annealing process. Therefore, the concentration and concentration distribution of each dipole dopant material in one or more gate dielectric layers can be controlled individually, for example by controlling the thickness of the dipole layer or the temperature and / or time period of the annealing process in each doping cycle. The method according to some embodiments can also provide doping of two or more dipole dopant materials in a single gate dielectric layer, wherein each of the dipole dopant materials has a well-controlled concentration and concentration distribution to provide a finely tuned threshold voltage.

[0083] In one embodiment, a semiconductor device includes: a first channel region in a first device region, wherein the first device region has a first conductivity type; a second channel region in a second device region, wherein the second device region has the first conductivity type; a third channel region in a third device region, wherein the third device region has a second conductivity type different from the first conductivity type; a first doped gate dielectric layer disposed over the first channel region, wherein the first doped gate dielectric layer includes a high-k material doped with a first dipole dopant, wherein the first doped gate dielectric layer has a first concentration of the first dipole dopant, wherein the first doped gate dielectric layer has a first concentration distribution of the first dipole dopant, wherein the first concentration distribution has a first distance from a first concentration peak of the first dipole dopant to the first channel region, wherein the first dipole dopant is an n-type dipole dopant; and a second doped gate dielectric layer disposed over the second channel region, wherein the second doped gate dielectric layer includes a high-k material doped with the first dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant, wherein the second doped gate dielectric layer has a second concentration distribution of the first dipole dopant, wherein the second concentration distribution has a second distance from a second concentration peak of the first dipole dopant to the second channel region, wherein the first concentration is greater than the second concentration, and wherein the first distance is less than the second distance; a third doped gate dielectric layer is disposed above the third channel region, wherein the third doped gate dielectric layer includes a high-k material doped with a second dipole dopant different from the first dipole dopant; a first gate electrode is located above the first doped gate dielectric layer, wherein the first gate electrode includes a first conductive layer and a first filling layer located above the first conductive layer; a second gate electrode is located above the second doped gate dielectric layer; and a third gate electrode is located above the third doped gate dielectric layer, wherein the third gate electrode includes a second conductive layer and a second filling layer disposed above the second conductive layer, wherein the first filling layer and the second filling layer have the same width. In one embodiment, the first conductive layer is a single layer, wherein the first conductive layer is in solid contact with the first fill layer and the first doped gate dielectric layer; wherein the second conductive layer is a single layer, wherein the second conductive layer is in solid contact with the second fill layer and the third doped gate dielectric layer. In one embodiment, the first dipole dopant comprises La, Mg, Sr, or Y, and the second dipole dopant comprises Ti, Al, Ga, In, Nb, or Zn. In one embodiment, the first dipole dopant has a lower thermal diffusivity than the second dipole dopant.In one embodiment, the semiconductor device further includes: a first undoped gate dielectric layer located between the first doped gate dielectric layer and the first gate electrode; a second undoped gate dielectric layer located between the second doped gate dielectric layer and the second gate electrode; and a third undoped gate dielectric layer located between the third doped gate dielectric layer and the third gate electrode. In one embodiment, the first doped gate dielectric layer further includes a third dipole dopant different from the first dipole dopant and the second dipole dopant.

[0084] In one embodiment, a method of manufacturing a semiconductor device includes: forming a first gate dielectric layer over a first channel region in a first device region, a second channel region in a second device region, and a third channel region in a third device region, wherein the first device region and the second device region have a first conductivity type, and wherein the third device region has a second conductivity type different from the first conductivity type; forming a first dipole layer including a first dipole dopant over the first gate dielectric layer in the first device region; performing a first annealing process to convert the first gate dielectric layer in the first device region into a first doped gate dielectric layer including the first dipole dopant, wherein the first annealing process has a first thermal budget; removing the remaining portion of the first dipole layer; and after removing the remaining portion of the first dipole layer, forming a second dipole layer including the first dipole dopant over the first gate dielectric layer in the second device region, wherein the second dipole layer... The thickness is thinner than the thickness of the first dipole layer; a second annealing process is performed to convert the first gate dielectric layer in the second device region into a second doped gate dielectric layer including the first dipole dopant, wherein the second annealing process has a second thermal budget different from the first thermal budget; the remaining portion of the second dipole layer is removed; the first gate dielectric layer in the third device region is converted into a third doped gate dielectric layer, wherein the third doped gate dielectric layer includes a second dipole dopant different from the first dipole dopant; and a first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode includes a conductive layer and a fill layer filling the conductive layer, wherein each of the fill layers has a substantially the same width. In one embodiment, the first annealing process and the second annealing process are different. In one embodiment, the second annealing process has the same temperature as the first annealing process and has a shorter cycle than the first annealing process. In one embodiment, the second annealing process has the same time period as the first annealing process but at a lower temperature. In one embodiment, the second dipole dopant has a greater thermal diffusivity than the first dipole dopant. In one embodiment, the method further includes doping a third dipole dopant into the first gate dielectric layer before forming the first gate electrode, the second gate electrode, and the third gate electrode. In one embodiment, the first dipole layer is an oxide or nitride of the first dipole dopant.

[0085] In one embodiment, a method of manufacturing a semiconductor device includes: forming a first gate dielectric layer over a first channel region in a first p-type region, over a second channel region in a second p-type region, and over a third channel region in an n-type region; performing a first doping cycle to convert the first gate dielectric layer in the first p-type region into a first doped gate dielectric layer, wherein the first doping cycle includes: forming a first dipole layer over the first gate dielectric layer in the first p-type region, wherein the first dipole layer includes a first dipole dopant and has a first thickness; and performing a first annealing; after the first doping cycle, performing a second doping cycle to convert the first gate dielectric layer in the second p-type region into a second doped gate dielectric layer, wherein... The second doping cycle includes: forming a second dipole layer over a first gate dielectric layer in the second p-type region, wherein the second dipole layer includes the first dipole dopant and has a second thickness different from the first thickness; and performing a second annealing; performing a third doping cycle to convert the first gate dielectric layer in the n-type region into a third doped gate dielectric layer, wherein the third doping cycle includes: forming a third dipole layer, the third dipole layer including a second dipole dopant different from the first dipole dopant; and performing a third annealing; and forming a first gate electrode over the first doped gate dielectric layer, forming a second gate electrode over the second doped gate dielectric layer, and forming a third gate electrode over the third doped gate dielectric layer. In one embodiment, the first dipole dopant has a lower thermal diffusivity than the second dipole dopant. In one embodiment, the method further includes: forming a second gate dielectric layer over the first doped gate dielectric layer, the second doped gate dielectric layer, and the third doped gate dielectric layer before forming the first gate electrode, the second gate electrode, and the third gate electrode, wherein the second gate dielectric layer is substantially free of the first dipole dopant and the second dipole dopant, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode is in solid contact with the second gate dielectric layer. In one embodiment, the first annealing and the second annealing have the same temperature and the same time period. In one embodiment, the first annealing is an immersion annealing or a spike annealing. In one embodiment, the thermal budget of the second annealing is less than the thermal budget of the first annealing. In one embodiment, the method further includes: performing a fourth doping cycle to dope a third dipole dopant into the first doped gate dielectric layer, wherein the third dipole dopant is different from the first dipole dopant and the second dipole dopant.

[0086] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0087] Example

[0088] Example 1. A semiconductor device, comprising:

[0089] A first channel region in a first device region, wherein the first device region has a first conductivity type;

[0090] The second channel region in the second device region has the first conductivity type;

[0091] The third channel region in the third device region, wherein the third device region has a second conductivity type different from the first conductivity type;

[0092] A first doped gate dielectric layer is disposed above the first channel region, wherein the first doped gate dielectric layer comprises a high-k material doped with a first dipole dopant, wherein the first doped gate dielectric layer has a first concentration of the first dipole dopant, wherein the first doped gate dielectric layer has a first concentration distribution of the first dipole dopant, wherein the first concentration distribution has a first distance from a first concentration peak of the first dipole dopant to the first channel region, wherein the first dipole dopant is an n-type dipole dopant;

[0093] A second doped gate dielectric layer is disposed above the second channel region, wherein the second doped gate dielectric layer includes a high-k material doped with the first dipole dopant, wherein the second doped gate dielectric layer has a second concentration of the first dipole dopant, wherein the second doped gate dielectric layer has a second concentration distribution of the first dipole dopant, wherein the second concentration distribution has a second distance from a second concentration peak of the first dipole dopant to the second channel region, wherein the first concentration is greater than the second concentration, and wherein the first distance is less than the second distance;

[0094] A third doped gate dielectric layer is disposed above the third channel region, wherein the third doped gate dielectric layer includes a high-k material doped with a second dipole dopant that is different from the first dipole dopant.

[0095] A first gate electrode is located above the first doped gate dielectric layer, wherein the first gate electrode includes a first conductive layer and a first filling layer located above the first conductive layer;

[0096] The second gate electrode is located above the second doped gate dielectric layer; and

[0097] The third gate electrode is located above the third doped gate dielectric layer, wherein the third gate electrode includes a second conductive layer and a second filling layer disposed above the second conductive layer, wherein the first filling layer and the second filling layer have the same width.

[0098] Example 2. The semiconductor device according to Example 1, wherein the first conductive layer is a single layer, wherein the first conductive layer is in solid contact with the first fill layer and the first doped gate dielectric layer, wherein the second conductive layer is a single layer, wherein the second conductive layer is in solid contact with the second fill layer and the third doped gate dielectric layer.

[0099] Example 3. The semiconductor device according to Example 1, wherein the first dipole dopant comprises La, Mg, Sr or Y, and the second dipole dopant comprises Ti, Al, Ga, In, Nb or Zn.

[0100] Example 4. The semiconductor device according to Example 1, wherein the first dipole dopant has a smaller thermal diffusivity than the second dipole dopant.

[0101] Example 5. The semiconductor device according to Example 1 further includes:

[0102] A first undoped gate dielectric layer is located between the first doped gate dielectric layer and the first gate electrode;

[0103] A second undoped gate dielectric layer is located between the second doped gate dielectric layer and the second gate electrode; and

[0104] The third undoped gate dielectric layer is located between the third doped gate dielectric layer and the third gate electrode.

[0105] Example 6. The semiconductor device according to Example 1, wherein the first doped gate dielectric layer further includes a third dipole dopant that is different from the first dipole dopant and the second dipole dopant.

[0106] Example 7. A method for manufacturing a semiconductor device, the method comprising:

[0107] A first gate dielectric layer is formed over a first channel region in a first device region, a second channel region in a second device region, and a third channel region in a third device region, wherein the first device region and the second device region have a first conductivity type, and wherein the third device region has a second conductivity type different from the first conductivity type.

[0108] A first dipole layer comprising a first dipole dopant is formed on the first gate dielectric layer in the first device region;

[0109] A first annealing process is performed to convert a first gate dielectric layer in the first device region into a first doped gate dielectric layer including the first dipole dopant, wherein the first annealing process has a first thermal budget;

[0110] Remove the remaining portion of the first dipole layer;

[0111] After removing the remaining portion of the first dipole layer, a second dipole layer comprising the first dipole dopant is formed on the first gate dielectric layer in the second device region, wherein the thickness of the second dipole layer is thinner than the thickness of the first dipole layer.

[0112] A second annealing process is performed to convert the first gate dielectric layer in the second device region into a second doped gate dielectric layer including the first dipole dopant, wherein the second annealing process has a second thermal budget that is different from the first thermal budget;

[0113] Remove the remaining portion of the second dipole layer;

[0114] The first gate dielectric layer in the third device region is converted into a third doped gate dielectric layer, wherein the third doped gate dielectric layer includes a second dipole dopant different from the first dipole dopant; and

[0115] A first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode includes a conductive layer and a fill layer filling the conductive layer, wherein each of the fill layers has a substantially the same width.

[0116] Example 8. The method according to Example 7, wherein the first annealing process and the second annealing process are different.

[0117] Example 9. The method according to Example 7, wherein the second annealing process has the same temperature as the first annealing process and has a shorter cycle than the first annealing process.

[0118] Example 10. The method according to Example 7, wherein the second annealing process has the same time period as the first annealing process and has a lower temperature than the first annealing process.

[0119] Example 11. The method according to Example 7, wherein the second dipole dopant has a thermal diffusivity greater than that of the first dipole dopant.

[0120] Example 12. The method according to Example 7 further includes: doping a third dipole dopant into the first gate dielectric layer before forming the first gate electrode, the second gate electrode and the third gate electrode.

[0121] Example 13. The method according to Example 7, wherein the first dipole layer is an oxide or nitride of the first dipole dopant.

[0122] Example 14. A method of manufacturing a semiconductor device, the method comprising:

[0123] A first gate dielectric layer is formed over a first channel region in a first p-type region, over a second channel region in a second p-type region, and over a third channel region in an n-type region;

[0124] Performing a first doping cycle to convert the first gate dielectric layer in the first p-type region into a first doped gate dielectric layer, wherein the first doping cycle includes:

[0125] A first dipole layer is formed on a first gate dielectric layer in the first p-type region, wherein the first dipole layer includes a first dipole dopant and has a first thickness; and

[0126] Perform the first annealing;

[0127] After the first doping cycle, a second doping cycle is performed to convert the first gate dielectric layer in the second p-type region into a second doped gate dielectric layer, wherein the second doping cycle includes:

[0128] A second dipole layer is formed on the first gate dielectric layer in the second p-type region, wherein the second dipole layer includes the first dipole dopant and has a second thickness different from the first thickness; and

[0129] Perform a second annealing;

[0130] Perform a third doping cycle to convert the first gate dielectric layer in the n-type region into a third-doped gate dielectric layer, wherein the third doping cycle includes:

[0131] A third dipole layer is formed, the third dipole layer comprising a second dipole dopant different from the first dipole dopant; and

[0132] Perform third annealing; and

[0133] A first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer.

[0134] Example 15. The method according to Example 14, wherein the first dipole dopant has a lower thermal diffusivity than the second dipole dopant.

[0135] Example 16. The method according to Example 14 further includes: forming a second gate dielectric layer over the first doped gate dielectric layer, the second doped gate dielectric layer, and the third doped gate dielectric layer before forming the first gate electrode, the second gate electrode, and the third gate electrode, wherein the second gate dielectric layer is substantially free of the first dipole dopant and the second dipole dopant, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode is in solid contact with the second gate dielectric layer.

[0136] Example 17. The method according to Example 14, wherein the first annealing and the second annealing have the same temperature and the same time period.

[0137] Example 18. The method according to Example 14, wherein the first annealing is immersion annealing or spike annealing.

[0138] Example 19. The method according to Example 14, wherein the heat budget of the second annealing is less than the heat budget of the first annealing.

[0139] Example 20. The method according to Example 14 further includes: performing a fourth doping cycle to dope a third dipole dopant into the first doped gate dielectric layer, wherein the third dipole dopant is different from the first dipole dopant and the second dipole dopant.

Claims

1. A semiconductor device, comprising: A first channel region in a first device region, wherein the first device region has a first conductivity type; The second channel region in the second device region has the first conductivity type; The third channel region in the third device region, wherein the third device region has a second conductivity type different from the first conductivity type; A first doped gate dielectric layer is disposed above the first channel region, wherein the first doped gate dielectric layer comprises a high-k material doped with a first dipole dopant, wherein the first doped gate dielectric layer has a first concentration of the first dipole dopant, wherein the first doped gate dielectric layer has a first concentration distribution of the first dipole dopant, wherein the first concentration distribution has a first distance from a first concentration peak of the first dipole dopant to the first channel region, wherein the first dipole dopant is an n-type dipole dopant; A second doped gate dielectric layer is disposed above the second channel region, wherein the second doped gate dielectric layer includes a high-k material doped with the first dipole dopant, wherein the second doped gate dielectric layer has a second concentration of the first dipole dopant, wherein the second doped gate dielectric layer has a second concentration distribution of the first dipole dopant, wherein the second concentration distribution has a second distance from a second concentration peak of the first dipole dopant to the second channel region, wherein the first concentration is greater than the second concentration, and wherein the first distance is less than the second distance; A third doped gate dielectric layer is disposed above the third channel region, wherein the third doped gate dielectric layer includes a high-k material doped with a second dipole dopant that is different from the first dipole dopant. A first gate electrode is located above the first doped gate dielectric layer, wherein the first gate electrode includes a first conductive layer and a first filling layer located above the first conductive layer; The second gate electrode is located above the second doped gate dielectric layer; and The third gate electrode is located above the third doped gate dielectric layer, wherein the third gate electrode includes a second conductive layer and a second filling layer disposed above the second conductive layer, wherein the first filling layer and the second filling layer have the same width.

2. The semiconductor device according to claim 1, wherein, The first conductive layer is a single layer, wherein the first conductive layer is in solid contact with the first filling layer and the first doped gate dielectric layer, wherein the second conductive layer is a single layer, wherein the second conductive layer is in solid contact with the second filling layer and the third doped gate dielectric layer.

3. The semiconductor device according to claim 1, wherein, The first dipole dopant includes La, Mg, Sr or Y, and the second dipole dopant includes Ti, Al, Ga, In, Nb or Zn.

4. The semiconductor device according to claim 1, wherein, The first dipole dopant has a smaller thermal diffusivity than the second dipole dopant.

5. The semiconductor device according to claim 1, further comprising: A first undoped gate dielectric layer is located between the first doped gate dielectric layer and the first gate electrode; The second undoped gate dielectric layer is located between the second doped gate dielectric layer and the second gate electrode; as well as The third undoped gate dielectric layer is located between the third doped gate dielectric layer and the third gate electrode.

6. The semiconductor device according to claim 1, wherein, The first doped gate dielectric layer further includes a third dipole dopant, which is different from the first dipole dopant and the second dipole dopant.

7. A method for manufacturing a semiconductor device, the method comprising: A first gate dielectric layer is formed over a first channel region in a first device region, a second channel region in a second device region, and a third channel region in a third device region, wherein the first device region and the second device region have a first conductivity type, and wherein the third device region has a second conductivity type different from the first conductivity type. A first dipole layer comprising a first dipole dopant is formed on the first gate dielectric layer in the first device region; A first annealing process is performed to convert a first gate dielectric layer in the first device region into a first doped gate dielectric layer including the first dipole dopant, wherein the first annealing process has a first thermal budget; Remove the remaining portion of the first dipole layer; After removing the remaining portion of the first dipole layer, a second dipole layer comprising the first dipole dopant is formed on the first gate dielectric layer in the second device region, wherein the thickness of the second dipole layer is thinner than the thickness of the first dipole layer. A second annealing process is performed to convert the first gate dielectric layer in the second device region into a second doped gate dielectric layer including the first dipole dopant, wherein the second annealing process has a second thermal budget that is different from the first thermal budget; Remove the remaining portion of the second dipole layer; The first gate dielectric layer in the third device region is converted into a third doped gate dielectric layer, wherein the third doped gate dielectric layer includes a second dipole dopant different from the first dipole dopant; and A first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer, wherein each of the first gate electrode, the second gate electrode, and the third gate electrode includes a conductive layer and a fill layer filling the conductive layer, wherein each of the fill layers has a substantially the same width.

8. The method according to claim 7, wherein, The first annealing process and the second annealing process are different.

9. The method according to claim 7, wherein, The second annealing process has the same temperature as the first annealing process but has a shorter cycle time than the first annealing process.

10. The method according to claim 7, wherein, The second annealing process has the same time period as the first annealing process but at a lower temperature.

11. The method according to claim 7, wherein, The second dipole dopant has a higher thermal diffusivity than the first dipole dopant.

12. The method of claim 7, further comprising: Before forming the first gate electrode, the second gate electrode and the third gate electrode, a third dipole dopant is doped into the first gate dielectric layer.

13. The method according to claim 7, wherein, The first dipole layer is an oxide or nitride of the first dipole dopant.

14. A method for manufacturing a semiconductor device, the method comprising: A first gate dielectric layer is formed over a first channel region in a first p-type region, over a second channel region in a second p-type region, and over a third channel region in an n-type region; Performing a first doping cycle to convert the first gate dielectric layer in the first p-type region into a first doped gate dielectric layer, wherein the first doping cycle includes: A first dipole layer is formed on a first gate dielectric layer in the first p-type region, wherein the first dipole layer includes a first dipole dopant and has a first thickness; and Perform the first annealing; After the first doping cycle, a second doping cycle is performed to convert the first gate dielectric layer in the second p-type region into a second doped gate dielectric layer, wherein the second doping cycle includes: A second dipole layer is formed on the first gate dielectric layer in the second p-type region, wherein the second dipole layer includes the first dipole dopant and has a second thickness different from the first thickness; and Perform a second annealing; Perform a third doping cycle to convert the first gate dielectric layer in the n-type region into a third-doped gate dielectric layer, wherein the third doping cycle includes: A third dipole layer is formed, the third dipole layer comprising a second dipole dopant different from the first dipole dopant; and Perform third annealing; and A first gate electrode is formed on the first doped gate dielectric layer, a second gate electrode is formed on the second doped gate dielectric layer, and a third gate electrode is formed on the third doped gate dielectric layer.

15. The method according to claim 14, wherein, The first dipole dopant has a lower thermal diffusivity than the second dipole dopant.

16. The method of claim 14, further comprising: Before forming the first gate electrode, the second gate electrode, and the third gate electrode, a second gate dielectric layer is formed on the first doped gate dielectric layer, the second doped gate dielectric layer, and the third doped gate dielectric layer, wherein the second gate dielectric layer is substantially free of the first dipole dopant and the second dipole dopant, and wherein each of the first gate electrode, the second gate electrode, and the third gate electrode is in solid contact with the second gate dielectric layer.

17. The method according to claim 14, wherein, The first annealing and the second annealing have the same temperature and the same time period.

18. The method according to claim 14, wherein, The first annealing is either immersion annealing or spike annealing.

19. The method of claim 14, wherein, The heat budget for the second annealing is less than that for the first annealing.

20. The method of claim 14, further comprising: A fourth doping cycle is performed to dope a third dipole dopant into the first doped gate dielectric layer, wherein the third dipole dopant is different from the first dipole dopant and the second dipole dopant.

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