A method for ROM compression of DDS and application

Abstract

The application discloses a ROM compression method and application for DDS, and belongs to the technical field of frequency synthesis; two ROM tables are adopted to compress and store a sine wave signal; wherein the first ROM table takes a phase quantization value as an addressing address and an amplitude quantization value as storage data, so as to realize phase-amplitude conversion; the second ROM table takes the amplitude quantization value as the addressing address and the phase quantization value as the storage data, so as to realize amplitude-phase conversion; the double-rom-table compression storage realized by introducing a flag bit reduces the zero value stored in the traditional non-phase-truncated ROM table, and can reduce the occupied ROM resource. In addition, the application adopts multiple phase steps to non-uniformly divide the phase interval of the sine wave signal (0, pi / 2), so as to obtain multiple sub-phase intervals, so that each sub-phase interval only includes one critical phase point, the depth of the first ROM table can be further compressed, the ROM table is losslessly compressed under the premise of not increasing too much circuit complexity, and the required ROM capacity is further reduced.

Description

Technical Field

[0001] This invention belongs to the field of frequency synthesis technology, and more specifically, relates to a ROM compression method and application for DDS. Background Technology

[0002] Direct Digital Frequency Synthesis (DDS or DDFS) synthesizes frequencies based on the concept of phase, offering advantages such as high frequency resolution, frequency agility, and continuous phase during frequency hopping. Traditional DDS, to achieve extremely high frequency resolution, places high demands on the depth of the phase-amplitude conversion lookup table (ROM) corresponding to the bit width of the phase accumulator. However, large-capacity ROMs introduce problems related to power consumption, cost, and speed. Therefore, in practical designs, the higher bits of the phase accumulator are often truncated as the addressing signal for the ROM table. This leads to phase truncation errors, introducing spurious components into the output spectrum and degrading spectral purity.

[0003] To address the phase truncation problem of traditional DDS (Distributed Dynamic Signal Processor), existing technologies propose a phase-truncation-free structure. This structure uses a special ROM table and comparison circuit to compare the discarded phase with specific values ​​to correct the output amplitude, thus eliminating spurious signals caused by phase truncation. In contrast, the N-bit phase accumulator of a traditional DDS divides the phase (0, π / 2) of a 1 / 4-cycle sine wave into 2... N-2 The ROM table is divided into two equal parts, corresponding to a total of 2 addressable addresses. N-2 Existing technology corresponds to the phase (0, π / 2) of a 1 / 4-cycle sine wave signal. N-2 The phase interval is redivided into smaller, more spaced intervals, ensuring that each interval contains at most one critical phase point, resulting in a maximum interval Δ = 2. N-L-2 This reduces the total number of minimum addressable addresses in the ROM table to 2. L The ROM table stores two parts at each address: the first part is the L-1 bits of waveform amplitude quantization value, and the second part is the lower NL-2 bits of the N-2 bits of the critical phase quantization value corresponding to the amplitude quantization value. Therefore, the required ROM table size is 2. L ×(N-3), where N represents the bit width of the phase accumulator and L represents the bit width of the DAC.

[0004] However, the ROM table in the above method stores a lot of zero values, and many values ​​are repeated, meaning this storage method has significant redundancy. Therefore, it is necessary to propose a compression method that can reduce redundancy and save ROM resources. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a ROM compression method and application for DDS, the purpose of which is to reduce the ROM resources occupied by phase-truncation-free DDS.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a ROM compression method for DDS, comprising: compressing and storing a sine wave signal using a dual ROM table, specifically including:

[0007] The phase interval of the sinusoidal signal (0, π / 2) is divided into multiple sub-phase intervals. The upper bound of each sub-phase interval is quantized and encoded. The resulting phase quantization value is used as the address of the first ROM table corresponding to the sub-phase interval. The flag bit of each sub-phase interval and the waveform amplitude quantization value corresponding to its upper bound are sequentially stored at the address of the corresponding first ROM table.

[0008] Divide the amplitude interval corresponding to the phase interval of the sinusoidal signal (0, π / 2) into equal intervals to obtain 2. L-1 Each sub-amplitude interval is divided into several sub-amplitude intervals, and the upper bound of each sub-amplitude interval is quantized and encoded. The resulting amplitude quantization value is used as the address of the second ROM table corresponding to the sub-amplitude interval. The phase point corresponding to the upper bound of each sub-amplitude interval is recorded as the critical phase point, and the lower N-2-L bits of the N-2-bit phase quantization value at the critical phase point are stored in the address of the corresponding second ROM table.

[0009] The flag bit indicates whether the sub-phase interval contains a critical phase point; L is the bit width of the digital-to-analog converter used in the DDS; and N is the bit width of the phase accumulator used in the DDS.

[0010] More preferably, when the sub-phase interval contains a critical phase point, the flag bit of the sub-phase interval is 1; when the sub-phase interval does not contain a critical phase point, the flag bit of the sub-phase interval is 0.

[0011] More preferably, the phase interval of the sinusoidal signal (0, π / 2) is uniformly divided.

[0012] More preferably, the phase interval of the sinusoidal signal (0, π / 2) is non-uniformly divided to obtain multiple sub-phase intervals.

[0013] More preferably, the phase interval of the sinusoidal signal (0, π / 2) is non-uniformly divided using multiple phase steps to obtain multiple sub-phase intervals, such that each sub-phase interval includes only one critical phase point; wherein, when switching phase steps, the switching point is determined based on the slope at the switching point being equal to the ratio of the size of the aforementioned sub-amplitude interval to the next phase step; the ratio of the next phase step to the previous phase step is 2; the first phase step...

[0014] Secondly, this invention provides a direct digital frequency synthesis method for transforming a sinusoidal signal based on an input frequency control word, specifically including the following steps:

[0015] S1. Input the frequency control word K into the N-bit phase accumulator to obtain the N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as the sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as the truncated phase quantization value, and the middle L bits as the address of the first ROM table;

[0016] S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4.

[0017] S3. Use the lower L-1 bits of the content stored in the address address of the first ROM table as the address address of the second ROM table, read the content stored in the second ROM table, compare it with the truncated phase quantization value, and if the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address address of the first ROM table by 1.

[0018] S4. Based on the sign flag bit, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted to obtain the amplitude quantization value of L bits. Then, a digital-to-analog converter is used to perform digital-to-analog conversion to transform the sine wave signal.

[0019] The sine wave signal is stored in the first ROM table and the second ROM table using the ROM compression method provided in the first aspect.

[0020] Thirdly, the present invention provides a direct digital frequency synthesis system, comprising: a controller, a phase accumulator, and a digital-to-analog converter;

[0021] The controller is used to execute the direct digital frequency synthesis method provided in the second aspect of the present invention.

[0022] Fourthly, when the phase interval (0, π / 2) of a sinusoidal signal is non-uniformly divided using multiple phase steps, this invention provides a direct digital frequency synthesis method for transforming a sinusoidal signal based on an input frequency control word, comprising the following steps:

[0023] S1. Input the frequency control word K into the N-bit phase accumulator to obtain the N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as the sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as the truncated phase quantization value, and the middle L bits as the address to be corrected; compare the address to be corrected with the L-bit phase quantization value at each switching point to determine the phase step of the interval where the address to be corrected is located; subtract the L-bit phase quantization value at the switching point when switching to the phase step from the address to be corrected, divide the difference by the phase step and round up, add the rounded result to the number of sub-phase intervals under all phase steps smaller than the phase step, and obtain the corrected L-bit address as the address of the first ROM table;

[0024] S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4.

[0025] S3. Use the lower L-1 bits of the content stored in the address address of the first ROM table as the address address of the second ROM table, read the content stored in the second ROM table, compare it with the truncated phase quantization value, and if the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address address of the first ROM table by 1.

[0026] S4. Based on the sign flag bit, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted to obtain the amplitude quantization value of L bits. Then, a digital-to-analog converter is used to perform digital-to-analog conversion to transform the sine wave signal.

[0027] The sine wave signal is stored in the first ROM table and the second ROM table using the ROM compression method provided in the first aspect.

[0028] Fifthly, the present invention provides a direct digital frequency synthesis system, comprising: a controller, a phase accumulator, and a digital-to-analog converter;

[0029] The controller is used to execute the direct digital frequency synthesis method provided in the fourth aspect of the present invention.

[0030] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0031] 1. This invention provides a ROM compression method for DDS, employing a dual ROM table to compress and store a sinusoidal signal. The first ROM table uses phase quantization values ​​as address addresses and amplitude quantization values ​​as stored data to achieve phase-to-amplitude conversion. Conversely, the second ROM table uses amplitude quantization values ​​as address addresses and phase quantization values ​​as stored data to achieve amplitude-to-phase conversion. The dual ROM table compression storage, achieved by introducing flag bits, reduces the number of zero values ​​stored in traditional ROM tables without phase truncation, thus reducing the size of the first ROM table to 2. L ×L, the size of the second ROM table is 2 L-1 ×(N-2-L) can greatly reduce the ROM resources occupied by phase-truncation DDS.

[0032] 2. Furthermore, since the phase quantization point corresponding to the original amplitude quantization point divides the phase [0, π / 2) into non-uniform phase intervals and these intervals are sequentially increasing, the ROM compression method provided by this invention uses multiple phase steps to non-uniformly divide the phase interval of the sine wave signal (0, π / 2) to obtain multiple sub-phase intervals, so that each sub-phase interval includes only one critical phase point. Using multiple phase steps can divide the phase of the sine wave signal (0, π / 2) into fewer sub-phase intervals. The number of sub-phase intervals corresponds to the total number of addressing addresses of the first ROM table. Therefore, the depth of the first ROM table can be further compressed, and thus the ROM table can be losslessly compressed without increasing the circuit complexity too much, further reducing the required ROM capacity. Attached Figure Description

[0033] Figure 1 This is a flowchart of the direct digital frequency synthesis method provided in Embodiment 2 of the present invention;

[0034] Figure 2 This is a flowchart of the direct digital frequency synthesis method provided in Embodiment 4 of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0036] Example 1

[0037] A ROM compression method for DDS includes: compressing and storing a sine wave signal using a dual ROM table, specifically including:

[0038] The phase interval of the sinusoidal signal (0, π / 2) is divided into multiple sub-phase intervals. The upper bound of each sub-phase interval is quantized and encoded, and the resulting quantized phase value is used as the address of the first ROM table corresponding to that sub-phase interval. The flag bit of each sub-phase interval and the waveform amplitude quantization value corresponding to its upper bound are sequentially stored at the address of the corresponding first ROM table. Specifically, the number of sub-phase intervals is equal to the total number of addresses in the first ROM table. The output content corresponding to each address in the first ROM table consists of two parts: the first part is a flag bit (0 / 1) used to determine if the sub-phase interval contains a critical phase point, and the second part is the L-1 bits of waveform amplitude quantization value corresponding to the upper bound of each sub-phase interval.

[0039] Divide the amplitude interval corresponding to the phase interval of the sinusoidal signal (0, π / 2) into equal intervals to obtain 2. L-1 The system divides the system into sub-amplitude intervals and quantizes the upper bound of each sub-amplitude interval. The resulting amplitude quantization value is used as the address of the second ROM table corresponding to that sub-amplitude interval. The phase point corresponding to the upper bound of each sub-amplitude interval is recorded as a critical phase point, and the lower N-2-L bits of the N-2-bit phase quantization value at that critical phase point are stored at the address of the corresponding second ROM table. Specifically, the number of amplitude quantization values ​​is equal to the total number of addresses in the second ROM table.

[0040] Where L is the bit width of the digital-to-analog converter (DAC) used in the DDS; N is the bit width of the phase accumulator used in the DDS. The flag bit is used to indicate whether the sub-phase interval contains a critical phase point; in one optional implementation, when the sub-phase interval contains a critical phase point, the flag bit of the sub-phase interval is 1; when the sub-phase interval does not contain a critical phase point, the flag bit of the sub-phase interval is 0.

[0041] This invention employs dual ROM tables for waveform storage; wherein, the first ROM table ROM1 uses the phase quantization value as the address and the amplitude quantization value as the stored data to achieve phase-amplitude conversion; conversely, the second ROM table ROM2 uses the amplitude quantization value as the address and the phase quantization value as the stored data to achieve amplitude-phase conversion.

[0042] It should be noted that the phase interval of the sinusoidal signal (0, π / 2) can be divided uniformly or non-uniformly.

[0043] When uniformly dividing the phase interval of a sinusoidal signal (0, π / 2), one possible implementation is to use a step Δ = 2. N-L-2 The (0,π / 2) phase output is divided into equal intervals to achieve phase cutoff.

[0044] The principle behind this method of achieving phase-free truncation is as follows: Let 1 / 4 of a sine wave in the phase interval (0, π / 2) have 2... L-1 Amplitude quantization point A i Each amplitude quantization point corresponds to a phase quantization value E at an N-2 bit critical phase point. i If the phase (0, π / 2) is divided into equal parts by a step size Δ, and the Δ interval contains at most one E... i And address the corresponding amplitude quantization point A in the ROM table in units of Δ intervals. i When the interval Δ contains E i When, the phase E in the Δ interval n Corresponding amplitude quantization point A i-1 and A i The phase E within the Δ interval can be corrected simply by comparing the magnitudes. n This corresponds to the correct amplitude quantization value. When the Δ interval does not include E... i At that time, i.e., E i and E i+1 It contains multiple Δ intervals, and the phase E within each Δ interval n The corresponding amplitude quantization points are all A. i .

[0045] Specifically, the calculation process for the maximum step size that ensures each Δ interval contains at most one critical phase point is as follows:

[0046] Let the sine function be... Amplitude quantization step Δ A =1 / 2 L-1 , using A i Indicates the amplitude quantization point:

[0047] A0 = 0 and

[0048] Amplitude quantization point A i The corresponding phase value is

[0049]

[0050] Phase quantization step is E i The phase quantization value at the critical phase point, i.e., the phase value. The corresponding binary code: Here, "round" means rounding to the nearest integer.

[0051] According to the properties of trigonometric functions, as i increases, E i With E i+1 Gradually increase, that is:

[0052]

[0053] Based on the above analysis, we can conclude that:

[0054]

[0055] From E0 = 0, we can obtain:

[0056]

[0057] Because 2 < π < 2 2 ,so We can conclude that Δ = 2 N -L-2 .

[0058] Furthermore, when non-uniformly dividing the phase interval of the sinusoidal signal (0, π / 2), since the critical phase point corresponding to the amplitude quantization value of 1 / 4 of the waveform divides the phase (0, π / 2) into progressively increasing phase intervals, using multiple steps (Δ, 2Δ, 4Δ, 8Δ...) for phase division ensures that each phase interval still contains only one critical phase point. Specifically, a preferred non-uniform division method includes: using multiple phase steps to non-uniformly divide the phase interval of the sinusoidal signal (0, π / 2) to obtain multiple sub-phase intervals, such that each sub-phase interval contains only one critical phase point; wherein, when switching phase steps, the switching point is determined based on the slope at the switching point being equal to the ratio of the size of the aforementioned sub-amplitude interval to the next phase step; the ratio of the next phase step to the previous phase step is 2; the first phase step...

[0059] Specifically, due to the original amplitude quantization point A i The corresponding critical phase point E i The phase was divided into (0, π / 2) non-uniform phase intervals. and It increases sequentially, so when The subsequent intervals can be divided using larger steps (2Δ, 4Δ, 8Δ...), which reduces the number of addresses in the ROM table. The specific operation is as follows:

[0060] Taking compression using two step sizes, Δ and 2Δ, as an example, the step size is known to be Δ = 2. N-L-2 The corresponding phase interval is Then, a phase interval of twice the step size 2Δ is adopted. To ensure that each phase interval still contains only one critical phase point when the phase step is doubled, the phase quantization point interval at the switching point when switching phase steps is equal to the phase interval when switching phase steps. That is, the slope of the sine curve at the switching point should be equal to the ratio of the amplitude interval (i.e., sub-amplitude interval) to the double-step phase interval (double phase step). Here, Δy is the amplitude interval. Δx is the phase interval

[0061] Since the derivative of the sine function sinθ is cosθ, we have Solving Then the L-bit binary code corresponding to the critical phase point θ1 of Δ and 2Δ is:

[0062]

[0063] Similarly, the critical phase point θ2 for 2Δ and 4Δ can be obtained:

[0064]

[0065] The L-bit binary code corresponding to θ2 is:

[0066]

[0067] When only Δ and 2Δ steps are used for compression, the compression ratio is:

[0068] That is, the improved ROM1 table can reduce the capacity by about 22%.

[0069] When compression is performed using three steps: Δ, 2Δ, and 4Δ, the compression ratio is:

[0070] That is, the improved ROM1 table can reduce the capacity by about 27%.

[0071] Similarly, more step sizes such as Δ, 2Δ, 4Δ, 8Δ, etc., can be used. Although using more step sizes can improve the compression ratio, the improvement in compression ratio becomes increasingly limited, while the circuit complexity increases. Therefore, considering both compression ratio and circuit complexity, Δ and 2Δ step sizes are preferred for compression.

[0072] Specifically, the composition of ROM1 using Δ and 2Δ stepping is shown in Table 1, where n Δ This indicates the number of phase intervals divided by a step of Δ.

[0073] Table 1

[0074]

[0075]

[0076] ROM2 implements amplitude-phase conversion, using L-1 bits of amplitude quantization value as the address and storing the interval [0, π / 2). L-1 Amplitude quantization point A iThe corresponding N-2 bit phase quantization value E i The low NL-2 bit phase quantization value.

[0077] The composition of ROM2 is shown in Table 2:

[0078] Table 2

[0079]

[0080] It should be noted that the ROM size of a traditional phase-truncation-free DDS is 2. L ×(N-3); Taking dual-step as an example, the ROM size after compression using the dual-ROM table provided by this invention is: in, This indicates rounding up to the nearest integer.

[0081] Specifically, based on the dual-ROM table compression method provided by this invention, when N=12 and L=5, the size of the ROM before compression is 2. 5 ×9, the compressed ROM size is approximately 2 5 ×6.5, the compression ratio is 6.5 / 9≈0.722. When N=32 and L=16, the size of the ROM before compression is 2. 16 ×29, the compressed ROM size is 2 16 ×19.5, the compression rate is 19.5 / 29≈0.672.

[0082] In summary, the ROM compression method based on phase truncation provided by this invention, compared with the traditional phase truncation DDS using a single ROM table, can perform lossless compression of the ROM table without significantly increasing circuit complexity, and can reduce the ROM capacity by about 30%.

[0083] Example 2

[0084] A direct digital frequency synthesis method is used to transform sinusoidal signals based on an input frequency control word, such as... Figure 1 As shown, the specific steps include:

[0085] S1. Input the frequency control word K into the N-bit phase accumulator to obtain the N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as the sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as the truncated phase quantization value, and the middle L bits as the address of the first ROM table (ROM1);

[0086] Specifically, the frequency control word K is input into an N-bit phase accumulator to obtain an N-bit phase quantization value Ad. This N-bit phase quantization value first enters an address adapter to divide it into three parts. Specifically, the highest bit of the N-bit phase quantization value is used as a sign flag, and it is determined whether the second highest bit of the N-bit phase quantization value is 1. If so, the lower N-2 bits of the N-bit phase quantization value (i.e., bits 0 to N-3 from low to high) are inverted (specifically: (Ad[N-2] == 1)). After ? ~Ad[N-3:0]:Ad[N-3:0]), take the middle L bits of the N-bit phase quantization value (i.e., the N-2-Lth to N-3th bits of the N-bit phase quantization value from low to high) as the address of ROM1, and the lower N-2-L bits as the truncated phase quantization value, and store them in the register. Otherwise, directly use the middle L bits of the N-bit phase quantization value as the address of ROM1 to map the amplitude value of the first quadrant to the entire quadrant, and store the lower N-2-L bits as the truncated phase quantization value in the register.

[0087] S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4.

[0088] Specifically, the high 1 bit of the content stored in the address of the first ROM table is the flag bit of the current sub-phase interval; it is determined whether the high 1 bit of the content stored in the address of ROM1 is 1. If it is, it means that the current sub-phase interval contains a critical phase point. The low bits need to be compared and judged and then the amplitude is corrected. The low bits to be compared are stored in ROM2.

[0089] S3. Use the lower L-1 bits of the content stored in the address of the first ROM table as the address of the second ROM table (ROM2), read the content stored in the second ROM table, and compare it with the truncated phase quantization value. If the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address of the first ROM table by 1; otherwise, do not operate on the lower L-1 bits of the content stored in the address of the first ROM table.

[0090] Specifically, based on the address of ROM2, ROM2 is looked up, and the output N-2-L bits are calculated. A comparator compares the N-2-L bits output from the ROM2 lookup table with the truncated phase quantization value. If the N-2-L bits output from the ROM2 table are greater than the truncated phase quantization value, the comparator outputs 1; otherwise, the comparator outputs 0. A subtractor subtracts the lower L-1 bits of the stored content at the address of the first ROM table from the comparator output. That is, when the comparator output is 1, the lower L-1 bits of the stored content at the address of the first ROM table are decremented by 1; otherwise, no operation is performed on the lower L-1 bits of the stored content at the address of the first ROM table. The result of the subtractor is the lower L-1 bits of the stored content at the new address of the first ROM table.

[0091] S4. Using an amplitude adapter, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted based on the sign flag bit. After obtaining the L-bit amplitude quantization value, a digital-to-analog converter is used to perform digital-to-analog conversion, thereby transforming the sine wave signal and finally generating a specific sine wave signal.

[0092] Specifically, the amplitude adapter is used to map the waveform to the correct quadrant;

[0093] The sine wave signal is stored in the first ROM table and the second ROM table using the ROM compression method provided in Embodiment 1 of the present invention.

[0094] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0095] Example 3

[0096] A direct digital frequency synthesis system includes: a controller, a phase accumulator, and a digital-to-analog converter;

[0097] The controller is used to execute the direct digital frequency synthesis method provided in Embodiment 2 of the present invention.

[0098] The relevant technical solutions are the same as in Embodiment 2, and will not be repeated here.

[0099] Example 4

[0100] When a sinusoidal signal is stored in a first ROM table (ROM1) and a second ROM table (ROM2) using the ROM compression method provided in Embodiment 1, and specifically when the phase interval of the sinusoidal signal (0, π / 2) is non-uniformly divided using multiple phase steps, this embodiment provides a direct digital frequency synthesis method for transforming a sinusoidal signal based on an input frequency control word, such as... Figure 2 As shown, it includes the following steps:

[0101] S1. Input the frequency control word K into the N-bit phase accumulator to obtain the N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as the sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as the truncated phase quantization value, and the middle L bits as the address to be corrected; compare the address to be corrected with the L-bit phase quantization value at each switching point to determine the phase step of the interval where the address to be corrected is located; subtract the L-bit phase quantization value at the switching point when switching to the phase step from the address to be corrected, divide the difference by the phase step and round up, add the rounded result to the number of sub-phase intervals under all phase steps smaller than the phase step, and obtain the corrected L-bit address as the address of the first ROM table (ROM1);

[0102] Specifically, the frequency control word K is input into an N-bit phase accumulator to obtain an N-bit phase quantization value Ad. This N-bit phase quantization value first enters an address adapter to divide it into three parts, and then adjusts bits N-2-L to N-3 from low to high. Specifically, the highest bit of the N-bit phase quantization value is used as a sign flag, and it is determined whether the second highest bit is 1. If so, the lowest N-2 bits (i.e., bits 0 to N-3 from low to high) of the N-bit phase quantization value are inverted. After performing the operation (specifically: (Ad[N-2]==1)?~Ad[N-3:0]:Ad[N-3:0]), the middle L bits of the N-bit phase quantization value (i.e., bits N-2-L to N-3 from low to high) are taken as the address to be corrected, and the lower N-2-L bits are used as the truncated phase quantization value and stored in the register. Otherwise, the middle L bits of the N-bit phase quantization value are directly used as the address of ROM1 to map the amplitude value of the first quadrant to the entire quadrant, and the lower N-2-L bits are used as the truncated phase quantization value and stored in the register.

[0103] Furthermore, the address to be corrected is modified. Here, we take the non-uniform segmentation of the phase interval of the sine wave signal (0, π / 2) using two steps, Δ and 2Δ, as an example. In this case, the compositions of ROM1 and ROM2 are shown in Table 1 and Table 2 of Example 1, respectively. The address to be corrected is matched with the binary code corresponding to the critical phase point θ1. Compare the addresses; if the address to be corrected is less than or equal to... If the address to be corrected is used directly as the addressing address of the first ROM table, then the address to be corrected is used for addressing. Otherwise, the address to be corrected is subtracted. Divide the difference by 2 and round up. Then add the rounded result to the number of phase intervals n divided by a step of Δ. Δ This is used as the address for ROM1. Specifically, the address of ROM1 is: Where x is the address to be corrected.

[0104] S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4.

[0105] Specifically, the high 1 bit of the content stored in the address of the first ROM table is the flag bit of the current sub-phase interval; it is determined whether the high 1 bit of the content stored in the address of ROM1 is 1. If it is, it means that the current sub-phase interval contains a critical phase point. The low bits need to be compared and judged and then the amplitude is corrected. The low bits to be compared are stored in ROM2.

[0106] S3. Use the lower L-1 bits of the content stored in the address of the first ROM table as the address of the second ROM table, read the content stored in the second ROM table, compare it with the truncated phase quantization value, and if the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address of the first ROM table by 1.

[0107] Specifically, based on the address of ROM2, ROM2 is looked up, and the output N-2-L bits are calculated. A comparator compares the N-2-L bits output from the ROM2 lookup table with the truncated phase quantization value. If the N-2-L bits output from the ROM2 table are greater than the truncated phase quantization value, the comparator outputs 1; otherwise, the comparator outputs 0. A subtractor subtracts the lower L-1 bits of the stored content at the address of the first ROM table from the comparator output. That is, when the comparator output is 1, the lower L-1 bits of the stored content at the address of the first ROM table are decremented by 1; otherwise, no operation is performed on the lower L-1 bits of the stored content at the address of the first ROM table. The result of the subtractor is the lower L-1 bits of the stored content at the new address of the first ROM table.

[0108] S4. Using an amplitude adapter, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted based on the sign flag bit. After obtaining the L-bit amplitude quantization value, a digital-to-analog converter is used to perform digital-to-analog conversion, thereby transforming the sine wave signal and finally generating a specific sine wave signal.

[0109] Specifically, the amplitude adapter is used to map the waveform to the correct quadrant.

[0110] The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0111] Example 5

[0112] A direct digital frequency synthesis system includes: a controller, a phase accumulator, and a digital-to-analog converter;

[0113] The controller is used to execute the direct digital frequency synthesis method provided in Embodiment 4 of the present invention.

[0114] The relevant technical solutions are the same as in Embodiment 4, and will not be repeated here.

[0115] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A ROM compression method for DDS, characterized in that, A dual-ROM table is used to compress and store the sine wave signal, including: The phase interval of the sinusoidal signal (0, π / 2) is divided into multiple sub-phase intervals. The upper bound of each sub-phase interval is quantized and encoded. The resulting phase quantization value is used as the address of the first ROM table corresponding to the sub-phase interval. The flag bit of each sub-phase interval and the waveform amplitude quantization value corresponding to its upper bound are sequentially stored in the address of the corresponding first ROM table. Divide the amplitude interval corresponding to the phase interval of the sinusoidal signal (0, π / 2) into equal intervals to obtain 2. L-1 Each sub-amplitude interval is divided into several sub-amplitude intervals, and the upper bound of each sub-amplitude interval is quantized and encoded. The resulting amplitude quantization value is used as the address of the second ROM table corresponding to the sub-amplitude interval. The phase point corresponding to the upper bound of each sub-amplitude interval is recorded as the critical phase point, and the lower N-2-L bits of the N-2-bit phase quantization value at the critical phase point are stored in the address of the corresponding second ROM table. Wherein, the flag bit is used to indicate whether the sub-phase interval contains a critical phase point; L is the bit width of the digital-to-analog converter used in the DDS; N is the bit width of the phase accumulator used in the DDS.

2. The ROM compression method according to claim 1, characterized in that, When a sub-phase interval contains a critical phase point, the flag bit of the sub-phase interval is 1; when a sub-phase interval does not contain a critical phase point, the flag bit of the sub-phase interval is 0.

3. The ROM compression method according to claim 1 or 2, characterized in that, The phase interval of the sinusoidal signal (0, π / 2) is uniformly divided.

4. The ROM compression method according to claim 1 or 2, characterized in that, The phase interval of the sinusoidal signal (0, π / 2) is non-uniformly divided to obtain multiple sub-phase intervals.

5. The ROM compression method according to claim 4, characterized in that, The phase interval of a sinusoidal signal (0, π / 2) is non-uniformly divided using multiple phase steps to obtain multiple sub-phase intervals, ensuring that each sub-phase interval includes only one critical phase point. When switching phase steps, the switching point is determined based on the slope at the switching point being equal to the ratio of the size of the aforementioned sub-amplitude interval to the next phase step. The ratio of the next phase step to the previous phase step is 2. The first phase step...

6. A direct digital frequency synthesis method, characterized in that, The process for transforming a sinusoidal signal based on an input frequency control word includes the following steps: S1. Input the frequency control word K into the N-bit phase accumulator to obtain an N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as the sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as the truncated phase quantization value, and the middle L bits as the address of the first ROM table; S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4. S3. Use the lower L-1 bits of the content stored in the address of the first ROM table as the address of the second ROM table, read the content stored in the second ROM table, compare it with the truncated phase quantization value, and if the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address of the first ROM table by 1. S4. Based on the symbol flag bit, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted to obtain the L-bit amplitude quantization value. Then, a digital-to-analog converter is used to perform digital-to-analog conversion to transform the sine wave signal. The sine wave signal is stored in the first ROM table and the second ROM table using the ROM compression method described in claim 3.

7. A direct digital frequency synthesis system, characterized in that, include: Controller, phase accumulator, and digital-to-analog converter; The controller is used to execute the direct digital frequency synthesis method according to claim 6.

8. A direct digital frequency synthesis method, characterized in that, The process for transforming a sinusoidal signal based on an input frequency control word includes the following steps: S1. Input the frequency control word K into the N-bit phase accumulator to obtain an N-bit phase quantization value; use the higher bit of the N-bit phase quantization value as a sign flag bit, and when the next higher bit is 1, invert the lower N-2 bits to update the N-bit phase quantization value; use the lower N-2-L bits of the N-bit phase quantization value as a truncated phase quantization value, and the middle L bits as the address to be corrected; compare the address to be corrected with the L-bit phase quantization value at each switching point to determine the phase step of the interval where the address to be corrected is located; subtract the L-bit phase quantization value at the switching point when switching to the phase step from the address to be corrected, divide the resulting difference by the phase step and round up, add the rounded result to the number of sub-phase intervals under all phase steps smaller than the phase step, and obtain the corrected L-bit address as the address of the first ROM table; S2. Determine whether the current sub-phase interval contains a critical phase point based on the high 1 bit of the content stored in the address of the first ROM table. If yes, proceed to step S3; otherwise, proceed to step S4. S3. Use the lower L-1 bits of the content stored in the address of the first ROM table as the address of the second ROM table, read the content stored in the second ROM table, compare it with the truncated phase quantization value, and if the former is greater than the latter, decrement the lower L-1 bits of the content stored in the address of the first ROM table by 1. S4. Based on the symbol flag bit, the lower L-1 bits of the content stored in the address of the first ROM table are amplitude adapted to obtain the L-bit amplitude quantization value. Then, a digital-to-analog converter is used to perform digital-to-analog conversion to transform the sine wave signal. The sine wave signal is stored in the first ROM table and the second ROM table using the ROM compression method described in claim 5.

9. A direct digital frequency synthesis system, characterized in that, include: Controller, phase accumulator, and digital-to-analog converter; The controller is used to execute the direct digital frequency synthesis method according to claim 8.

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