Transmitting and receiving circuit and control method for frequency synthesizer thereof

Abstract

A transceiver includes a transmit circuit, a frequency synthesizer, and a control circuit. The transmit circuit is configured to generate a transmit signal. The frequency synthesizer is configured to generate a frequency signal for the transmit circuit to generate the transmit signal. The control circuit is configured to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer. When the transceiver operates in a standby mode, the control circuit generates the first control signal to cause the frequency synthesizer to have a first loop bandwidth. After the transceiver switches from the standby mode to a transmission mode for a period of time, the control circuit generates the first control signal to cause the frequency synthesizer to have a second loop bandwidth.

Description

Technical Field

[0001] This invention relates to a frequency synthesizer in a transceiver circuit. Background Technology

[0002] Current frequency synthesizers only have a single loop bandwidth. However, in carrier frequency offset and drift (CFD) testing of Bluetooth systems, a higher loop bandwidth allows for faster frequency locking and thus smaller frequency drift, resulting in better performance for the Bluetooth system in CFD tests. However, a higher loop bandwidth also makes it easier for noise from other parts of the circuit to enter the synthesizer, leading to a deterioration in the error vector magnitude (EVM) of the Bluetooth system in modulation characteristics testing. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a frequency synthesizer with adjustable loop bandwidth, which can set different loop bandwidths during the operation of a Bluetooth system, so that the Bluetooth system can have better performance in carrier frequency offset and drift as well as modulation characteristics. The frequency synthesizer has a simple architecture to avoid increasing excessive design and manufacturing costs, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a transceiver circuit is disclosed, comprising a transmission circuit, a frequency synthesizer, and a control circuit. The transmission circuit generates a transmission signal, wherein the transmission signal is transmitted via an antenna; the frequency synthesizer generates a frequency signal for the transmission circuit to generate the transmission signal; and the control circuit generates a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to enable the frequency synthesizer to have a first loop bandwidth, and for a period of time after the transceiver circuit switches from the standby mode to a transmission mode, the control circuit generates the first control signal to enable the frequency synthesizer to have a second loop bandwidth.

[0005] In one embodiment of the present invention, a control method for a frequency synthesizer of a transceiver circuit is disclosed, comprising: when the transceiver circuit is operating in a standby mode, controlling the frequency synthesizer to have a first loop bandwidth; and after the transceiver circuit switches from the standby mode to a transmission mode for a period of time, generating the first control signal to have a second loop bandwidth of the frequency synthesizer, wherein the first loop bandwidth is higher than the second loop bandwidth. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a Bluetooth transceiver circuit according to an embodiment of the present invention.

[0007] Figure 2 Timing diagram for setting the RF mode, payload format, and loop bandwidth of the frequency synthesizer for the Bluetooth transceiver circuit.

[0008] Figure 3 This is a schematic diagram of a frequency synthesizer and control circuit according to an embodiment of the present invention.

[0009] Figure 4 This is a flowchart of a control method for a frequency synthesizer in a transceiver circuit according to an embodiment of the present invention. Detailed Implementation

[0010] Figure 1 This is a schematic diagram of a Bluetooth transceiver circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the Bluetooth transceiver circuit 100 includes a receiving circuit 110, a transmitting circuit 120, a frequency synthesizer 130, and a control circuit 140. The receiving circuit 110 includes at least a low-noise amplifier 112, a mixer 114, a filter 116, an analog-to-digital converter 118, and a demodulation circuit 119. The transmitting circuit 120 includes at least a power amplifier 122, a mixer 124, a filter 126, a digital-to-analog converter 128, and a modulation circuit 129. Furthermore, the Bluetooth transceiver circuit 100 transmits and receives packets via at least one antenna 102.

[0011] In the operation of the Bluetooth transceiver circuit 100, the receiving circuit 110 receives a received signal through the antenna 102. After processing by the low-noise amplifier 112, the mixer 114 uses the frequency signal CK generated by the frequency synthesizer 130 to mix the received signal, generating a mixed signal. The mixed signal then undergoes low-pass filtering by the filter 116, and then analog-to-digital conversion by the analog-to-digital converter 118 before being input to the demodulation circuit 119 for processing. Furthermore, regarding the operation of the transmitting circuit 120, the modulation circuit 129 first generates the data to be transmitted, sends it to the digital-to-analog converter for digital-to-analog conversion, and then performs low-pass filtering by the filter 126 to generate a filtered signal. Next, the mixer 124 uses the frequency signal CK generated by the frequency synthesizer 130 to mix the filtered signal, generating a transmit signal. This transmit signal is then processed by the power amplifier 122 and transmitted through the antenna 102. It should be noted that since the operation of the receiving circuit 110 and the transmitting circuit 120 is well known to those skilled in the art, and since the focus of the present invention is on the loop bandwidth adjustment of the frequency synthesizer 130, the details of the receiving circuit 110 and the transmitting circuit 120 will not be described in detail.

[0012] refer to Figure 2 The diagram illustrates the timing of the RF mode, payload format, and loop bandwidth settings of the Bluetooth transceiver circuit 100. First, the Bluetooth transceiver circuit 100 is powered on and transitions from its original off mode to standby mode. In standby mode, the components within the Bluetooth transceiver circuit 100 begin receiving the supplied voltage, and the control circuit 140 generates a control signal Vc to control the frequency synthesizer 130 to have a first loop bandwidth BW1. In this embodiment, the first loop bandwidth BW1 has a relatively high bandwidth.

[0013] Next, at time t1, the Bluetooth transceiver circuit 100 enters the transmission mode. At the beginning of the transmission mode, the transmission circuit 120 transmits a signal outside the Bluetooth specification. This serves not only to ensure the frequency synthesizer 130 locks properly but also to provide the receiver with time to adjust the receiving frequency and gain. This period can be called early transmission (Early Tx). Specifically, during the early transmission phase, the power amplifier 122 of the transmission circuit 120 is activated and begins operation. Other control circuits of the Bluetooth transceiver circuit 100 begin pre-processing operations such as transmission power detection, and the frequency synthesizer 130 operates to generate the frequency signal CK. In this embodiment, since the first loop bandwidth BW1 of the frequency synthesizer 130 is relatively high, when the Bluetooth transceiver circuit 100 switches from standby mode to transmission mode, the frequency synthesizer 130 can directly use the higher loop bandwidth to generate the frequency signal CK, allowing it to output a frequency signal CK with the desired frequency (e.g., 2.4 GHz) in a shorter time. In this embodiment, during the early transmission phase, the transmission circuit 120 only generates a transmission signal for detection and does not transmit Bluetooth packets.

[0014] Next, at time t2, the control circuit 140 generates a control signal Vc to control the frequency synthesizer 130 to have a second loop bandwidth BW2. In this embodiment, the second loop bandwidth BW2 has a lower bandwidth, that is, the second loop bandwidth BW2 is smaller than the first loop bandwidth BW1.

[0015] At time t3, the early transmission phase ends, and the transmission circuit 120 begins transmitting Bluetooth packets. Each Bluetooth packet sequentially includes a preamble, access address, header, and payload. In the Bluetooth specification, the preamble can be 1-2 bytes, the access address approximately 4 bytes, the header 2 bytes, and the payload 0-255 bytes. In carrier frequency offset and drift testing, the average frequency of the preamble is first calculated and defined as f0. Then, frequencies f1, f2, ... measured according to the specification are compared with f0 to calculate the frequency offset. In this embodiment, since the frequency synthesizer 130 has already locked the frequency of the frequency signal CK before the transmission circuit 120 begins transmitting Bluetooth packets, the Bluetooth transceiver circuit 100 will have a smaller frequency offset, thus allowing for better performance in carrier frequency offset and drift testing. Furthermore, since the frequency synthesizer 130 has been switched to have a lower second loop bandwidth BW2 before the transmission circuit 120 starts transmitting Bluetooth packets, it is possible to avoid a large amount of noise generated in other areas of the Bluetooth transceiver circuit 100 mixing into the frequency synthesizer and affecting the performance of the Bluetooth system in modulation characteristic tests.

[0016] In one embodiment, since the time point t1 at which the Bluetooth transceiver circuit 100 enters the transmission mode from the standby mode is known, the time length for the frequency synthesizer 130 to generate the frequency signal CK with the desired frequency under the condition of having the first loop bandwidth BW1 can be obtained through simulation. Furthermore, the time length for the frequency synthesizer 130 to generate the frequency signal CK with the desired frequency under the condition of switching to the second loop bandwidth BW2 can also be obtained through simulation. Therefore, the control circuit 140 can determine an appropriate first loop bandwidth BW1 and an appropriate time point t2 to perform loop bandwidth switching. In one embodiment, the control circuit 140 can use a timer to count down starting at time point t1, so that it switches to the second loop bandwidth BW2 after the frequency synthesizer 130 has generated a stable frequency signal CK at time t2.

[0017] Figure 3 This is a schematic diagram of a frequency synthesizer 130 and a control circuit 140 according to an embodiment of the present invention. Figure 3As shown, the frequency synthesizer 130 includes a phase frequency detector 310, a charge pump 320, a loop filter 330, an oscillator 340, and a frequency divider 350. The charge pump 320 includes at least two current sources 332 and 334, and two switches SW1 and SW2. Current source 332 is coupled to a supply voltage VDD and is used to charge an output terminal N1 of the charge pump 320 through switch SW1. Current source 334 is coupled to a ground voltage and is used to discharge the output terminal N1 of the charge pump 320 through switch SW2. The loop filter 330 includes capacitors C1 to C3 and resistors R1 and R2. Capacitor C1 is coupled between terminal N1 and the ground voltage. Capacitor C2, connected in series with resistor R1, is coupled between terminal N1 and the ground voltage. Resistor R2 is coupled between terminal N1 and terminal N2. Capacitor C3 is coupled between terminal N2 and the ground voltage.

[0018] In the basic operation of the frequency synthesizer 130, the phase frequency detector 310 receives a reference frequency signal CK_REF and a frequency signal CK_DIV after division to generate a detection result. The charge pump 320 controls the opening / closing of switches SW1 and SW2 based on the detection result to generate a control signal V1. The loop filter 330 performs a low-pass filter operation on the control signal V1 to generate a filtered control signal V1'. The oscillator 340 generates a frequency signal CK based on the filtered control signal V1'. The frequency divider 350 divides the frequency signal CK to generate the frequency signal CK_DIV after division. It should be noted that since the basic functions of the various components of the phase frequency detector 310 are well known to those skilled in the art, and the focus of this embodiment is on the setting of the loop bandwidth, further details of each component are not described here.

[0019] exist Figure 3In this embodiment, the current sources 332 and 334 in the charge pump 320 are variable current sources, and the control circuit 140 can generate a control signal Vc1 to control the current amounts of the current sources 332 and 334, thereby adjusting the loop bandwidth of the frequency synthesizer 130. For example, the control circuit 140 can generate the control signal Vc1 to make the current sources 332 and 334 have a higher first current amount, so that the frequency synthesizer 130 has a higher first loop bandwidth BW1; and the control circuit 140 can generate the control signal Vc1 to make the current sources 332 and 334 have a lower second current amount, so that the frequency synthesizer 130 has a lower second loop bandwidth BW2. Furthermore, at least a portion of the capacitors C1-C3 and resistors R1 and R2 included in the loop filter 330 can be variable capacitors / variable resistors, and the control circuit 140 can generate a control signal Vc2 to control the capacitance / resistance values ​​of at least a portion of the capacitors C1-C3 and resistors R1 and R2 to adjust the loop bandwidth of the frequency synthesizer 130. For example, the control circuit 140 can generate the control signal Vc2 to adjust the capacitance / resistance values ​​in the loop filter 330 to achieve a higher cutoff frequency, thereby giving the frequency synthesizer 130 a higher first loop bandwidth BW1; and the control circuit 140 can generate the control signal Vc2 to adjust the capacitance / resistance values ​​in the loop filter 330 to achieve a lower cutoff frequency, thereby giving the frequency synthesizer 130 a lower second loop bandwidth BW2.

[0020] exist Figure 3 In the embodiments described, the control circuit 140 simultaneously generates control signals Vc1 and Vc2 to control the charge pump 320 and the loop filter 330 to obtain the desired loop bandwidth. However, the present invention is not limited thereto. In other embodiments, the control circuit 140 may generate only control signal Vc1 to control the charge pump 320, or only control signal Vc2 to control the loop filter 330 to obtain the desired loop bandwidth, without simultaneously controlling the charge pump 320 and the loop filter 330. These design variations should fall within the scope of the present invention.

[0021] It should be noted that, Figure 3 The internal circuit architecture of the charge pump 320 and loop filter 330 shown is merely illustrative and not intended to limit the invention. In other words, in other embodiments, the charge pump 320 may have a different number of current sources, and the loop filter 330 may have different resistor / capacitor configurations. As long as the control circuit 140 can control the loop bandwidth by controlling the current of at least one current source in the charge pump 320 and / or controlling a capacitor value or a resistor value in the loop filter 320, the related design variations should fall within the scope of this invention.

[0022] exist Figures 1 to 3 In this embodiment, the frequency synthesizer 130 with adjustable loop bandwidth is applied in the Bluetooth transceiver circuit 100; however, the invention is not limited thereto. In other embodiments, the frequency synthesizer 130 with adjustable loop bandwidth can also be applied to transceiver circuits of other specifications.

[0023] Figure 4 This is a flowchart of a control method for a frequency synthesizer in a transceiver circuit according to an embodiment of the present invention. Referring also to the above embodiments, Figure 4 The process is as follows.

[0024] Step 400: The process begins, and the receiver and generator circuits are energized.

[0025] Step 402: The transceiver circuit operates in standby mode.

[0026] Step 404: Control the frequency synthesizer so that the frequency synthesizer has a first loop bandwidth.

[0027] Step 406: The transceiver circuit enters the early transmission phase of the transmission mode.

[0028] Step 408: Control the frequency synthesizer to switch to having a second loop bandwidth, wherein the second loop bandwidth is lower than the first loop bandwidth.

[0029] Step 410: The early transmission phase ends, and the transceiver circuit begins transmitting packets.

[0030] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

[0031] [Symbol Explanation]

[0032] 100: Bluetooth transceiver circuit

[0033] 102: Antenna

[0034] 110: Receiver circuit

[0035] 112: Low-noise amplifier

[0036] 114: Mixer

[0037] 116: Filter

[0038] 118: Analog-to-Digital Converter

[0039] 119: Demodulation circuit

[0040] 120: Transmission circuit

[0041] 122: Power Amplifier

[0042] 124: Mixer

[0043] 126: Filter

[0044] 128: Digital-to-Analog Converter

[0045] 129: Modulation Circuit

[0046] 130: Frequency Synthesizer

[0047] 140: Control Circuit

[0048] CK: Frequency signal

[0049] Vc: Control signal

[0050] t1~t3: Time

[0051] 310: Phase-frequency detector

[0052] 320: Charge Pump

[0053] 322, 324: Current source

[0054] 330: Loop Filter

[0055] 340: Oscillator

[0056] 350: Frequency divider

[0057] CK_DIV: Frequency signal after frequency division

[0058] CK_REF: Reference frequency signal

[0059] C1~C3: Capacitors

[0060] N1, N2: Endpoints

[0061] R1, R2: Resistors

[0062] SW1, SW2: Switches

[0063] V1: Control signal

[0064] V1': Filtered control signal

[0065] Vc1, Vc2: Control signals

[0066] 400-410: Steps

Claims

1. A transceiver circuit, comprising: A transmission circuit for generating a transmission signal, wherein the transmission signal is transmitted via an antenna; A frequency synthesizer is used to generate a frequency signal for the transmission circuit to generate the transmission signal. as well as A control circuit is used to generate a first control signal to control the frequency synthesizer to determine a loop bandwidth of the frequency synthesizer; When the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to give the frequency synthesizer a first loop bandwidth. And for a period of time after the transceiver circuit switches from the standby mode to a transmission mode, the control circuit generates the first control signal to give the frequency synthesizer a second loop bandwidth. The bandwidth of the first circuit is higher than that of the second circuit.

2. The transceiver circuit according to claim 1, wherein, after the transceiver circuit operates for a period of time following a switch from the standby mode to the transmission mode, and during an early transmission phase of the transmission mode, the control circuit generates the first control signal to cause the frequency synthesizer to have the second loop bandwidth.

3. The transceiver circuit according to claim 2, wherein the transmission circuit begins to generate a packet as the transmission signal only after the transceiver circuit has completed the early transmission phase and the frequency synthesizer has the second loop bandwidth.

4. The transceiver circuit according to claim 1, wherein the frequency synthesizer comprises: A phase frequency detector is used to receive a reference frequency signal and a frequency signal after frequency division to generate a detection result; A charge pump, coupled to the phase frequency detector, is used to generate a control signal based on the detection result; A primary loop filter, coupled to the charge pump, is used to filter the control signal to generate a filtered control signal. An oscillator, coupled to the loop filter, is used to generate the frequency signal according to the filtered control signal; as well as A frequency divider, coupled to the oscillator and the phase frequency detector, is used to divide the frequency signal to generate the divided frequency signal; The control circuit generates the first control signal to control the current amount of at least one current source in the charge pump to determine the loop bandwidth of the frequency synthesizer.

5. The transceiver circuit of claim 4, wherein when the transceiver circuit operates in a standby mode, the control circuit generates the first control signal to cause the at least one current source to have a first current quantity, so that the frequency synthesizer has the first loop bandwidth; and after the transceiver circuit operates in a period of time following a switch from the standby mode to the transmission mode, the control circuit generates the first control signal to cause the at least one current source to have a second current quantity, so that the frequency synthesizer has the second loop bandwidth, wherein the first current quantity is greater than the second current quantity.

6. The transceiver circuit according to claim 4, wherein the control circuit further generates a second control signal to control a capacitor value or a resistor value in the loop filter to determine the loop bandwidth of the frequency synthesizer.

7. The transceiver circuit according to claim 1, wherein the frequency synthesizer comprises: A phase frequency detector is used to receive a reference frequency signal and a frequency signal after frequency division to generate a detection result; A charge pump, coupled to the phase frequency detector, is used to generate a control signal based on the detection result; A primary loop filter, coupled to the charge pump, is used to filter the control signal to generate a filtered control signal. An oscillator, coupled to the loop filter, is used to generate the frequency signal according to the filtered control signal; as well as A frequency divider, coupled to the oscillator and the phase frequency detector, is used to divide the frequency signal to generate the divided frequency signal; The control circuit generates the first control signal to control a capacitor value or a resistor value in the loop filter to determine the loop bandwidth of the frequency synthesizer.

8. The transceiver circuit according to claim 1, wherein the transceiver circuit is a Bluetooth transceiver circuit.

9. A control method for a frequency synthesizer of a transceiver circuit, the frequency synthesizer being used to generate a frequency signal for a transmission circuit of the transceiver circuit to generate a transmission signal, the method comprising: When the transceiver circuit is operating in a standby mode, the frequency synthesizer is controlled to have a first loop bandwidth. as well as After the receiver / transmitter switches from standby mode to a transmission mode for a certain period of time, a first control signal is generated to give the frequency synthesizer a second loop bandwidth, wherein the first loop bandwidth is higher than the second loop bandwidth.

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