LDPC decoder based on a large check matrix

Abstract

The application discloses a kind of LDPC decoders based on large-scale check matrix;It includes central controller, variable node memory, check node memory, update algorithm calculation unit, hard decision memory and early termination iteration module;Among them: the check node memory reduces the bit width of check node signal, and the FIFO of the update algorithm variable node update outer information in the update algorithm calculation unit is removed.The application can save storage space and improve hardware resource utilization rate with little performance loss;At the same time, the FIFO of the temporary variable node outer information in the traditional serial layer decoding algorithm (TDMP) decoder is removed, the resource occupation of the memory is reduced, and the area efficiency of the decoder is improved.

Description

Technical Field

[0001] This invention belongs to the field of channel coding and decoding technology, and more specifically, relates to an LDPC decoder based on a large-scale parity-check matrix. Background Technology

[0002] With the continuous development of technology, in order to meet the ever-increasing demand for data transmission, it is necessary to develop optical communication technologies that balance system reliability and efficiency. Channel coding and decoding technologies can effectively improve the anti-interference capability of communication systems, ensuring reliable transmission while maintaining transmission rate. Low-density parity-check codes (LDPC), with decoding performance approaching the Shannon limit, are widely used as channel error correction codes in communication standards such as wide area network communication standards, millimeter-wave communication standards, digital satellite broadcasting standards, 10 Gigabit Ethernet standards, and 5G.

[0003] With the increasing demands for data transmission throughput, existing solutions that consume excessive hardware resources for storing variable nodes and parity nodes remove the space for the minimum value, storing only the second smallest value, and using the second smallest value to deduce the minimum value. When the second smallest value is greater than a certain threshold T, the minimum value is equal to a preset value β; otherwise, it is equal to 0. However, when the parity check matrix is ​​large and the throughput requirement is high, the decoding performance suffers significantly. Therefore, it is necessary to propose an LDPC decoding technique for large-scale parity check matrices that can improve decoder throughput and reduce hardware resource consumption while minimizing decoding performance loss. Summary of the Invention

[0004] To address the shortcomings or improvement needs of existing technologies, this invention proposes an LDPC decoder based on a large-scale parity-check matrix. This decoder solves the problem of excessive hardware resource consumption for storing node update information in long codes and large matrices, significantly improving the decoder's throughput and area efficiency.

[0005] To achieve the above objectives, this invention provides an LDPC decoder based on a large-scale parity-check matrix, comprising a central controller, variable node memory, parity node memory, update algorithm calculation unit, hard-decision codeword memory, and early termination iteration module. External data is input to the decoder, and after calculation by the calculation unit and successful hard-decision, the decoded result is output; wherein:

[0006] The central controller coordinates the cooperation between various modules during the decoding process of the entire LDPC decoder.

[0007] Variable node storage is used to store variable node information;

[0008] Verification node storage is used to store verification node information;

[0009] The algorithm calculation unit is updated to calculate the updates of variable nodes and verification nodes;

[0010] Hard decision memory is used to store hard decision results;

[0011] The early termination module checks whether the hard decision result meets the decoding stop condition. If it does, the early termination of the decoding iteration is completed and the result is output; otherwise, the decoding iteration continues.

[0012] The signal bit width of the check node is reduced in the check node memory to reduce the storage resource consumption of the check node without increasing the output bit error rate (FER) and the average decoding time (ADC).

[0013] In the update algorithm calculation unit, the first-in-first-out (FIFO) process for updating external information in the temporary variable node of the update algorithm is completely removed, thereby improving the area efficiency in the update algorithm calculation unit.

[0014] In this invention, the width of the check node signal in the check node memory is reduced by 1 bit, for example, from 6 bits to 5 bits.

[0015] The workflow of an LDPC decoder based on a large-scale parity-check matrix includes:

[0016] Step 1: Read the variable node information from the variable node memory;

[0017] Step 2: Read the information of the previous connected check node of the corresponding variable node in the check node memory;

[0018] Step 3: Update the verification information by passing the read variable node and verification node information through an adder;

[0019] Step 4: Take the posterior information sign bit for hard decision. If the decision is successful, the iteration will end early and the codeword will be output. Otherwise, jump to step 1 and repeat the loop until the iteration ends.

[0020] In summary, compared with the prior art, the above technical solutions proposed by this invention can achieve the following beneficial effects:

[0021] The LDPC decoder based on a large-scale parity-check matrix proposed in this invention reduces the bit width of the existing parity node signal by 1 bit, removes the first-in-first-out (FIFO) method that requires temporary storage of information outside the virtual network (VN), reuses the a posteriori information memory, reduces memory resource consumption, improves the area efficiency of the decoder without changing the algorithm, and significantly reduces the technical problem of long code and large matrix storage resource consumption. Attached Figure Description

[0022] Figure 1 This is a diagram of the overall hardware framework of the LDPC decoder based on a large-scale parity-check matrix in this invention.

[0023] Figure 2This is a comparison chart of the output frame error rate (FER) and average decoding time (ADC) results of the traditional 6-bit parity node and the reduced 1-bit width provided by this invention.

[0024] Figure 3 This is a hardware architecture diagram of a traditional TDMP LDPC decoder.

[0025] Figure 4 This is a hardware architecture diagram of a storage-multiplexed LDPC layered decoder based on a large-scale parity check matrix provided by the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] To facilitate understanding of this invention, the overall hardware architecture of the LDPC decoder will first be described, such as... Figure 1 The diagram shown is the final hardware architecture of the LDPC decoder based on a large-scale parity-check matrix designed in this embodiment. It mainly includes the following modules:

[0028] The central controller (Controller) coordinates the cooperation between the various modules during the decoding process of the entire LDPC decoder;

[0029] Variable node storage (VM) is used to store variable node information;

[0030] The verification node storage (CM, SM) is used to store verification node information;

[0031] The Update Algorithm Element is used to update variable nodes and check nodes.

[0032] Hard decision memory (HM) is used to store hard decision results;

[0033] The Early Termination of Iteration (ET) module determines whether the hard decision result meets the decoding stop condition. If it does, the iterative decoding is terminated early and the result is output. If not, the decoding iteration continues.

[0034] This invention, through analysis of the check node calculation formula, discovers that reducing the bit width of the check node information by one bit results in an overflow error that can be tolerated by the decoder. According to the check node calculation formula:

[0035]

[0036] When the check information is 6 bits, the maximum amplitude of the check node information is: and Generally, it's less than 1. Therefore, the range that 6 bits can represent exceeds the possible values ​​of CN, making 6-bit quantization wasteful. However, when the bit width is reduced by 1 bit, using 5 bits, if the bit width of CN is insufficient to represent the corresponding value, causing an overflow error, this situation actually indicates that the decoding iteration is about to converge. Therefore, this part of the error can be tolerated by the decoder, just as... Figure 2 As shown, both the output bit error rate (FER) and average decoding time (ADC) indicate that the decoding performance difference introduced by this technique is minimal.

[0037] For easier understanding, please refer to Figure 3 and Figure 4 This invention proposes an embodiment that removes the FIFO that temporarily stores VN external information and reuses the posterior information memory. In the traditional Serial Layer Decoding (TDMP) decoder, a FIFO is needed to temporarily store the VN external information obtained by subtracting the CN external information from the posterior probability information. After the CN external information is updated, it is added to the VN external information to obtain the updated posterior probability information, which is then written back to the posterior probability information memory.

[0038] In the LDPC storage reuse hardware architecture based on large-scale parity-check matrix, the variable node information generated by the V network variable node unit NC that needs to be temporarily stored is first written back to the variable node memory VM, and then read from the VM when the central control unit CNU needs it, which reduces hardware resource consumption and improves area efficiency.

[0039] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An LDPC decoder based on a large-scale parity-check matrix, characterized in that, It includes: The central controller coordinates the cooperation between various modules during the decoding process of the entire LDPC decoder. Variable node storage is used to store variable node information; Verification node storage is used to store verification node information; The algorithm calculation unit is updated to calculate the updates of variable nodes and verification nodes; Hard decision memory is used to store hard decision results; The early termination module checks whether the hard decision result meets the decoding stop condition. If it does, the early termination of the decoding iteration is completed and the result is output; otherwise, the decoding iteration continues. The signal width of the check node is reduced from 6 bits to 5 bits in the check node memory to reduce the storage resource consumption of the check node without increasing the output bit error rate (FER) and average decoding time (ADC). The FIFO that removes external information from the update algorithm variable node in the update algorithm calculation unit is used to improve the area efficiency in the update algorithm calculation unit. The variable node information generated by the network variable node unit that needs to be temporarily stored is first written back to the variable node memory, and then read from the variable node memory when the central controller needs it.

2. The LDPC decoder based on a large-scale parity-check matrix according to claim 1, characterized in that, Its workflow includes: Step 1: Read the variable node information from the variable node memory; Step 2: Read the information of the previous connected check node of the corresponding variable node in the check node memory; Step 3: Update the verification information by passing the read variable node and verification node information through an adder; Step 4: Take the posterior information sign bit for hard decision. If the decision is successful, the iteration will end early and the codeword will be output. Otherwise, jump to step 1 and repeat the loop until the iteration ends.

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