Image processing circuit and electronic device

Abstract

The present disclosure provides an image processing circuit and an electronic device, wherein the image processing circuit comprises a first delay module, a second delay module, an identification module and an adjustment module. Firstly, the pixel values of every three adjacent pixel points are pairwise differentiated in each row, and the change of the differentiation result is identified to determine the change identification sequence corresponding to each row of pixel points. Thus, based on the change identification sequence, each row of pixel points can be divided into different segments (such as high-frequency change segments or low-frequency change segments) according to the change. Then, different processing methods can be used for different segments. Thus, the problems that the effect is not obvious enough after the low-frequency region is processed, the visual effect is too messy after the high-frequency region is processed, or the effect is not good enough when the region in the high-frequency region that meets the linear rule is processed in the same way as the high-frequency region, can be avoided when the same image processing algorithm is applied to the whole row.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and more particularly to an image processing circuit and electronic device. Background Technology

[0002] Currently, video image processing is often performed on a line-by-line basis. However, applying the same image processing algorithm to an entire line can lead to poor image processing results. Summary of the Invention

[0003] This disclosure proposes an image processing circuit and electronic device. The specific solution is as follows:

[0004] The first aspect of this disclosure provides an image processing circuit, comprising:

[0005] The system comprises a first delay module, a second delay module, an identification module, and an adjustment module.

[0006] The input terminal of the first delay module is connected to the first input terminal of the recognition module, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed;

[0007] The first delay module is used to delay each received pixel value for a first duration and then output it to the second delay module and the second input terminal of the recognition module;

[0008] The second delay module is used to delay each received pixel value for the first duration and then output it to the third input terminal of the recognition module;

[0009] The identification module is used to determine a first difference between a first pixel value received by the first input terminal and a second pixel value received by the second input terminal, and a second difference between the second pixel value and a third pixel value received by the third input terminal, and based on the relationship between the third difference between the first difference and the second difference and the difference threshold, determine a change identifier corresponding to the first pixel value, and output the change identifier to the adjustment module;

[0010] The adjustment module is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition.

[0011] Another embodiment of this disclosure provides an electronic device including the image processing circuit described above.

[0012] The image processing circuit and electronic device of this disclosure include a first delay module, a second delay module, a recognition module, and an adjustment module. First, the pixel values ​​of every three adjacent pixels are differentially analyzed row by row. The changes between the differential results are identified to determine the change identifier sequence corresponding to each row of pixels. The change identifiers of the first two pixels in each row are initially set to fixed values. Then, based on the change identifier sequence and a first preset condition, change identifiers that do not meet the first preset condition are adjusted and output. This allows each row of pixels to be directly divided into different segments (e.g., high-frequency change segments or low-frequency change segments) based on the adjusted change identifier sequence, enabling different processing methods to be applied to different segments. This avoids the problems that may occur when applying the same image processing algorithm to an entire row, such as insufficient effect after processing low-frequency areas, excessive visual clutter after processing high-frequency areas, or insufficient effect when using the same image processing algorithm for linearly regular areas within high-frequency areas.

[0013] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 This is a schematic diagram of the structure of an image processing circuit provided in an embodiment of the present disclosure;

[0016] Figure 2 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure;

[0017] Figure 3 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure;

[0018] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0019] The embodiments disclosed herein are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0020] In related technologies, video image processing is performed on a line-by-line basis. However, using the same image processing algorithm for an entire line may result in insufficient effect after processing low-frequency regions, or excessive visual clutter after processing high-frequency regions. Furthermore, high-frequency regions sometimes exhibit linear sequence changes; applying the same algorithm to such sequences as to high-frequency regions yields inadequate processing results.

[0021] This disclosure addresses the above-mentioned problems by proposing an image processing circuit that, during video image processing, identifies the pixel value sequence corresponding to each row of pixels in the image. This accurately classifies the pixels in each row into low-frequency and high-frequency pixels, allowing different processing methods to be applied to different pixels. Furthermore, the same algorithm is used for linear sequences appearing in the high-frequency region as for the low-frequency region. This provides the means for finer-grained image processing and improved image processing results.

[0022] The image processing circuit provided in this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a schematic diagram of the structure of an image processing circuit provided in an embodiment of the present disclosure.

[0024] like Figure 1 As shown, the image processing circuit includes: a first delay module 101, a second delay module 102, a recognition module 103, and an adjustment module 104.

[0025] The input terminal of the first delay module 101 is connected to the first input terminal of the recognition module 103, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed;

[0026] The first delay module 101 is used to delay each received pixel value for a first time period and then output it to the second delay module 102 and the second input terminal of the recognition module 103;

[0027] The second delay module 102 is used to delay each received pixel value for the first duration and then output it to the third input terminal of the recognition module 103;

[0028] The identification module 103 is used to determine the first difference between the first pixel value received by the first input terminal and the second pixel value received by the second input terminal, and the second difference between the second pixel value and the third pixel value received by the third input terminal, and based on the relationship between the third difference between the first difference and the second difference and the difference threshold, determine the change identifier corresponding to the first pixel value, and output the change identifier to the adjustment module 104.

[0029] The adjustment module 104 is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition.

[0030] A pixel value sequence is a sequence of pixel values ​​corresponding to each row of pixels in an image. For example, if an image consists of 100 rows of pixels, then it will form 100 pixel value sequences.

[0031] The first duration can be any preset time length. In some possible implementations, the first duration can be the length of one cycle of the clock signal in the image processing circuit, or the length of several clock signal cycles.

[0032] Furthermore, the first pixel value is the pixel value in the pixel value sequence input to the first input terminal of the recognition module 103 in the image to be processed. The second pixel value is the pixel value in the pixel value sequence input to the second input terminal of the recognition module 103 after being delayed for a first duration by the first delay module 101. The third pixel value is the pixel value in the pixel value sequence input to the third input terminal of the recognition module 103 after being delayed for a first duration by both the first delay module 101 and the second delay module 102. The difference threshold is a preset critical value used to determine the change indicator corresponding to the first pixel value, and can be 10, 15, 20, etc., which is not limited in this disclosure.

[0033] The third difference is the absolute value of the difference between the first and second differences.

[0034] The change identifier is used to identify the change in the pixel value corresponding to a pixel point compared with the two adjacent pixel values. For example, if the third difference is greater than or equal to the difference threshold, the change identifier is set to 0, indicating that the change between the first and second differences is larger among the three pixel values; if the third difference is less than the difference threshold, the change identifier is set to 1, indicating that the change between the first and second differences is smaller, and so on. This disclosure does not limit the specific implementation of the change identifier.

[0035] It should be noted that, in order to divide the image into finer granularities, the first delay module 101 and the second delay module 102 can delay each pixel value by the transmission time of each pixel value in the pixel value sequence, so that the first pixel value, the second pixel value and the third pixel value processed by the recognition module 103 are three adjacent pixel values ​​in the same row of pixel values.

[0036] The first preset condition is a pre-defined condition used to determine whether the change identifier corresponding to each pixel needs to be adjusted. In this disclosure, the change identifier corresponding to each pixel is used to identify the change between the pixel and the difference results obtained after pairwise difference between the two preceding pixels. Simultaneously (except for the last two pixels), each pixel is also the pixel used to determine the change identifier of the first or second preceding pixel. If the change identifier corresponding to a pixel is inconsistent with the change identifier corresponding to an adjacent pixel, it indicates that the change identifier determined by the difference result between the pixel values ​​of the two preceding pixels is different from the change identifier determined by the difference result between the subsequent pixel values ​​of the pixel and its preceding pixel. Dividing the image into high-frequency and low-frequency regions at the pixel granularity not only reduces the accuracy of region division but also increases the complexity of the overdrive compensation process. Therefore, it is possible to determine whether a consecutive pixel is a high-frequency pixel or a low-frequency pixel based on whether the change results of pairwise difference between multiple consecutive pixels are consistent. Therefore, the first preset condition can be a set distance threshold. In other words, based on the first preset condition, if the change identifiers corresponding to multiple pixels within any distance threshold range in the change identifier sequence are inconsistent, the change identifiers corresponding to the pixels that need to be adjusted will be adjusted.

[0037] For example, if the distance threshold corresponding to the first preset condition is 5, and the change identifier for a pixel is 0, it means that the difference between the pixel value of that pixel and its adjacent pixel is relatively large compared to the difference between the two adjacent pixels. A change identifier of 1 indicates a relatively small change. In this case, if a segment of the change identifier sequence contains "0101011111", this segment contains both "1" and "0". Although the first five change identifiers contain both "1" and "0", the consecutive repetitions of 1 and 0 are less than 5, meaning the first preset condition is not met. Since the change of the "1" identifier is relatively small, the adjustment module 104 can adjust the "1" identifier to "0" before outputting the segment of change identifiers. The adjusted output change sequence identifier might be "0000011111", which divides this part of the pixels into pixels with larger changes (high-frequency region) and pixels with smaller changes (low-frequency region).

[0038] It should be noted that since there are no adjacent first two pixels in the same row for the first two pixels of each row, the change identifiers corresponding to the first two pixels of each row can be determined based on fixed pixel values; or, the change identifiers corresponding to the first two pixels of each row can be set to fixed values. It is estimated that the change identifiers corresponding to the first two pixels of each row can be set to the identifiers with larger changes (0 or 1), or they can be set to the identifiers with smaller changes (1 or 0), etc. This disclosure does not limit this.

[0039] In this disclosure, by utilizing an image processing circuit, the pixel values ​​of every three adjacent pixels are first differentially analyzed row by row. The changes between the differential results are then identified to determine the change identifier sequence corresponding to each row of pixels. Next, based on the change identifier sequence and a first preset condition, change identifiers that do not meet the first preset condition are adjusted before being output. This allows each row of pixels to be directly divided into different segments (such as high-frequency change segments or low-frequency change segments) based on the adjusted change identifier sequence, enabling different processing methods to be applied to different segments. This avoids the problems that may occur when applying the same image processing algorithm to an entire row, such as insufficient effect after processing low-frequency areas, excessive visual clutter after processing high-frequency areas, or insufficient effect when using the same image processing algorithm for linearly consistent areas within high-frequency regions.

[0040] In some possible implementations, the image processing circuit may include a clock module 105 connected to the first delay module 101 and the second delay module 102, respectively. The first delay module 101 and the second delay module 102 are respectively used to determine the first duration based on the period of the clock signal output by the received clock module 105.

[0041] In this disclosure, the first delay module 101 and the second delay module 102 determine the first duration by receiving the clock cycle signal input by the clock module 105, for example, the first duration is the length of one clock cycle signal. In the first clock cycle, the first pixel value in the pixel value sequence is input into the recognition module 103 and the first delay module 101; in the second clock cycle, the second pixel value in the pixel value sequence is input into the recognition module 103 and the first delay module 101, while the first delay module 101 inputs the first pixel value into the second delay module 102 and the recognition module 103; in the third clock cycle, the third pixel value in the pixel value sequence is input into the recognition module 103 and the first delay module 101, while the first delay module 101 inputs the second pixel value into the recognition module 103 and the second delay module 102, and the second delay module 102 inputs the first pixel value into the recognition module 103; in the fourth clock cycle, the fourth pixel value in the pixel value sequence is input into the recognition module 103 and the first delay module 101, while the first delay module 101 inputs the third pixel value into the recognition module 103 and the second delay module 102, and the second delay module 102 inputs the second pixel value into the recognition module 103, and so on. Except for the first two pixels in each row, a new pixel value in the pixel value sequence is input to the recognition module 103 in each clock cycle. At the same time, the first delay module 101 and the second delay module 102 input the two pixel values ​​adjacent to the new pixel value to the recognition module 103. Then, the recognition module 103 can determine the change identifier of the new pixel value based on the change of the difference result between the new pixel value and the two adjacent pixel values.

[0042] In some possible implementations, the identification module 103 can be used to determine the change identifier corresponding to the first pixel value as the first identifier when the third difference is greater than the difference threshold; or, when the third difference is less than or equal to the difference threshold, determine the change identifier corresponding to the first pixel value as the second identifier.

[0043] The specific forms of the first and second identifiers can be set as needed, such as the first identifier being "0" and the second identifier being "1", or the first identifier being "1" and the second identifier being "0", etc. This disclosure does not limit this.

[0044] In this disclosure, the identification module 103 performs pairwise difference operations on the received first pixel value, second pixel value, and third pixel value to obtain a first difference and a second difference. Then, it compares the difference between the two difference results with the difference threshold, and determines the change identifier corresponding to the first pixel value based on the relationship between the two, providing conditions for the subsequent adjustment module 104 to perform further operations on the sequence.

[0045] For example, the difference threshold is 20. The pixel value sequence input to the recognition module 103 contains a segment of pixel values ​​60, 70, and 80. The recognition module 103 obtains the first pixel value, the second pixel value, and the third pixel value, which are 60, 70, and 80 respectively. After pairwise difference analysis, the difference results are all 10, and the difference of the difference results is 0, which is less than the difference threshold. Therefore, the recognition module 103 can determine that the change identifier of the pixel point corresponding to the first pixel value is the second identifier.

[0046] In some possible implementations, the image processing circuit may further include a setting module 106 connected to the recognition module 103 and the adjustment module 104 respectively. The setting module 106 is used to determine a difference threshold and a first preset condition based on the acquired configuration information, and synchronize the difference threshold to the recognition module 103 and the first preset condition to the adjustment module 104.

[0047] The configuration information can be parameters that the user configures as needed, or parameters that the setting module determines based on historical data from the image processing circuit. This disclosure does not limit this.

[0048] For example, the setting module 106 determines a difference threshold of 20 based on the acquired configuration information, and the distance threshold corresponding to the first preset condition is 5. The setting module 106 can then send the difference threshold of 20 to the recognition module 103. The recognition module 103 can then determine the change identifier corresponding to each pixel value based on this difference threshold and the difference between each pixel value and the difference between the pairwise differences between each pixel value and its two adjacent preceding pixel values. Simultaneously, the adjustment module 104 receives the distance threshold of 5 corresponding to the first preset condition from the setting module 106. Based on this first preset condition, the adjustment module 104 can determine whether each change identifier in the change identifier sequence received from the recognition module 103 needs adjustment, and then adjusts the change identifiers that need adjustment before outputting them.

[0049] In some possible implementations, the image processing circuit may further include an overdrive compensation module 107 connected to the adjustment module 104, which is used to determine the first set of pixels and the second set of pixels contained in each row of pixels according to the change identifier sequence corresponding to each row of pixels output by the adjustment module 104, and to perform overdrive compensation on the pixels in the first set of pixels based on the first compensation algorithm, and to perform overdrive compensation on the pixels in the second set of pixels based on the second compensation algorithm.

[0050] Overdrive compensation is an image quality compensation algorithm. The first set of pixels represents the set of pixels with low-frequency changes. The second set of pixels represents the set of pixels with high-frequency changes.

[0051] The first compensation algorithm is for the first set of pixels. The second compensation algorithm is for the second set of pixels.

[0052] For example, in the change identifier sequence adjusted by adjustment module 103, a segment of the change identifier is "0000001111". Here, a change identifier of 0 for a pixel indicates a significant difference between the pixel value and the values ​​of its two preceding pixels, while a change identifier of 1 indicates a relatively small difference. After obtaining this change identifier sequence, overdrive compensation module 107 can determine that the first six digits "000000" represent pixels with significant changes (the second set of pixels), and the last four digits "1111" represent pixels with smaller changes (the first set of pixels). Therefore, the second compensation algorithm is used to compensate for overdrive in the first six pixels corresponding to this change identifier, and the first compensation algorithm is used for the last four pixels. This allows for different algorithms to be used to process different parts of the same row of pixels, further refining the granularity of image processing and improving the image processing effect.

[0053] Figure 2 This is a schematic diagram of another image processing circuit provided in an embodiment of the present disclosure.

[0054] like Figure 2 As shown, the adjustment module 104 in the image processing circuit provided in this disclosure includes an N-bit shift register 201, a data selector 202, and a logic gate processing component 203, wherein N is an integer greater than 1.

[0055] like Figure 2 As shown, the output of each shift register in the N-shift register 201 is connected to one input of the logic gate processing component 203, and the output of the Nth shift register in the N-shift register 201 is connected to one input of the data selector 202.

[0056] The output terminal of the logic gate processing component 203 is connected to the control terminal of the data selector 202;

[0057] Another input terminal of the data selector 202 is used to receive a preset level value;

[0058] The logic gate processing component 203 is used to determine whether the change flag in the Nth register is a flag that satisfies the first preset condition based on the output value of each register in the Nth shift register 201, and based on the determination result, control the data selector to output the value output by the shift register or output the preset level value.

[0059] The preset level value is the level value that the adjustment module 104 needs to adjust to when adjusting the change indicator. For example, the preset level value can be 0, and this disclosure does not limit it.

[0060] In this disclosure, after receiving the change identifier sequence, the adjustment module 104 retains and outputs change identifiers that meet the first preset condition based on the change identifier sequence and according to the different changes of each row of pixels, and adjusts and outputs change identifiers that do not meet the condition.

[0061] In some possible implementations, the logic gate processing component 203 includes N-2 AND gates (such as...). Figure 2 The module indicated by the "&" symbol in the diagram), and four NOT gates (such as... Figure 2 The "!" symbol in the text indicates a module, and an OR gate circuit (such as...). Figure 2 The module indicated by the symbol “≥1” and the counter 203a.

[0062] The first input terminal of the first AND gate is connected to the output terminal of the second shift register, and the second input terminal is connected to the output terminal of the first shift register;

[0063] The first input terminal of the first AND gate is connected to the output terminal of the second shift register, and the second input terminal is connected to the output terminal of the first shift register;

[0064] The first input of the i-th AND gate is connected to the output of the (i+1)-th shift register, and the second input is connected to the output of the (i-1)-th AND gate, where i is a value greater than 1 and less than N-2.

[0065] The output of the (N-3)th AND gate is connected to the first input of the OR gate through the first NOT gate.

[0066] The first input of the (N-2)th AND gate is connected to the output of the Nth shift register through the second NOT gate, the second input is connected to the output of the (N-1)th shift register through the third NOT gate, and the output is connected to the second input of the OR gate.

[0067] The output of the OR gate is connected to the input of the counter through the fourth NOT gate.

[0068] The maximum count value of the counter 203a is N, where N is a first preset condition value.

[0069] The first input is the right-hand input of the AND gate. The second input is the left-hand input of the AND gate.

[0070] The following is combined with Figure 3Taking N=5 as an example, the structure of the adjustment module provided in this disclosure will be further explained. Figure 3As shown, suppose the identifier sequence input to the adjustment module 104 is "0100111111". The currently received change identifiers in the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 of the adjustment module 104 are 1, 0, 0, 1, and 0, respectively. After calculation by the logic circuit, the OR gate outputs 1. After the OR gate output value of 1 is processed by the NOT gate, the output is 0, that is, rst_n is 0 at this time, the counter is reset to 0, and the data selector 202 outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit, and a new sequence identifier "1" is input into the shift register FF1. At this time, the values ​​of the shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 0, 0, and 1, respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n is still 0, the counter is still in the reset state, the output is 0, and the data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 1, 0, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n remains 0, the counter remains in the reset state, and the output is 0. The data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 1, 1, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 0. After the OR gate output value of 0 is processed by the NOT gate, the output value is 1. This means that rst_n is now 1, the counter value is incremented by 1, the output count value is 1, and the data selector 202 selects the value in shift register FF5 for output. In other words, the data selector output value is "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 1, 1, and 1 respectively. After calculation by the logic circuit, the OR gate outputs 0, rst_n remains 1, the counter value is incremented by 1, the output count value is 2, and the data selector 202 selects the value in shift register FF5 for output. In other words, the data selector output value is "1". From the above analysis, it can be seen that the "01001" in the change identifier sequence "0100111111" input to the adjustment module 104, after processing, becomes 00001.

[0071] Suppose the identifier sequence input to adjustment module 104 is "0100111000". The currently received change identifiers in the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 of adjustment module 104 are 1, 0, 0, 1, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 1. After the OR gate output value of 1 is processed by the NOT gate, the output is 0, that is, rst_n is 0 at this time, the counter is reset to 0, and the data selector 202 outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit, and a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 0, 0, and 1 respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n is still 0, the counter is still in the reset state, the output is 0, and the data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "1" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 1, 1, 1, 0, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n remains 0, the counter remains in the reset state, and the output is 0. The data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "0" is input into shift register FF1. At this time, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 0, 1, 1, 1, and 0 respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n remains 0, the counter remains in the reset state, and the output is 0. The data selector 202 still outputs the preset level value "0". In the next cycle, the values ​​of the 5-bit shift registers FF1, FF2, FF3, FF4, and FF5 are all shifted forward by one bit. Simultaneously, a new sequence identifier "0" is input into shift register FF1. At this point, the values ​​of shift registers FF1, FF2, FF3, FF4, and FF5 are 0, 0, 1, 1, and 1 respectively. After calculation by the logic circuit, the OR gate outputs 1, rst_n remains 0, the counter remains in the reset state, and the output is 0. The data selector 202 still outputs the preset level value "0". From the above analysis, it can be seen that the "01001" in the change identifier sequence "0100111000" input to the adjustment module 103, after processing, becomes 00000.

[0072] As can be seen from the above analysis, whether each change flag (the value in shift register FF5 in each cycle) will be output by data selector 202 depends on the current value in each shift register. In other words, whether each change flag will be adjusted depends on the next few change flags adjacent to it.

[0073] In summary, when the adjustment module 104 receives the change identifier sequence, it directly outputs the change identifiers of pixels that meet the first preset condition. For pixels that do not meet the first preset condition, the corresponding change identifiers are adjusted to "0" before output. For example, if the distance threshold set for the first preset condition is 5, in the change identifier sequence "0100111000", the number of consecutive repetitions of the first 5 "0" and "1" is less than 5, and the number of pixels with a change identifier of "1" in the consecutive pixels after the fifth pixel does not meet the distance threshold, therefore, the identifiers "1" in the first five bits will be adjusted to "0".

[0074] In some possible implementations, the adjustment module 104 further includes a data adjustment unit 204 connected to the output of the data selector 202, which is used to adjust the first identifier in the identifier sequence output by the data selector 202 that meets the second preset condition to the second identifier before outputting it.

[0075] The second preset condition is a pre-defined condition used to determine whether the change identifier corresponding to each pixel needs further adjustment. Since each change identifier in the identifier sequence output by the data selector 202 is an identifier adjusted according to the distance threshold configured by the first preset condition, each change identifier in the identifier sequence output by the data selector 202 must be the same as its several adjacent change identifiers. In this case, if the change identifier corresponding to a certain pixel in the identifier sequence output by the data selector 202 is 0, and the change identifier corresponding to its adjacent next pixel is 1, it means that the change of the next pixel relative to the previous pixel is not significant. Therefore, the change of the previous pixel relative to the next pixel can also be considered not significant. In this case, to avoid visual clutter after processing the previous pixel as a high-frequency pixel, in this disclosure, its corresponding change identifier can be adjusted to "1" to perform overdrive compensation on the previous pixel as a low-frequency pixel. That is, the second preset condition can be that the first identifier is "0", and the change identifier corresponding to its adjacent next pixel is "1", and the corresponding second identifier after adjusting the first identifier is "1".

[0076] For example, suppose the change flag sequence output by the data selector 202 to the data adjustment unit 204 is "0000111111", the change flags corresponding to the third and fourth pixels are both "0", and the change flags of all pixels following the fourth pixel are "1". In this sequence, the change flags of the third and fourth pixels are determined by the difference between the pixel values ​​of the two adjacent pixels and the pixel value of the current pixel. The change flag of the fifth pixel, determined based on the pixel values ​​of the third and fourth pixels, is "1". In other words, it can be considered that the difference between the third and fourth pixels does not change much compared to the difference between the subsequent adjacent pixels. With reference to the subsequent pixels, the third and fourth pixels can form an arithmetic sequence. Therefore, the change flags "0" for the third and fourth pixels can be adjusted to "1". The change identifier sequence “0000111111” input to the data adjustment unit 204 is adjusted and then output as “0011111111”.

[0077] In this disclosure, when the data adjustment unit 204 adjusts the change identifier sequence, for a pixel with a change identifier of "0", if multiple consecutive pixels following it satisfy a second preset condition and all have change identifiers of "1", it can be considered that this pixel and its preceding neighboring pixel can form an arithmetic sequence with multiple subsequent consecutive pixels. Therefore, the change identifiers corresponding to these two pixels are adjusted to "1". If the number of consecutive pixels following this pixel with a change identifier of "1" does not meet the second preset condition, it can be considered that this pixel and its preceding neighboring pixel cannot form an arithmetic sequence, and the change identifiers corresponding to these two pixels are not adjusted. Thus, the data adjustment unit 204 further adjusts the pixel division of each row, further improving the accuracy of pixel division in each row, thereby providing conditions for more accurate image processing.

[0078] In the image processing circuit provided in this embodiment, the pixel values ​​of every three adjacent pixels are first differentially analyzed on a row-by-row basis. The changes between the differential results are then identified to determine the change identifier sequence corresponding to each row of pixels. The change identifiers of the first two pixels in each row are initially set to fixed values. Then, based on the change identifier sequence and a first preset condition, change identifiers that do not meet the first preset condition are adjusted before being output. This allows each row of pixels to be directly divided into different segments (such as high-frequency change segments or low-frequency change segments) based on the adjusted change identifier sequence, enabling different processing methods to be applied to different segments. This avoids the problems that may occur when the same image processing algorithm is applied to an entire row, such as insufficient effect after processing low-frequency areas, excessive visual clutter after processing high-frequency areas, or insufficient effect when using the same image processing algorithm for linearly regular areas within high-frequency areas.

[0079] Based on the image processing circuit provided in the above embodiments, this disclosure also provides an electronic device, including the image processing circuit provided in the above embodiments.

[0080] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure.

[0081] like Figure 4 As shown, the electronic device 400 may include an image processing circuit 401 and a display component 402.

[0082] The structure of the image processing circuit 401 and the image processing process can be described in detail in other embodiments of this disclosure, and will not be repeated here.

[0083] In this disclosure, the image processing circuit 401 can process the image to be displayed, and then display it through the display component 402, thereby improving the quality and effect of the image displayed by the display component 402.

[0084] In some possible implementations, the electronic device 400 may also include a transceiver, a processor, a memory, etc.

[0085] The transceiver can be used to obtain the task to be run and its configuration information.

[0086] The processor executes computer instructions stored in memory. A processor can be a general-purpose processor, including a Central Processing Unit (CPU) and a network processor (NP); it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0087] The memory is connected to the processor via the system bus and communicates with it. The memory is used to store computer program instructions.

[0088] The system bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The system bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the diagram, but this does not indicate that there is only one bus or one type of bus. Transceivers are used to enable communication between database access devices and other computers (e.g., clients, read-write libraries, and read-only libraries). Memory may include random access memory (RAM) and may also include non-volatile memory.

[0089] The electronic device provided in this disclosure can be the terminal device described in the above embodiments.

[0090] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

[0091] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An image processing circuit, characterized in that, include: The system comprises a first delay module, a second delay module, an identification module, and an adjustment module. The input terminal of the first delay module is connected to the first input terminal of the recognition module, and is used to receive the sequence of pixel values ​​of each row contained in the image to be processed; The first delay module is used to delay each received pixel value for a first duration and then output it to the second delay module and the second input terminal of the recognition module; The second delay module is used to delay each received pixel value for the first duration and then output it to the third input terminal of the recognition module; The identification module is used to determine a first difference between a first pixel value received by the first input terminal and a second pixel value received by the second input terminal, and a second difference between the second pixel value and a third pixel value received by the third input terminal, and based on the relationship between the third difference between the first difference and the second difference and the difference threshold, determine a change identifier corresponding to the first pixel value, and output the change identifier to the adjustment module; The adjustment module is used to adjust and output the change identifiers in the received change identifier sequence that do not meet the first preset condition. The first preset condition is a set distance threshold. When the change identifiers corresponding to multiple pixels within the distance threshold range in the change identifier sequence are inconsistent, the change identifiers corresponding to the pixels that need to be adjusted are adjusted. The adjustment module includes: an N-bit shift register, a data selector, and a logic gate processing component, where N is an integer greater than 1; The output of each shift register in the N-bit shift register is connected to one input of the logic gate processing component, and the output of the Nth shift register in the N-bit shift register is connected to one input of the data selector. The output of the logic gate processing component is connected to the control terminal of the data selector. Another input terminal of the data selector is used to receive a preset level value; The logic gate processing component is used to determine whether the change flag in the Nth register is a flag that satisfies the first preset condition based on the output value of each register in the Nth shift register, and based on the determination result, control the data selector to output the value output by the shift register or output the preset level value.

2. The circuit as described in claim 1, characterized in that, Also includes: A clock module that is connected to the first delay module and the second delay module respectively; The first delay module and the second delay module are respectively used to determine the first duration based on the period of the clock signal output by the received clock module.

3. The circuit as described in claim 1, characterized in that, Also includes: A setting module that is connected to both the identification module and the adjustment module; The setting module is used to determine the difference threshold and the first preset condition based on the acquired configuration information, and synchronize the difference threshold to the identification module and the first preset condition to the adjustment module.

4. The circuit as described in claim 1, characterized in that, The identification module is specifically used for: If the third difference is greater than the difference threshold, the change identifier corresponding to the first pixel value is determined as the first identifier; or, If the third difference is less than or equal to the difference threshold, the change identifier corresponding to the first pixel value is determined as the second identifier.

5. The circuit as described in claim 1, characterized in that, The adjustment module also includes a data adjustment unit connected to the output of the data selector; The data adjustment unit is used to adjust the first identifier in the identifier sequence output by the data selector that meets the second preset condition to the second identifier before outputting it.

6. The circuit as claimed in claim 1, characterized in that, The logic gate processing component includes N-2 AND gates, four NOT gates, one OR gate, and a counter. The first input terminal of the first AND gate is connected to the output terminal of the second shift register, and the second input terminal is connected to the output terminal of the first shift register; The first input of the i-th AND gate is connected to the output of the (i+1)-th shift register, and the second input is connected to the output of the (i-1)-th AND gate, where i is a value greater than 1 and less than N-2. The output of the (N-3)th AND gate is connected to the first input of the OR gate through the first NOT gate. The first input of the (N-2)th AND gate is connected to the output of the Nth shift register through the second NOT gate, the second input is connected to the output of the (N-1)th shift register through the third NOT gate, and the output is connected to the second input of the OR gate. The output of the OR gate is connected to the input of the counter through the fourth NOT gate.

7. The circuit as described in claim 6, characterized in that, The maximum count value of the counter is N.

8. The circuit as described in any one of claims 1-6, characterized in that, It also includes: an overdrive compensation module connected to the adjustment module; The overdrive compensation module is used to determine the first set of pixels and the second set of pixels contained in each row of pixels according to the change identifier sequence corresponding to each row of pixels output by the adjustment module, and to perform overdrive compensation on the pixels in the first set of pixels based on the first compensation algorithm, and to perform overdrive compensation on the pixels in the second set of pixels based on the second compensation algorithm.

9. An electronic device, characterized in that, Includes the image processing circuit as described in any one of claims 1-8.

Images