Identifying dependencies in control sequences for execution on hardware accelerators

Abstract

Computer-implemented methods, systems, and computer program products for identifying dependencies in control sequences are provided. The computer-implemented method includes receiving a control block including a first error dependency (EDEP) level, maintaining the first EDEP level, and determining whether the received control block is successfully executed. Embodiments also include receiving a subsequent control block including a second EDEP level, comparing the first EDEP level and the second EDEP level, and providing the subsequent control block for execution based at least in part on the successful execution of the received control block and on the second EDEP level being less than or equal to the first EDEP level.

Description

Background Technology

[0001] This invention relates to computer hardware, and more particularly to identifying dependencies in control sequences used for execution on hardware accelerators.

[0002] Different acceleration techniques can be used to improve the efficiency of performing different computing tasks. Hardware acceleration achieves efficiency improvements by offloading different tasks to highly specialized hardware such as graphics processing units (GPUs) and application-specific integrated circuits (ASICs). Software acceleration techniques are designed to maximize the system functionality executed in software before offloading other functions to external hardware. Summary of the Invention

[0003] Embodiments of the present invention relate to a computer-implemented method for identifying dependencies in a control sequence for execution on a hardware accelerator. Non-limiting examples of the computer-implemented method include: receiving a control block including a first Error Dependency Prediction (EDEP) level; maintaining the first EDEP level; and determining whether the received control block has been successfully executed. The computer-implemented method further includes: receiving a subsequent control block including a second EDEP level; comparing the first EDEP level and the second EDEP level; and providing a subsequent control block for execution based at least in part on the successful execution of the received control block and based on the second EDEP level being less than or equal to the first EDEP level. Embodiments of the invention are also provided for systems and computer program products for identifying dependencies in a control sequence for execution on a hardware accelerator.

[0004] Additional technical features and benefits are achieved through the technology of this invention. Embodiments and aspects of the invention are described in detail herein, and these embodiments and aspects are considered part of the claimed subject matter. For a better understanding, reference is made to the specific embodiments and accompanying drawings. Attached Figure Description

[0005] The details of the exclusive rights described herein are specifically pointed out and clearly claimed in the claims at the conclusion of this specification. The foregoing and other features and advantages of embodiments of the invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0006] Figure 1 A block diagram of a system according to one or more embodiments of the present invention is depicted;

[0007] Figure 2A and 2B An example control sequence with dependencies is described according to one or more embodiments of the present invention;

[0008] Figure 3A flowchart illustrating a method for identifying dependencies in a control sequence according to one or more embodiments of the present invention is shown; and

[0009] Figure 4 A block diagram of a computer system according to one or more embodiments of the present invention is depicted.

[0010] The figures depicted herein are illustrative. Many variations may be made to the figures or operations described herein without departing from the scope of the invention. For example, actions may be performed in a different order, or actions may be added, deleted, or modified. Furthermore, the term "coupled" and its variations describe a communication path between two elements and do not imply a direct connection between the elements without intervening elements / connections. All such variations are considered part of the specification.

[0011] In the following detailed description of the accompanying drawings and the disclosed embodiments, the different elements shown in the drawings are equipped with two or three numerical reference numerals. With minor exceptions, the leftmost digit of each reference numeral corresponds to the drawing in which its element is first shown. Detailed Implementation

[0012] One or more embodiments of the present invention provide a hardware accelerator that queues a plurality of control block (CB) instructions intended to be executed in a predetermined order. The control blocks may exhibit relationships with previous and subsequent control blocks. If an error occurs during the execution of a control block, it may be necessary to reprocess one or more control blocks to correctly complete the job or task.

[0013] Modern systems do not provide a mechanism for tracking dependencies between control blocks that need to be executed in a predetermined order or in another independent order. Even when a control block fails (and one or more subsequent control blocks depend on it), the subsequent dependent control blocks are still processed. Because the sequence of control blocks is executed to include the failed control block, the entire sequence of control blocks must be requeued into the control block store queue and re-executed. This results in a performance penalty. Furthermore, if another independent sequence of control blocks is queued after the sequence that includes the failed control block, that independent sequence must still wait for the complete processing of the control blocks that depend on the failed control block, also causing delays.

[0014] One or more embodiments of the present invention address one or more of the aforementioned disadvantages of the prior art by providing a mechanism in which dependencies between sequential flows of control blocks can be identified, such that if a control block fails, the execution unit can automatically suspend processing of any subsequent control blocks based on the failed control block, and then automatically resume execution when there are no longer any dependencies on the control blocks.

[0015] Turn now Figure 1 The diagram generally illustrates a block diagram of a system 100 for identifying dependencies in a control sequence according to one or more embodiments of the present invention. In some embodiments of the invention, system 100 may be implemented in a computing system server 12 in computing node 10, such as... Figure 4 As shown. System 100 includes a main processor 102. The main processor 102 is configured to assign Error Dependency Processing Level (EDEP) to each control block (CB), and the main processor 102 is configured to provide control blocks to a control block storage queue 104. In some embodiments, the main processor 102 may include one or more hardware and / or software instructions for configuration. The hardware may include... Figure 1 The computing node 10 shown comprises one or more elements. Each control block is programmed using an EDEP level allocated from the main processor 102. The EDEP level can be 2 bits long and indicates the hierarchical dependency between control blocks in the control sequence. The EDEP level defines whether a subsequent control block should be executed if the execution of a previous control block in the hierarchical level fails.

[0016] According to one or more embodiments of the present invention, a control block storage queue 104 is configured to store one or more control blocks. When control blocks arrive at the head of the storage queue, they are provided to an EDEP processor 108 according to one or more embodiments of the present invention. The EDEP processor 108 is configured to perform several functions, including but not limited to receiving control blocks from the control block storage queue 104, providing control blocks to an execution unit 110, processing responses from the execution unit 110, providing response words to a response word processor 112, and receiving reset signals from the main processor 102.

[0017] The EDEP processor 108 can be further configured to detect whether a fault has occurred during the execution of a control block at the execution unit 110. Errors may occur for various reasons. For example, an error may occur during execution when a "divide by zero" operation or parity occurs. If an error is detected, the execution unit 110 can provide an indication of such an error to the EDEP processor 108. If an error is detected, the execution unit 110 does not execute each subsequent control block that depends on the faulty control block indicated by the EDEP level. Therefore, when a subsequent control block that depends on the faulty control block is received from the control block storage queue 104 and identified, these control blocks are abended (abend). The control block is not executed, and a response word (RspW) indicating that the control block was not executed is generated.

[0018] The EDEP processor 108 is configured to analyze the EDEP level of received control blocks and maintain the current EDEP level, wherein the EDEP level indicates the correlation between control blocks. In response to determining that an error has occurred, the EDEP processor 108 analyzes the EDEP level of each subsequently received control block to determine whether the control block should be passed to the execution unit 110 for execution.

[0019] For example, if it is determined that a control block with EDEP level = 0 has failed at EDEP processor 108, then all subsequent control blocks with EDEP level = 0 received at EDEP processor 108 do not need to be processed. Therefore, upon receipt, the control block is marked at EDEP processor 108 and is not passed to execution unit 110 for execution. By not executing the control block at EDEP processor 108 in execution unit 110, processing latency is improved because subsequent control blocks are not processed depending on the failure.

[0020] If a control block execution at EDEP level n fails, all subsequent control blocks with EDEP levels less than (<) n will not be executed at execution unit 110. This continues until a control block with an EDEP level greater than or equal to n is encountered. In this case, control block execution resumes until another failed control block is detected.

[0021] The EDEP processor 108 is configured to receive a response word (RspW) from the execution unit 110 and provide it to the response word processor 112 to notify the host processor 102 of the status of the control block. The RspW can indicate successful execution, error, or loss of the control block. It should be understood that the RspW can indicate additional information to the host processor 102.

[0022] In one or more embodiments of the invention, the main processor 102 of system 100 can adjust the EDEP level maintained at the EDEP processor 108 by sending a NULL CB. In a non-limiting example, a NULL CB with EDEP=3 is sent to the EDEP processor, and upon receipt, the EDEP processor 108 is configured to 3. It should be understood that the NULL CB will be executed without error. Alternatively, the host processor 102 can directly provide the CB with EDEP=3 to the EDEP processor 108 to reset the dependency chain. In one instance, when a NULL CB or a reset CB is received at the EDEP processor 108, the EDEP level maintained at the EDEP processor 108 can be initialized to the highest EDEP level and will be reset to the highest level when a new dependency chain is identified.

[0023] like Figure 2A and Figure 2BAs shown, an example of an erroneous dependency is provided for identifying dependencies in a control sequence among multiple control blocks. Multiple control blocks are illustrated, where one or more control blocks can be used to define a job. Each control block is queued in a specific order into control block storage queue 104 before execution. Each control block may include a job number and an EDEP level. Figure 2A As illustrated in the example of a non-restricted error dependency, two jobs (job 1 and job 2) are represented by multiple control blocks. Job 1 is the first job to be queued into the control block storage queue 104 and provided to the EDEP processor 108, followed by job 2, which is the second job. Each job (job 1 and job 2) includes multiple control blocks, and as shown, the rightmost control block includes the highest EDEP level (EDEP level 2), and each subsequent control block includes an EDEP level less than or equal to the EDEP level of the rightmost control block. When a control block reaches the head of the control block storage queue 104, each control block is transmitted to the EDEP processor 108, and if a fault is detected, the EDEP level of the control block is compared with the EDEP level maintained at the EDEP processor 108.

[0024] If the EDEP processor 108 determines that the rightmost control block has failed, each subsequent control block will be flagged. Considering an example where the second control block (job 1, layer 1) with EDEP level = 1 fails, all subsequent jobs / control blocks with EDEP level = 0 will not be executed because they have a lower EDEP level. In another instance, if control block (job 1, layer 2) fails, all subsequent control blocks / jobs with EDEP layer level = 0 will not be executed at execution unit 110. If control block (job 2, layer 1) is executed successfully (without errors), the remaining jobs / control blocks will be executed until the failed control block is detected.

[0025] In another instance of incorrect dependency (such as) Figure 2BIn the diagram, four different jobs (J1, J2, J3, J4) are represented. The first job (J1) is queued in the control block storage queue 104, followed by the subsequent jobs (J2, J3, J4). The first control block of J1 awaiting processing is "Clear Spad" EDEP3, and control blocks J4 MB1 and EDEP1 are the last control blocks awaiting processing. In the case where the rightmost job "Clear Spad" with EDEP level = 3 fails, each control block with EDEP3 is not executed until the next "Clear Spad" VF: 2. That is, the control blocks (J1 preload, J1 MB1, J1 MB2, J2 preload, J2 MB1, J2 MB2, J2 MB3, J2 MB4) are not executed by the execution unit 110 because the rightmost control block "Clear Spad" has failed.

[0026] However, if only the control block (J1 MB1) fails, the next job (J2, MB2) can still be executed. If the control block corresponding to the J1 preloading step fails, then both control blocks (J1 MB1, J1 MB2) will not be executed, but jobs (J2, J3, J4) can continue to be processed.

[0027] See now Figure 3 A flowchart of a method 300 for identifying dependencies in a control sequence according to one or more embodiments is shown. Method 300 can be used in, for example... Figure 1 This method is executed in systems such as System 100 shown. It should be understood that Method 300 can also be executed in other systems, and is not limited to them. Figure 1 The system is shown. Method 300 begins at block 302 and proceeds to block 304, where block 304 provides for receiving control blocks at the Error Dependency Processor 108, wherein the control blocks include a first EDEP level. The EDEP level indicates the dependency between control blocks.

[0028] Box 306 maintains the first EDEP level at EDEP processor 108. EDEP processor 108 maintains the EDEP level of the latest control block, which enables EDEP processor 108 to determine the correlation between control blocks in the control sequence.

[0029] Block 308 determines whether the received control block was successfully executed. The EDEP processor 108 determines whether the control block was successfully executed at the execution unit 110 in response to receiving an instruction or response from the execution unit 110. Block 310 receives subsequent control blocks including a second EDEP level. The EDEP processor 108 receives subsequent control blocks with EDEP levels from the control block storage queue 104.

[0030] Box 312 compares the first EDEP level with the second EDEP level. In one or more embodiments of the invention, if the EDEP level of the received control block is greater than the EDEP level maintained in the EDEP processor 108, the EDEP level is updated. Receiving an EDEP level greater than the maintained EDEP level can indicate that a new sequence of control blocks independent of previous control blocks has been received.

[0031] Box 314 provides subsequent control blocks for execution based at least in part on the successful execution of the received control block and on the premise that the second EDEP level is less than or equal to the first EDEP level. If no fault or error is detected during the execution of a control block, subsequent control blocks may be provided to execution unit 110 and executed by execution unit 110. However, if a fault is detected in a control block, subsequent control blocks dependent on the faulty control block will not be provided to execution unit 110 and will not be executed by execution unit 110. Those control blocks identified as dependent on the faulty control block based on the EDEP level will not be processed, and the next control block not dependent on the faulty control block, also indicated by the EDEP level, may be processed. Therefore, the processing of other control blocks is no longer delayed by the processing of control blocks dependent on the faulty control block.

[0032] Method 300 ends in box 316. It should be understood that Method 300 is not intended for users... Figure 3 The steps shown are not limited to those described herein, but may include additional steps and / or different sequences of steps to identify dependencies in the control sequence according to one or more embodiments of the invention.

[0033] See now Figure 4 The diagram illustrates an example of a computing node. Computing node 10 is merely one instance of a suitable computing node and is not intended to impose any limitation on the scope of use or functionality of the embodiments of the invention described herein. In any case, computing node 10 is capable of implementing and / or performing any of the functions set forth above.

[0034] Within compute node 10, there exists a computer system / server 12 that can operate alongside many other general-purpose or special-purpose computing system environments or configurations. Examples of known computing systems, environments, and / or configurations that may be suitable for computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the aforementioned systems or devices.

[0035] The computer system / server 12 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. The computer system / server 12 can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside in local and remote computer system storage media, including memory storage devices.

[0036] like Figure 4 As shown, the computer system / server 12 in compute node 10 is illustrated in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to, one or more processors or processing units 11, system memory 28, and a bus 18 that couples the various system components, including the system memory 28, to the processor 16.

[0037] Bus 18 represents any one or more of several types of bus architectures, including memory buses or memory controllers, peripheral buses, accelerated graphics ports, and processor or local buses using any of the various bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0038] Computer system / server 12 typically includes a variety of computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, and includes volatile and non-volatile media, removable and non-removable media.

[0039] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be provided for reading from and writing to a non-removable non-volatile magnetic medium (not shown, and generally referred to as a "hard disk drive"). Although not shown, disk drives for reading from or writing to removable non-volatile disks (e.g., "floppy disks") and optical disk drives for reading from or writing to removable non-volatile optical disks (e.g., CD-ROMs, DVD-ROMs, or other optical media) may be provided. In such cases, each may be connected to bus 18 via one or more data media interfaces. As will be further described and illustrated below, memory 28 may include at least one program product having at least one set of program modules configured to perform embodiments of the invention.

[0040] A program / utility 40 having a set (at least one) of program modules 42, along with an operating system, one or more applications, other program modules, and program data, may be stored in memory 28 by way of example, not limitation. Each or some combination of the operating system, one or more applications, other program modules, and program data may include an implementation of a network environment. Program modules 42 typically perform functions and / or methods as described herein in embodiments of the invention.

[0041] The computer system / server 12 can also communicate with one or more external devices 14 (such as a keyboard, pointing device, display 24, etc., enabling users to interact with the computer system / server 12, and / or any device that enables the computer system / server 12 to communicate with one or more other computing devices (e.g., a network card, modem, etc.)). This communication can be performed via input / output (I / O) interface 22. Furthermore, the computer system / server 12 can communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet), via network adapter 20. As shown, network adapter 20 communicates with other components of the computer system / server 12 via bus 18. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with the computer system / server 12. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0042] The technique described in this paper improves upon existing technologies by reducing the processing speed of control blocks in a control sequence by decreasing the latency of processing unrelated control blocks. The EDEP level allows the system to discard control blocks that depend on faulty control blocks. Control blocks that do not depend on faulty control blocks are allowed to be processed, while control blocks that depend on faulty control blocks are not processed due to latency issues.

[0043] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the invention.

[0044] Computer-readable storage media can be tangible devices that can retain and store instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disk drives, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory.

[0045] (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital universal disc (DVD), memory stick, floppy disk, mechanical encoding device (e.g., a punched card or a raised structure in a slot with instructions recorded thereon), and any suitable combination of the foregoing. Computer-readable storage media as used herein should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0046] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0047] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information from the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention.

[0048] This document describes various aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0049] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that these instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner, such that the computer-readable storage medium storing the instructions comprises an article of manufacture containing instructions that implement aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0050] These computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, thereby causing the instructions to be executed on the computer, other programmable apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0051] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than indicated in the figures. For example, depending on the functions involved, two consecutively shown blocks may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0052] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable those skilled in the art to understand the embodiments described herein.

[0053] This document describes various embodiments of the invention with reference to the accompanying drawings. Alternative embodiments of the invention may be devised without departing from its scope. In the following description and drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are illustrated between elements. Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the aspects of the invention herein are limiting. Therefore, the connection of entities may refer to direct or indirect connections, and the positional relationship between entities may be direct or indirect positional relationships. Furthermore, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process with additional steps or functions not described in detail herein.

[0054] The following definitions and abbreviations will be used to interpret the claims and specification. As used herein, the term "comprising" is used in conjunction with other terms.

[0055] The terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains,” or “containing,” or any other variation thereof, are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0056] Furthermore, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or design described herein as "exemplary" need not be construed as preferred or advantageous over other implementations or designs. The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "multiple" can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" can include both indirect "connection" and direct "connection."

[0057] The terms “about,” “substantially,” “roughly,” and their variations are intended to include the degree of error associated with a measurement based on a specific quantity of equipment available at the time of application submission. For example, “about” could include a range of ±8%, 5%, or 2% of a given value.

[0058] For the sake of brevity, this document may or may not describe in detail conventional techniques associated with the manufacture and use of aspects of the invention. Specifically, various aspects of computing systems and specific computer programs used to implement the different technical features described herein are well known. Consequently, for the sake of brevity, many conventional implementation details are only briefly mentioned or omitted entirely herein, without providing well-known system and / or process details.

Claims

1. A computer-implemented method for identifying dependencies in a control sequence, the computer-implemented method comprising: Receive a control block at the processor that includes the first error dependency EDEP level; The first EDEP level is maintained at the processor; Determine whether the received control block was successfully executed; Receive subsequent control blocks including the second EDEP level; Compare the first EDEP level and the second EDEP level; and At least in part based on the successful execution of the received control block, and based on the second EDEP level being less than or equal to the first EDEP level, subsequent control blocks are provided for execution.

2. The computer-implemented method according to claim 1, wherein, The EDEP level defines the hierarchical dependencies between control block sequences.

3. The computer-implemented method according to claim 1, wherein, The determination includes receiving an indication of successful execution of the control block from the execution unit.

4. The computer-implemented method of claim 3, further comprising transmitting a response word from the processor to a host processor, wherein, The response word indicates whether the control block was successfully executed at the execution unit.

5. The computer-implemented method of claim 1, further comprising resetting the EDEP level maintained at the processor in response to receiving a reset command from the host processor.

6. The computer-implemented method of claim 1, further comprising initializing the EDEP level maintained at the processor to an initial value.

7. The computer-implemented method of claim 1, further comprising marking additional subsequent control blocks at the processor based at least in part on the EDEP level of the faulty control block.

8. The computer-implemented method according to claim 1, further comprising: If the EDEP level of another subsequent control block exceeds the maintained EDEP level, then the other subsequent control block is provided to the execution unit.

9. A system for identifying dependencies in a control sequence executed on a hardware accelerator, the system comprising: The host processor is configured to assign the Error Dependency EDEP level to the control block; A control block storage queue is configured to store the control blocks; as well as The EDEP processor is configured as follows: Receives a control block including the first EDEP level; Maintain EDEP level 1; Determine whether the received control block was successfully executed; Receive subsequent control blocks including the second EDEP level; Compare the first EDEP level and the second EDEP level; and At least in part based on the successful execution of the received control block, and based on the second EDEP level being less than or equal to the first EDEP level, subsequent control blocks are provided for execution.

10. The system according to claim 9, wherein, The EDEP level defines the hierarchical dependencies between control block sequences.

11. The system of claim 9, further comprising an execution unit configured to provide the EDEP processor with an indication of successful execution of the control block.

12. The system according to claim 11, wherein, The EDEP processor is further configured to transmit a response word to the host processor, wherein the response word indicates whether the control block was successfully executed at the execution unit.

13. The system according to claim 9, wherein, The host processor is further configured to reset the EDEP level maintained at the EDEP processor in response to receiving a reset command from the host processor.

14. The system according to claim 9, wherein, The host processor is further configured to initialize the EDEP level maintained at the EDEP processor to an initial value.

15. The system according to claim 9, wherein, The EDEP processor is further configured to flag additional subsequent control blocks based at least in part on the EDEP level of the faulty control block.

16. The system according to claim 9, wherein, The EDEP processor is further configured to provide the additional subsequent control block to the execution unit if the EDEP level of the additional subsequent control block exceeds the maintained EDEP level.

17. A computer program product for identifying dependencies in a control sequence executed on a hardware accelerator, the computer program product comprising: A computer-readable storage medium having first program instructions stored on the computer-readable storage medium, the first program instructions being executable by a processor to cause the processor to: Receive a control block including the first error dependency EDEP level; Maintain EDEP level 1; Determine whether the received control block was successfully executed; Receive subsequent control blocks including the second EDEP level; Compare the first EDEP level and the second EDEP level; and At least in part based on the successful execution of the received control block, and based on the second EDEP level being less than or equal to the first EDEP level, subsequent control blocks are provided for execution.

18. The computer program product according to claim 17, wherein, The determination includes receiving an indication of successful execution of the control block from the execution unit.

19. The computer program product according to claim 17, wherein, The instructions can be further executed by the processor to enable the processor to flag additional subsequent control blocks, at least in part, based on the EDEP level of the faulty control block.

20. The computer program product according to claim 17, wherein, The instructions can be further executed by the processor to enable the processor to provide the additional subsequent control block to the execution unit if the EDEP level of the additional subsequent control block exceeds the maintained EDEP level.

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