Stackable multiphase power stage controller with current matching

Abstract

A power stage controller (106A) includes a multiphase pulse control circuit (124), a current sense circuit (204), a comparator (116), an error amplifier (108), and a mode controller (135). The mode controller (135) includes a mode control input (136) and a summing circuit (210). The summing circuit (210) has a first summing circuit input (214) coupled to an error amplifier output (114), a second summing circuit input (212), and a summing circuit output (216) coupled to a first comparator input (118). The mode controller (135) is configured to select one of a primary controller mode or a secondary controller mode in response to a mode control voltage at the mode control input (136), bypass the summing circuit (210) in response to selection of the primary controller mode, and enable the summing circuit (210) in response to selection of the secondary controller mode.

Description

Background Technology

[0001] The proliferation of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are also being commercialized. An example IC product used in electronic devices is a power stage controller. One example power stage controller provides multiphase control signals. As electronic devices (such as communication equipment and servers) demand higher currents, the number of phases required to support these higher currents also increases. Furthermore, as the number of supported phases increases, the number of pins on the power stage controller also increases, leading to a larger package size. Efforts to support higher currents and associated phases are ongoing. Summary of the Invention

[0002] In at least one example, a power stage controller includes a multiphase pulse control circuit having a control input and a multiphase pulse output, each of the multiphase pulse outputs being adapted to be coupled to a corresponding switching control input of a corresponding power stage. The power stage controller also includes a current sensing circuit having a current sensing input and a current sensing output, each of the current sensing inputs being adapted to be coupled to a corresponding current sensing terminal of a corresponding power stage, and the current sensing circuit being configured to provide a combined current sensing voltage at the current sensing output in response to a current sensing voltage at the current sensing input. The power stage controller also includes a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being configured to receive a feedback voltage, the second comparator input being coupled to the first current sensing output, and the comparator output being coupled to the control input. The power stage controller also includes an error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output, the error amplifier being configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input. The power stage controller also includes a mode controller with mode controller inputs and a summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output. The first summing circuit input is coupled to an error amplifier output, and the summing circuit output is coupled to a first comparator input. The mode controller is configured to: select either a primary controller mode or a secondary controller mode in response to a mode control voltage at the mode controller input; bypass the summing circuit in response to the selection of the primary controller mode; and enable the summing circuit in response to the selection of the secondary controller mode.

[0003] In another example, a controller for a multiphase converter includes a main controller circuit having a first main controller input, a second main controller input, a current-sensing output terminal, and an error amplifier output terminal. The first main controller input is adapted to be coupled to an output voltage terminal of the multiphase converter, and the second main controller input is adapted to be coupled to a reference voltage terminal. The controller also includes a secondary controller circuit having a first controller input coupled to the current-sensing output terminal and a second controller input coupled to the error amplifier output terminal. The secondary controller circuit includes a summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input being coupled to the second controller input. The secondary controller circuit also includes an integrator having a first integrator input, a second integrator input, and an integrator output, the first integrator input being coupled to the first controller input, the second integrator input being configured to receive a combined current-sensing voltage associated with a power stage of the multiphase converter controlled by the secondary controller circuit, and the integrator output being coupled to the second summing circuit input.

[0004] In another example, a system includes a multiphase converter adapted to be coupled to a load. The multiphase converter has: an output voltage terminal; power stages connected in parallel, each power stage having a current-sensing output terminal; and a controller coupled to each power stage. The controller includes: a main controller circuit coupled to some of the power stages and having a first main controller input, a second main controller input, a current-sensing output terminal, and an error amplifier output terminal, the first main controller input being coupled to the output voltage terminal, and the second main controller input being adapted to be coupled to a reference voltage terminal; and a secondary controller circuit coupled to the main controller circuit and coupled to the other power stages and having a first controller input and a second controller input, the first controller input being coupled to the current-sensing output terminal, and the second controller input being coupled to the error amplifier output terminal. Attached Figure Description

[0005] Figure 1 This is a block diagram of a system according to an exemplary embodiment.

[0006] Figure 2 This is a schematic diagram of a power stage controller for a multiphase converter according to an exemplary embodiment.

[0007] Figure 3 This is a schematic diagram of a current-sharing loop circuit system for a power stage controller of a multiphase converter, according to an exemplary embodiment.

[0008] Figure 4 This is a schematic diagram of a power stage controller for a multiphase converter according to an exemplary embodiment.

[0009] Figure 5 It is a timing diagram showing the waveforms of a multiphase converter without the power stage controller.

[0010] Figure 6 It is a timing diagram showing the waveforms of a multiphase converter with the power stage controller. Detailed Implementation

[0011] In this specification, a controller for a multiphase converter includes a main controller circuit configured to provide multiphase pulses to a subset of power stages of the multiphase converter. The multiphase converter also includes one or more sub-controller circuits coupled to the main controller circuit, each sub-controller circuit being configured to provide multiphase pulses to a corresponding subset of power stages of the multiphase converter. In the described embodiments, the main controller circuit and each sub-controller circuit include input terminals, output terminals, and / or components to equalize corresponding current-sensing voltages provided to corresponding control loop comparators of the main controller circuit and each sub-controller circuit. In this way, even if the corresponding current-sensing voltages of the main controller circuit and each sub-controller circuit may differ, the corresponding control loop comparators will receive the same voltage difference. In some exemplary embodiments, each sub-controller circuit includes an integrator configured to compare the average or total current of the main controller circuit and the corresponding sub-controller circuit, resulting in an adjusted turn-off time (TOFF) for each corresponding sub-controller circuit and an equalized current for the corresponding control loop of the main controller circuit and each sub-controller circuit.

[0012] Without limiting other embodiments, in some exemplary embodiments, the main controller circuit and the secondary controller circuit have the same controller topology, wherein the controller circuit topology can be configured in either a main controller mode or a secondary controller mode. Therefore, the controller for the multiphase converter includes stackable controller integrated circuits (ICs), wherein one controller IC is configured as the main controller circuit, while the other controller ICs are configured as secondary controller circuits. As used herein, "stackable" means that an increasing number of controller ICs of the multiphase converter can be used as needed to support an increasing number of power stages and current output to the load. In different exemplary embodiments, the multiphase converter controller includes one main controller IC and N secondary controller ICs, where N is an integer equal to or greater than 1 (e.g., N = 1-10 or greater).

[0013] While the controller topology for a stackable controller IC may vary, a stackable controller IC for a power stage of a multiphase converter may include a multiphase pulse control circuit with a control input and a multiphase pulse output. In this example, each multiphase pulse output is adapted to be coupled to a corresponding switch control input of the corresponding power stage. The stackable controller IC also includes a current sensing circuit with a current sensing input and a current sensing output. Furthermore, each current sensing input is adapted to be coupled to a corresponding current sensing terminal of the corresponding power stage. Additionally, the current sensing circuit is configured to provide a combined current sensing voltage at the current sensing output in response to a current sensing voltage at the current sensing input. The stackable controller IC also includes a comparator with a first comparator input, a second comparator input, and a comparator output. The first comparator input is configured to receive a feedback voltage, the second comparator voltage is coupled to the first current sensing output, and the comparator output is coupled to the control input. The stackable controller IC also includes an error amplifier with a first error amplifier input, a second error amplifier input, and an error amplifier output. The error amplifier is configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input. In some exemplary embodiments, the stackable controller IC further includes a mode controller having a mode controller input and a summing circuit. The summing circuit has a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input being coupled to an error amplifier output. The summing circuit output is coupled to a first comparator input. In operation, the mode controller is configured to: select a primary controller mode or a secondary controller mode in response to a mode control voltage at the mode controller input; bypass the summing circuit in response to the selection of the primary controller mode; and enable the summing circuit in response to the selection of the secondary controller mode.

[0014] In some described embodiments, the control loop of each sub-controller circuit in the controller for the multiphase converter includes an integrator to equalize the current-sensing voltages supplied to the corresponding control loop comparators of the main controller circuit and the sub-controller circuits. This exemplary embodiment achieves an overall improvement in the reliability of the multiphase converter (because all phases will have the same current) without a significant increase in controller size or bill of materials (BOM). Furthermore, the operating frequency of the main controller circuit and each sub-controller circuit remains unchanged. Additionally, extra compensation circuitry or external devices are avoided. Other controller topologies are also possible, varying in complexity, cost, and benefits.

[0015] Figure 1 This is a block diagram of a system 100 according to an exemplary embodiment. Figure 1In the example, system 100 is a communication device or server device having a load 194 (e.g., one or more processors and / or other components) powered by a multiphase converter 102. As shown, the multiphase converter 102 includes a controller 104 coupled in parallel with power stages 190A-190N, wherein a power supply 196 provides an input voltage (VIN) at a VIN terminal 197 coupled to the power stages 190A-190N and the controller 104 (e.g., VIN is received at a VIN input terminal 198 of the controller 104 or a corresponding controller circuit). At the output of each power stage 190A-190N is a corresponding inductor (L_A to L_N), each of L_A to L_N having a corresponding first side coupled to the corresponding power stage and a corresponding second side coupled to the output terminal 192. As shown, system 100 includes an output capacitor (COUT) connected in parallel with the load 194 between the output terminal 192 and ground 195. Ground 195 is also coupled to components of the multiphase converter 102.

[0016] exist Figure 1 In the example, controller 106 includes a main controller circuit 106 and secondary controller circuits 150 and 151A-151M, wherein the main controller circuit 106 provides pulses (pulse subsets CP_A to CP_N) to a corresponding subset of power stages 190A-190N, and wherein each of the secondary controller circuits 150 and 151A-151M provides a corresponding pulse (corresponding pulse subsets CP_A to CP_N) to another corresponding subset of power stages 190A-190N. The pulses CP_A to CP_N provided to power stages 190A-109N control the corresponding switches of power stages 190A-109N.

[0017] As shown in the figure, the main controller circuit 106 includes a multiphase pulse control (labeled "TON / TOFF control") circuit 124 having a control input 134 and multiphase pulse outputs 132A-132M. In operation, the multiphase pulse control circuit 124 controls the on-time (TON) and off-time (TOFF) of pulses 133A-133M supplied to a corresponding subset of power stages 190A-190N. In some exemplary embodiments, each of the multiphase pulse outputs 132A-132M is adapted to couple to a corresponding subset of the switching control inputs 191A-191N of the corresponding subset of power stages 190A-190N. In some exemplary embodiments, the control input 134 is a first control input, and the multiphase pulse control circuit 124 also includes a second control input 126, a third control input 128, and a fourth control input 130. In these exemplary embodiments, the second control input 126 is configured to receive VOUT from the output node 192. Furthermore, the third control input 128 is configured to receive VIN from the VIN terminal 197. Additionally, the fourth control input 130 is configured to receive a ramp voltage (RAMP) from a RAMP source (not shown).

[0018] Reference Figure 2 In an exemplary embodiment, the main controller circuit (e.g., main control circuit 106) further includes a current sensing circuit having current sensing inputs 206A-206N and a current sensing output 208 (see, for example...). Figure 2 The current sensing circuit 204 in the power stage 190A-190N is adapted to couple to a corresponding subset of the current sensing terminals 193A-193N of the corresponding subset of the power stage 190A-190N, and the current sensing circuit is configured to respond to the current sensing voltage at the current sensing inputs 206A-206N. Figure 1 A subset of CS_A to CS_N in the dataset, or Figure 2 CSP1_M to CSPn_M in the current sensing output 208 provide the average current sensing voltage or the total current sensing voltage. Figure 2 (VISUM_M in the text).

[0019] Reference Figure 1 and Figure 2 The main controller circuit 106 also includes a pulse width modulation (PWM) comparator 116, which has a first comparator input 118, a second comparator input 120, and a comparator output 122. The first comparator input 118 is configured to receive a feedback voltage (e.g., Figure 2The second comparator input is coupled to the current sensing output 208, and the comparator output 122 is coupled to the control input 134. The PWM comparator 116 is configured to provide a voltage 123 at the comparator output 122 in response to a feedback voltage or error voltage 115 at the first comparator input 118 and a current sensing voltage 121 at the second comparator input 120. The main controller circuit 106 also includes an error amplifier or integrator 108 having a first error amplifier or integrator input 110, a second error amplifier or integrator input 112, and an error amplifier or integrator output 114. The error amplifier or integrator 108 is configured to provide an error voltage 115 at the error amplifier or integrator output 114 in response to a first voltage 111 at the first error amplifier or integrator input 110 and a second voltage 113 at the second error amplifier or integrator input 113. In some examples, the first voltage 111 is the output voltage (VOUT) at output node 192, while the second voltage 113 is a reference voltage provided by reference voltage terminal 107 and an associated reference voltage source.

[0020] The main controller circuit 106 also includes a mode controller input 136 and a summing circuit 210 (see, for example, see...). Figure 2 The mode controller (labeled "M / S") 135 is a summing circuit 210. The summing circuit 210 has a first summing circuit input 212, a second summing circuit input 214, and a summing circuit output 216. The first summing circuit input 212 is coupled to the error amplifier or integrator output 114, and the summing circuit output 216 is coupled to a first comparator input 118. In operation, the mode controller 135 is configured to select either a master controller mode or a secondary controller mode in response to a mode control voltage 137 at the mode controller input 136 (e.g., provided by the mode control pin or terminal 138). The mode control voltage 137 is selectable, for example, by the system designer. The mode controller 135 is also configured to bypass the summing circuit 210 in response to the selection of the master controller mode (causing the first comparator input 118 to receive an error voltage 115 from the error amplifier or integrator output 114). The mode controller 135 is also configured to enable the summing circuit 210 in response to the selection of the sub-controller mode (causing the first comparator input 118 to receive voltage from the summing circuit output 216).

[0021] exist Figure 1In an exemplary embodiment, when the master controller mode is selected, the mode controller 135 also outputs the error voltage 115 from the mode controller output 140 to the error amplifier output terminal 142. In other exemplary embodiments, regardless of the selected mode, the error voltage 115 is provided to the error amplifier output terminal 142 (e.g., the error amplifier output 114 is coupled directly or via the mode controller 135 to the error amplifier output terminal 142). In some exemplary embodiments, the master controller circuit 106 is also configured to sense the voltage (e.g., from the average or total current sense voltage) Figure 2 The current sensing circuit 204 in the middle (VISUM_M) outputs current from the current sensing output terminal (e.g., Figure 2 The current sensing output terminal 209 in the middle is output to each of the secondary controller circuits 150 and 151A-151M.

[0022] In some exemplary embodiments, the secondary controller circuit 150 is configured to receive an error voltage 115 and an average or total current sensing voltage (e.g., from the primary controller circuit 106). Figure 2 (VISUM_M in the text). Figure 1 In one example, the secondary controller circuit 150 includes a multiphase pulse control (labeled "TON / TOFF control") circuit 170 having a control input 168 and multiphase pulse outputs 178A-178M. In operation, the multiphase pulse control circuit 170 controls the TON and TOFF of pulses 179A-179M supplied to a corresponding subset of power stages 190A-190N. In some exemplary embodiments, each of the multiphase pulse outputs 179A-179M is adapted to couple to a corresponding subset of switching control inputs 191A-191N of the corresponding subset of power stages 190A-190N. In some exemplary embodiments, control input 168 is a first control input, and the multiphase pulse control circuit 170 also includes a second control input 172, a third control input 174, and a fourth control input 176. In these exemplary embodiments, the second control input 172 is configured to receive VOUT from output node 192. Furthermore, the third control input 174 is configured to receive VIN from the VIN terminal 197. Additionally, the fourth control input 176 is configured to receive RAMP from a RAMP source (not shown).

[0023] Reference Figure 2 In an exemplary embodiment, the secondary controller circuit (e.g., secondary control circuit 150) further includes a current sensing circuit having current sensing inputs 226A-226N and a current sensing output 228 (e.g., see [link to relevant documentation]). Figure 2The current sensing circuit 224 is configured to respond to the current sensing voltage at the current sensing inputs 226A-226N. Each current sensing input 226A-226N is adapted to couple to a corresponding subset of the current sensing terminals 193A-193N of the corresponding subset of the power stages 190A-190N. Furthermore, the current sensing circuit 224 is configured to respond to the current sensing voltage at the current sensing inputs 226A-226N. Figure 1 A subset of CS_A to CS_N in the dataset, or Figure 2 CSP1_S to CSPn_S in the figure provide the total or average current sensing voltage at the current sensing output 228. Figure 2 (VISUM_S in the text).

[0024] Reference Figure 1 and Figure 2 The secondary controller circuit 150 also includes a PWM comparator 160 having a first comparator input 162, a second comparator input 164, and a comparator output 166. The first comparator input 162 is configured to receive a feedback voltage, the second comparator input 164 is coupled to a current sensing output 228, and the comparator output 166 is coupled to a control input 168. The secondary controller circuit 150 also includes an error amplifier or integrator 152 having a first error amplifier or integrator input 154, a second error amplifier or integrator input 156, and an error amplifier or integrator output 158. The error amplifier or integrator 152 is configured to provide an error voltage 159 at the error amplifier output 158 ​​in response to a first voltage 155 at the first error amplifier or integrator input 154 and a second voltage 157 at the second error amplifier or integrator input 156. In some examples, the first voltage 155 is generated by the current sensing circuit of the main controller circuit 106 (e.g., Figure 2 The average or total current sensing voltage (e.g., in the current sensing circuit 204) provided by the current sensing circuit 204) Figure 2 The second voltage 157 is received by the current sensing circuit of the secondary controller circuit 150 (e.g., current sensing input terminal 240), and is also received by the current sensing circuit of the secondary controller circuit 150. Figure 2 The average or total current sensing voltage (e.g., in the current sensing circuit 224) provided by the current sensing circuit 224) Figure 2 (VISUM_S in the text).

[0025] The secondary controller circuit 150 also includes a mode controller input 182 and a summing circuit 230 (see, for example, see...). Figure 2The mode controller (labeled "M / S") 180. The summing circuit 230 has a first summing circuit input 232, a second summing circuit input 234, and a summing circuit output 236. The first summing circuit input 232 is coupled to an error amplifier or integrator output 158, and the summing circuit output 236 is coupled to a first comparator input 162. In operation, the mode controller 180 is configured to select either a master controller mode or a secondary controller mode in response to a mode control voltage 183 at the mode controller input 182 (e.g., provided by a mode control pin or terminal 188). The mode control voltage 183 is selectable, for example, by the system designer. The mode controller 180 is also configured to bypass the summing circuit 230 in response to the selection of the master controller mode. The mode controller 180 is also configured to enable the summing circuit 230 in response to the selection of the secondary controller mode.

[0026] In some exemplary embodiments, additional secondary controller circuits 151A-151M are present, each of which relates to a topology and operation similar to that described for secondary controller circuit 150. In such examples, each of the secondary controller circuits 151A-151M is configured to provide a corresponding subset of pulses CP_A to CP_N to a corresponding subset of power stages 190A-190N. For the multiphase converter 102, the number of controller circuits is adjustable to support the required number of power stages supplying current to load 194 at a target VOUT.

[0027] Without limiting other options, the main controller circuit 106 and each of the secondary controller circuits 150 and 151A-150M have the same topology, wherein the input terminals (e.g., terminals 218, 138, 240), output terminals (e.g., terminals 209 and 142), and / or components enable the corresponding control loop comparators (e.g., ...) provided to the main controller circuit 106 and each of the secondary controller circuits 150 and 151A-151M to... Figure 1 The corresponding current-sensing voltages of comparators 116 and 160 in the main controller circuit are balanced. In this way, even if the corresponding current-sensing voltages of the main controller circuit and each secondary controller circuit are different, the corresponding control loop comparators will receive the same voltage difference. As described herein, each of the secondary controller circuits 150 and 151A-151M includes an error amplifier or integrator (e.g., ...). Figure 1 The error amplifier or integrator 152 is configured to compare the average or total current of the main controller circuit and the corresponding secondary controller circuits, resulting in an adjusted TOFF for each secondary controller circuit and a balanced current for the corresponding control loops of the main controller circuit 106 and each secondary controller circuit 150 and 151A-151M.

[0028] Figure 2 This is an example of a method for a multiphase converter (e.g., according to an exemplary embodiment). Figure 1 A schematic diagram of the controller 200 for the multiphase converter 102 in the figure. As shown, the controller 200 includes a main controller circuit 106A ( Figure 1 Example of main controller circuit 106), secondary controller circuit 150A ( Figure 1 Examples of secondary controller circuit 150 and secondary controller circuits 151A-151M. Figure 2 In the example, the main controller circuit 106A includes many features for... Figure 1 The same components described in the main controller circuit 106 include an error amplifier or integrator 108 and associated inputs / outputs, a PWM comparator 116 and associated inputs / outputs, a multiphase pulse control circuit 124 and associated inputs / outputs, and a mode controller 134 and associated inputs / outputs. Additionally, the main controller circuit 106A includes a current sensing circuit 204 with current sensing inputs 206A-206N and a current sensing output 208.

[0029] exist Figure 2 In the example, a main controller circuit 106A is shown that includes a current sensing output terminal 209 coupled to the current sensing output 208, along with some additional inputs, outputs, and / or components. The main controller circuit 106A includes a fourth control input 130 coupled to the multiphase pulse control circuit 124 and a ramp terminal 203 configured to provide a ramp voltage. The main controller circuit 106A includes an error voltage input terminal 218 configured to receive an error voltage from another controller circuit (e.g., if the main controller circuit 106A is in a secondary controller mode). The main controller circuit 106A includes a summing circuit 210 having a first summing circuit input 212, a second summing circuit input 214, and a summing circuit output 216, wherein the summing circuit 210 is part of the mode controller 134. Figure 2 The mode controller 134 includes a mode controller input 136, which is a first mode controller input. The mode controller 134 also includes a second mode controller input 217 and a third mode controller input 219. As shown, the second mode controller input 217 is coupled to the error amplifier or integrator output 114, while the third mode controller input 219 is coupled to the error voltage input terminal 218. In other examples, the mode controller 134 is separate from the summing circuit 210, where logic bypasses or enables the summing circuit 210 based on a selected mode identified by the mode controller 134. The main controller circuit 106A includes a reference voltage terminal 215 configured to provide a reference voltage (VDAC) to the first error amplifier or integrator input 110. In operation, the main controller circuit 106A performs operations targeting... Figure 1 The operation of the main controller circuit 106 is described in the diagram.

[0030] exist Figure 2 In the example, the secondary controller circuit 150A includes a current sensing output terminal 229 coupled to the current sensing output 228. Additionally, the secondary controller circuit 150A includes a fourth control input 176 coupled to the multiphase pulse control circuit 170 and configured to provide a ramp voltage (RAMP) terminal 223. The secondary controller circuit 150A includes a slave control input configured to receive signals from the primary controller circuit (e.g., ...). Figure 2 The main controller circuit 106A receives the error voltage input terminal 238. The secondary controller circuit 150A includes a summing circuit 230 having a first summing circuit input 232, a second summing circuit input 234, and a summing circuit output 236, wherein the summing circuit 230 is part of the mode controller 180. Additionally, for Figure 2 The mode controller 180 includes a mode controller input 182, which is a first mode controller input. The mode controller 180 also includes a second mode controller input 237 and a third mode controller input 239. As shown, the second mode controller input 237 is coupled to an error amplifier or integrator output 158, while the third mode controller input 239 is coupled to an error voltage input terminal 238. In other examples, the mode controller 180 is separate from the summing circuit 230, where logic bypasses or enables the summing circuit 230 based on a selected mode identified by the mode controller 180. The secondary controller circuit 150A includes a current sensing input terminal 240, which is configured to receive an average or total sensed current voltage (e.g., ...) from the current sensing output terminal 209 of the main controller circuit 106A. Figure 2 (VISUM_M in the original text). In operation, the secondary controller circuit 150A executes the action targeting... Figure 1 The operation of the secondary controller circuit 150 is described in the text. Figure 2 The secondary controller circuits 151A-151M are similar to the secondary controller circuit 150A and are also configured to execute actions targeting... Figure 1 The operation of the secondary controller circuit 150 is described in the text.

[0031] Without restricting other options Figure 2 The main controller circuit 106A and each of the secondary controller circuits 150A and 151A-150M have the same topology, wherein the input terminals (e.g., terminals 218, 138, 215, 240), output terminals (e.g., terminals 209, 142, and 229), and / or other components enable the corresponding control loop comparators (e.g., ...) provided to the main controller circuit 106A and each of the secondary controller circuits 150A and 151A-150M to provide... Figure 1The corresponding current-sensing voltages of comparators 116 and 160 in the main controller circuit are balanced. In this way, even if the corresponding current-sensing voltages of the main controller circuit and each secondary controller circuit may differ, the corresponding control loop comparators will receive the same voltage difference. As described herein, each of the secondary controller circuits 150A and 151A-151M includes an error amplifier or integrator (e.g., Figure 1 The error amplifier or integrator 152 is configured to compare the average or total current of the main controller circuit and the corresponding secondary controller circuit, resulting in an adjusted TOFF for each secondary controller circuit and a balanced current for the corresponding control loops of the main controller circuit 106A and each secondary controller circuit 150A and 151A-151M.

[0032] Figure 3 This is an example of a method for a multiphase converter (e.g., according to an exemplary embodiment). Figure 1 A schematic diagram of a current-sharing loop circuit system 300 of a multiphase converter 102 in a power stage (e.g., a power stage controller). Figure 1 Controller 104 or Figure 2 The main controller circuit of the controller 200 in the middle (e.g., Figure 1 The main controller circuit 106 or Figure 2 The main controller circuit 106A and each secondary controller circuit (e.g., Figure 1 Each of the secondary controller circuits 150 and 151A-151M or Figure 2 Each of the secondary controller circuits 150A and 151A-151M operates in parallel. During operation, the current-sharing loop circuit system 300 equalizes the current across all phases, wherein the bandwidth of the current-sharing loop circuit system 300 is significantly lower than that of the current-mode control loop (e.g., each primary controller circuit 106 and each secondary controller circuit 150 and 151A-151M includes a current-mode control loop). More specifically, the current-sharing loop circuit system 300 compares the individual current-sensing voltages with the average current across all phases and adjusts TON.

[0033] As shown in the figure, the current-sharing loop circuit system 300 includes a configuration to receive current-sensing voltages (e.g., from a corresponding subset of power stages (e.g., power stages 190A-190N)). Figure 3The current sensing inputs 304A-304F (CSP1-CSP6) are coupled to corresponding delay filters 306A-306F (e.g., 5μs delay filters). The outputs of the delay filters 306A-306F are coupled to an averaging circuit 307 and corresponding multipliers 308A-308F. Each of the corresponding multipliers 308A-308F is configured to multiply the output of the corresponding delay filter 306A-306F by the average current (I) from the averaging circuit 307. AVG The outputs are multiplied. The corresponding outputs from multipliers 308A-308F (labeled as K×(I1-I)) are multiplied. AVG ) to K×(I6-I AVG The input is provided to the corresponding adders 310A-310F to convert K×(I1-I) into the output of the corresponding adders. AVG ) to K×(I6-I AVG A reference voltage (VDAC) is applied. The outputs of the corresponding adders 310A-310F are provided to the non-inverting inputs of the corresponding comparators 312A-312F. The inverting inputs of the corresponding comparators 312A-312F are coupled to the corresponding reference circuits, each with a resistor R. T(ON) and capacitor C T(ON) As shown in the figure, each R T(ON) The first side is coupled to the VIN source or associated terminal, while each R T(ON) The second side is coupled to the inverting input of the corresponding comparator in comparators 312A-312F. Additionally, each C... T(ON) The first side is coupled to the inverting input of the corresponding comparator in comparators 312A-312F, while each C T(ON) The second side is coupled to ground. The outputs of comparators 312A-312F are coupled to PWM output terminals 314A-314F to provide PWM pulses (PWM1-PWMF6). In summary, the main controller circuit and each secondary controller circuit operate to control the slave controller (e.g., Figure 1 The controller 104 in the document outputs a TOFF to the corresponding subset of PWM pulses of the power stage described herein. In parallel with the TOFF control provided by the main controller circuit and each secondary controller circuit, each current-sharing loop circuit system (e.g., for the main controller circuit and each secondary controller circuit) Figure 3 One of the current-sharing loop circuit systems 300 in the system controls the controller (e.g., Figure 1 The controller 104 in the document outputs PWM pulses to the corresponding subset of the power stage described herein.

[0034] Figure 4 This is an example of a method for a multiphase converter (e.g., according to an exemplary embodiment). Figure 1A schematic diagram of the power stage controller 400 of the multiphase converter 102 in the diagram. (Relative to...) Figure 1 , Figure 2 and Figure 3 The power stage controller 400 is an alternative topology to the topology shown. As shown, the power stage controller 400 includes a main controller circuit 401 with a delay filter 402, an integrator 404, a multiplier 406, and a comparator 408. More specifically, the delay filter 402 is configured to receive a current sensing signal (CSP1_m) and output a correlated current sensing signal (I1_m), which is compared with the average current sensing signal (I1_m) of the main controller circuit 401. AVG_M Multiply by 1. The output of integrator 404 is I1_m-I. AVG_M The function is provided to multiplier 406, which is configured to scale the output of integrator 404 using a reference voltage (VDAC). The output of multiplier 406 is coupled to the non-inverting input of comparator 408. Additionally, the inverting input of comparator 408 is coupled to a resistor (R). T(ON) ) and capacitors (C T(ON) The reference circuit for ) is shown in the figure. R T(ON) The first side is coupled to the VIN source or associated terminal, while R T(ON) The second side is coupled to the inverting input of comparator 408. Additionally, C T(ON) The first side is coupled to the inverting input of comparator 408, while C T(ON) The second side is coupled to ground. The output of comparator 408 is a PWM pulse (PWM_m). Figure 4 In this circuit, the circuit system of the main controller circuit 401 (e.g., delay filter 402, integrator 404, multiplier 406, and comparator 408) is repeated for each stage managed by the main controller circuit 401.

[0035] Additionally, the secondary controller circuit 411 includes a delay filter 412, an integrator 414, a multiplier 416, and a comparator 418. More specifically, the delay filter 412 is configured to receive a current sensing signal (CSP1_s) and output a correlated current sensing signal (I1_s), which is compared with the average current sensing signal (I1_s) of the secondary controller circuit 411. AVG_M Multiply by 1. The output of integrator 414 is I1_s - I. AVG_M The function is provided to multiplier 416, which scales the output of integrator 414 using a reference voltage (VDAC). The output of multiplier 416 is coupled to the non-inverting input of comparator 418. Additionally, the inverting input of comparator 418 is coupled to a circuit with R... T(ON) and C T(ON) The reference circuit is shown in the figure. R T(ON)The first side is coupled to the VIN source or associated terminal, while R T(ON) The second side is coupled to the inverting input of comparator 418. Additionally, C... T(ON) The first side is coupled to the inverting input of comparator 408, while C T(ON) The second side is coupled to ground. The output of comparator 418 is a PWM pulse (PWM_s). Figure 4 In this process, the circuitry of the secondary controller circuit 411 (e.g., delay filter 412, integrator 414, multiplier 416, and comparator 418) is repeated for each stage managed by each secondary controller circuit 411.

[0036] Through the topology of the power stage controller 400, the secondary controller circuit 411 can be reused to support additional stages. Additionally, the average current of the integrator and / or high-gain current-sharing loop along its path and the main controller circuit can be shared among all controller circuits or ICs. With this topology, the loop will have two poles at the origin due to the presence of inductors (e.g., one of L_A to L_N) and integrators. Therefore, additional loop compensation will be required. Furthermore, the described power stage controller 400 will change the TON of the IC, which in turn will change the operating frequency between the main controller circuit and the secondary controller circuit. To address this, another frequency control loop will be needed.

[0037] Another option involves using an averaging circuit system, where all phase currents of the main controller circuit and the secondary controller circuits are taken as inputs. The average output can then be provided to a current-sharing loop for both the main controller circuit and each secondary controller circuit. Using this alternative option increases the bill of materials (BOM) / cost. Additionally, the tonnage (TON) will be altered, and due to limited gain, errors may not be eliminated as desired.

[0038] Figure 5 This is a schematic diagram of timing diagram 500 showing the waveforms of a multiphase converter without a described power stage controller. Timing diagram 500 shows the waveforms of VOUT, load current (I_LOAD), main controller circuit current (I_M), and secondary controller circuit current (I_S). As shown, after VOUT reaches the target level, I_M and I_S become offset from each other, which reduces the power level of the multiphase converter (e.g., ...). Figure 1 The stability / efficiency of the multiphase converter 102 under transient conditions (e.g., when I_LOAD transitions from low to high).

[0039] for Figure 5 The timing diagram 500 is assumed to be... Figure 2The controller topology omits or disconnects the error amplifier 152, and applies an offset of approximately 350 μs between the main controller circuit 106A and the control loops of the secondary controller circuits 150A and 151A-151M. The result of this offset is that I_M and I_S become different from each other. This difference in I_M and I_S will cause the main controller circuit and the secondary controller circuits to have different current phases, creating a thermal imbalance between the phases of the main and secondary controller circuits. The difference in I_M and I_S also reduces the reliability of the phases taking higher currents because the robustness of the power stages and / or inductors is reduced. The difference in I_M and I_S also reduces efficiency at lower loads because current flows between the power stages associated with the main controller circuit and each secondary controller circuit, leading to heating losses (e.g., I^2*Ron losses).

[0040] Figure 6 It displays a power stage controller as described (e.g., Figure 1 Controller 104 in, or Figure 2 The timing diagram 600 is a schematic diagram of the waveforms of the multiphase converter (controller 200 in the controller). The timing diagram 600 shows the waveforms of VOUT, I_LOAD, I_M, and I_S. As shown, after VOUT reaches the target level, I_M and I_S are equal for most of the time, which improves the performance of the multiphase converter (e.g., controller 200). Figure 1 The stability / efficiency of the multiphase converter 102 under transient conditions (e.g., when I_LOAD transitions from low to high).

[0041] for Figure 6 The timing diagram 600 is assumed to be... Figure 2 The controller topology includes an error amplifier 152 connected, which applies an offset of approximately 350 μs between the main controller circuit 106A and the control loops of the secondary controller circuits 150A and 151A-151M. Initially, after the offset is applied, I_M and I_S begin to deviate from each other, but the operation of the error amplifier 152 brings I_M and I_S back to the same value. This ensures that the main controller circuit 106A takes the same current phase as each of the secondary controller circuits 150A and 151A-151M.

[0042] In this specification, the term "coupled" may cover a connection, communication, or signaling path that brings the functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C, such that device B is controlled by device A via a control signal generated by device A.

[0043] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A power stage controller, comprising: A multiphase pulse control circuit having a control input and multiphase pulse outputs, each of the multiphase pulse outputs being adapted to be coupled to a corresponding switch control input of a corresponding power level; A current sensing circuit having a current sensing input and a current sensing output, each of the current sensing inputs being adapted to be coupled to a corresponding current sensing terminal of a corresponding power stage, and the current sensing circuit being configured to provide a combined current sensing voltage at the current sensing output in response to a current sensing voltage at the current sensing input. A comparator having a first comparator input, a second comparator input, and a comparator output, the comparator being configured to receive a feedback voltage at the first comparator input, the second comparator input being coupled to the current sensing output, and the comparator output being coupled to the control input; An error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output, the error amplifier being configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input; as well as A mode controller having a mode controller input and a summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input being coupled to the error amplifier output, the summing circuit output being coupled to the first comparator input, and the mode controller being configured to: In response to the mode control voltage at the mode controller input, select one of the main controller mode or the secondary controller mode; In response to the selection of the main controller mode, the summing circuit is bypassed; as well as In response to the selection of the sub-controller mode, the summing circuit is enabled.

2. The power stage controller of claim 1, wherein in the master controller mode, the first error amplifier input is adapted to be coupled to the output voltage terminal, the second error amplifier input is adapted to be coupled to the reference voltage, and the first comparator input is configured to receive the error voltage as the feedback voltage.

3. The power stage controller of claim 2, further comprising an error amplifier output terminal coupled to the error amplifier output and configured to provide the error voltage to another power stage controller.

4. The power stage controller of claim 1, wherein in the secondary controller mode, the first error amplifier input is adapted to couple to a current sensing output terminal of another power stage controller, the second error amplifier input is adapted to couple to the current sensing output, and the first comparator input is configured to receive a summed voltage from the summing circuit output in response to: an error voltage provided at the first summing circuit input by another power stage controller in the primary controller mode; and the error voltage at the error amplifier output.

5. The power stage controller of claim 1, further comprising a current sensing output terminal coupled to the current sensing output and configured to provide the combined current sensing voltage at the current sensing output to another power stage controller.

6. The power stage controller of claim 1, wherein the control input is a first control input, the multiphase pulse control circuit has a second control input, a third control input, and a fourth control input, the second control input being coupled to an output voltage terminal, the third control input being coupled to an input voltage terminal, the fourth control input being coupled to a ramp terminal, and the multiphase pulse control circuit being configured to control the multiphase pulse output in response to a voltage at the first control input, an output voltage at the second control input, an input voltage at the third control input, and a ramp voltage at the fourth control input.

7. The power stage controller of claim 1, wherein in the secondary controller mode, the error amplifier is configured to operate as an integrator in the off-time control loop to balance the current of the other power stage controller configured in the primary controller mode with the current of the power stage controller.

8. A controller for a multiphase converter, comprising: The main controller circuit has a first main controller input, a second main controller input, a current sensing output terminal, and an error amplifier output terminal. The first main controller input is adapted to be coupled to the output voltage terminal of the multiphase converter, and the second main controller input is adapted to be coupled to a reference voltage terminal. as well as A secondary controller circuit has a first controller input and a second controller input, the first controller input being coupled to the current sensing output terminal, and the second controller input being coupled to the error amplifier output terminal. The secondary controller circuit includes: A summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, wherein the first summing circuit input is coupled to the second controller input; as well as An integrator having a first integrator input, a second integrator input, and an integrator output, the first integrator input being coupled to the first controller input, the integrator being configured to receive at the second integrator input a combined current-sensing voltage of the power stage of the multiphase converter controlled by the secondary controller circuit, and the integrator output being coupled to the second summing circuit input.

9. The controller of claim 8, wherein the combined current sensing voltage is a first combined current sensing voltage, and the main controller circuit comprises: A multiphase pulse control circuit having a control input and multiphase pulse outputs, each of the multiphase pulse outputs being adapted to be coupled to a corresponding switch control input of a corresponding power stage of the multiphase converter; A current sensing circuit having a current sensing input and a current sensing output, each of the current sensing inputs being adapted to be coupled to a corresponding current sensing output terminal of a corresponding power stage of the multiphase converter, and the current sensing circuit being configured to provide a second combined current sensing voltage at the current sensing output in response to a current sensing voltage at the current sensing input. A comparator having a first comparator input, a second comparator input, and a comparator output, the comparator being configured to receive a feedback voltage at the first comparator input, the second comparator input being coupled to the current sensing output, and the comparator output being coupled to the control input; An error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output, the first error amplifier input being coupled to a first main controller input, the second error amplifier input being coupled to a second main controller input, and the error amplifier being configured to provide an error voltage at the error amplifier output in response to an output voltage at the first error amplifier input and a reference voltage at the second error amplifier input.

10. The controller of claim 8, wherein the summing circuit is a first summing circuit, and the main controller circuit comprises: Second summing circuit; as well as A mode controller, having mode controller inputs and configured as follows: The mode controller selects either the primary controller mode or the secondary controller mode in response to the voltage at the input of the mode controller. In response to the selection of the main controller mode, the second summing circuit is bypassed; as well as In response to the selection of the secondary controller mode, the second summing circuit is enabled.

11. The controller of claim 8, wherein the secondary controller circuit comprises: A multiphase pulse control circuit having a control input and multiphase pulse outputs, each of the multiphase pulse outputs being adapted to be coupled to a corresponding switch control input of a corresponding power stage of the multiphase converter; A current sensing circuit having a current sensing input and a current sensing output, each of the current sensing inputs being adapted to be coupled to a corresponding current sensing output terminal of a corresponding power stage of the multiphase converter, and the current sensing circuit being configured to provide a combined current sensing voltage at the current sensing output in response to a current sensing voltage at the current sensing input. as well as A comparator having a first comparator input, a second comparator input, and a comparator output, the comparator being configured to receive a feedback voltage at the first comparator input, the second comparator input being coupled to the current sensing output, and the comparator output being coupled to the control input.

12. The controller of claim 8, wherein the main controller circuit is part of a first integrated circuit, i.e., a first IC, and the secondary controller circuit is part of a second IC.

13. The controller of claim 8, further comprising a plurality of secondary controller circuits including the secondary controller circuit, each of the plurality of secondary controller circuits having a corresponding primary controller input and a corresponding secondary controller input, each corresponding primary controller input being coupled to the current sensing output terminal, and each corresponding secondary controller input being coupled to the error amplifier output terminal.

14. The controller of claim 13, wherein the main controller circuit is part of a first integrated circuit, i.e., a first IC, and each secondary controller circuit is part of one or more other ICs.

15. An apparatus for controlling a multiphase converter, the apparatus comprising: The first controller circuit includes: A first error amplifier has a feedback input, a reference input, and a first error amplifier output; A first current sensing circuit having a first current sensing output, the first current sensing circuit being configured to generate a first current sensing signal representing a first combined current at the first current sensing output. A first comparator has a first comparator input, a second comparator input, and a first comparator output, the first comparator input being coupled to the output of the first error amplifier, and the second comparator input being coupled to the first current sensing output; and A first pulse generation circuit, coupled to the output of the first comparator; and The second controller circuit includes: A second current sensing circuit having a second current sensing output, the second current sensing circuit being configured to generate a second current sensing signal representing a second combined current at the second current sensing output; The second error amplifier has a first error amplifier input, a second error amplifier input, and a second error amplifier output, wherein the first error amplifier input is coupled to the first current sensing output, and the second error amplifier input is coupled to the second current sensing output. A summing circuit having a first summing input, a second summing input, and a summing output, wherein the first summing input is coupled to the output of a first error amplifier, and the second summing input is coupled to the output of a second error amplifier; A second comparator has a third comparator input, a fourth comparator input, and a second comparator output, the third comparator input being coupled to the summation output, and the fourth comparator input being coupled to the second current sensing output; and A second pulse generation circuit, coupled to the output of the second comparator, having a pulse generation output, is configured to adjust the pulse for the multiphase converter at the pulse generation output in response to the difference between the first combined current and the second combined current.

16. The apparatus of claim 15, wherein the first current sensing circuit has a first current sensing input, the second current sensing circuit has a second current sensing input, and the apparatus further comprises: A multiphase converter having a converter output coupled to the feedback input, a converter input coupled to the pulse generation output, and the multiphase converter including parallel-coupled power stages, each power stage having a corresponding current sensing output, some of the current sensing outputs being coupled to the first current sensing input, and other current sensing outputs being coupled to the second current sensing input.

17. The apparatus of claim 16, further comprising a load coupled to the output of the converter.

18. The apparatus of claim 15, wherein one or both of the first error amplifier or the second error amplifier include a corresponding integrator.

19. The apparatus of claim 15, wherein the first controller circuit is part of a first integrated circuit, and the second controller circuit is part of a second integrated circuit.

20. An apparatus for controlling a parallel power stage of a multiphase converter, the apparatus comprising: The first controller circuit includes: A first error amplifier is configured to generate a first error signal in response to the difference between a feedback signal from the multiphase converter and a reference signal; and A first current sensing circuit is configured to generate a first current sensing output signal representing a first combined current at the output of a first plurality of parallel power stages, wherein a first controller circuit is configured to provide a first pulse width modulation signal for the first plurality of parallel power stages in response to the difference between the first error signal and the first current sensing output signal. The second controller circuit includes: A second current sensing circuit is configured to generate a second current sensing output signal representing a second combined current at the output of the second plurality of parallel power stages; A second error amplifier is configured to generate a second error signal in response to the difference between the first combined current and the second combined current; and A summing circuit is configured to generate a summing signal in response to the first error signal and the second error signal, wherein the second controller circuit is configured to provide a second pulse width modulation signal for the second plurality of parallel power stages in response to the difference between the summing signal and the second current sensing output signal.

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