Display device, display panel and manufacturing method thereof

Abstract

A display device, a display panel and a manufacturing method thereof. The display panel comprises a driving back plate (BP), a first electrode layer (FE), a pixel definition layer (PDL), an emitting layer (OL) and a second electrode (CAT). The first electrode layer (FE) is arranged on one side of the driving back plate (BP) and comprises a plurality of first electrodes (ANO). The pixel definition layer (PDL) and the first electrode layer (FE) are arranged on the same side of the driving back plate (BP) and expose each first electrode (ANO). The pixel definition layer (PDL) comprises a filling layer (PBR) and a cutting layer (PCL) which are stacked in a direction away from the driving back plate (BP). The thickness of the filling layer (PBR) is less than that of the first electrode layer (FE). The cutting layer (PCL) is provided with a separation groove (SES) outside the first electrode (ANO). The sidewall of the separation groove (SES) is provided with a first cutting groove (CUS1). The emitting layer (OL) covers the cutting layer (PCL) and the first electrode layer (FE). The second electrode (CAT) covers the emitting layer (OL).

Description

[0001] Cross-referencing

[0002] This disclosure claims priority to PCT International Application No. PCT / CN2021 / 133886, filed on November 29, 2021, entitled “Display Substrate”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display device, a display panel, and a method for manufacturing the display panel. Background Technology

[0004] With the development of display technology, display panels have been widely used in various electronic devices such as mobile phones to achieve image display and touch operation. Among them, OLED (Organic Light-Emitting Diode) display panels are relatively common. However, the color gamut of existing display panels still needs to be improved.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] This disclosure provides a display device, a display panel, and a method for manufacturing the display panel.

[0007] According to one aspect of this disclosure, a display panel is provided, comprising:

[0008] Drive backplane;

[0009] The first electrode layer is disposed on one side of the drive back plate and includes a plurality of first electrodes spaced apart.

[0010] A pixel definition layer is disposed on the same side of the driving backplate as the first electrode layer, and exposes each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the driving backplate, the thickness of the fill layer is less than that of the first electrode layer, and it is located outside the first electrodes; the cut-off layer is provided with a partition groove located outside the first electrodes, and the sidewall of the partition groove is provided with a first cut-off groove.

[0011] A light-emitting layer covers the cut-off layer and the first electrode layer;

[0012] The second electrode covers the light-emitting layer.

[0013] In one exemplary embodiment of this disclosure, the cut-off layer includes a plurality of insulating layers stacked in a direction away from the drive backplate, and the partition groove exposes the filling layer; the first cut-off groove is formed in an insulating layer, and the insulating layer in which the first cut-off groove is located is any insulating layer other than the insulating layer farthest from the drive backplate.

[0014] In one exemplary embodiment of this disclosure, the insulating layer of the cut-off layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked sequentially in a direction away from the drive backplate, and the first cut-off groove is formed in the second insulating layer.

[0015] In one exemplary embodiment of this disclosure, the sidewall of the partition groove is a slope that expands in a direction away from the drive backplate.

[0016] In one exemplary embodiment of this disclosure, the bottom surface of the first cut-off groove is a slope that reduces its depth in a direction away from the drive backplate.

[0017] In one exemplary embodiment of this disclosure, the slope angle of the bottom surface of the first cut-off groove is greater than the slope angle of the partition groove located on the side wall of the first insulating layer, and is also greater than the slope angle of the partition groove located on the side wall of the third insulating layer.

[0018] In one exemplary embodiment of this disclosure, the sum of the slope angle of the bottom surface of the first cutting groove and the slope angle of the sidewall of the dividing groove located in the first insulating layer is not greater than 90°.

[0019] In one exemplary embodiment of this disclosure, the sum of the slope angle of the bottom surface of the first cutting groove and the slope angle of the sidewall of the dividing groove located in the third insulating layer is not greater than 90°.

[0020] In one exemplary embodiment of this disclosure, the included angle between the extended surfaces of the two side walls of the partition groove is an acute angle.

[0021] In one exemplary embodiment of this disclosure, the cut-off layer includes a cut-off portion and an extension portion. The cut-off portion is located outside the first electrode, and the extension portion is located on the surface of the first electrode away from the driving backplate and has a pixel opening that exposes the first electrode. The sidewall of the pixel opening is a slope that expands in a direction away from the driving backplate.

[0022] In one exemplary embodiment of this disclosure, the sum of the slope angle of the sidewall of the pixel opening and the slope angle of the bottom surface of the first cut-off groove is not less than 90°.

[0023] In one exemplary embodiment of this disclosure, at least a portion of the sidewalls of the pixel openings are provided with a second cut-off groove.

[0024] In one exemplary embodiment of this disclosure, the maximum depth of the first cut-off groove is greater than the maximum depth of the second cut-off groove.

[0025] In one exemplary embodiment of this disclosure, the portion of the sidewall of the third insulating layer used to form the first cut-off groove is inclined toward the drive back plate, and the inclination angle is a first inclination angle.

[0026] The portion of the third insulating layer that forms the second cut-off groove is inclined toward the drive back plate, and the inclination angle is the second inclination angle.

[0027] The first tilt angle is greater than the second tilt angle.

[0028] In one exemplary embodiment of this disclosure, the second electrode forms a flat portion in a region corresponding to the first electrode and a recessed portion in a region corresponding to the dividing groove, the recessed portion and the flat portion transitioning smoothly.

[0029] In one exemplary embodiment of this disclosure, the depth of the recess is less than the depth of the partition groove.

[0030] In one exemplary embodiment of this disclosure, the depth of the recess is greater than the thickness of the filling layer.

[0031] In one exemplary embodiment of this disclosure, the filling layer is in contact with the sidewall of the first electrode.

[0032] In one exemplary embodiment of this disclosure, the light-emitting layer further includes multiple light-emitting sub-layers connected in series, at least one of the light-emitting sub-layers being connected in series with an adjacent light-emitting sub-layer via a charge generation layer; the portion of the charge generation layer corresponding to the first electrode and the portion corresponding to the separator groove are disconnected.

[0033] In one exemplary embodiment of this disclosure, the filling layer includes a filling insulating layer and a filling conductive layer stacked in a direction away from the drive backplate, the filling insulating layer being in contact with the sidewall of the first electrode, and the filling conductive layer being spaced apart from the sidewall of the first electrode.

[0034] In one exemplary embodiment of this disclosure, the driving backplane includes a pixel region and a peripheral region located outside the pixel region; the pixel region has a pixel circuit for driving the light-emitting layer to emit light, and the peripheral region has a peripheral circuit;

[0035] The first electrode layer further includes a transition ring, the orthographic projection of which on the driving backplate is located in the peripheral area and surrounds the pixel area. The transition ring is connected to the peripheral circuit, and the second electrode is connected to the transition ring. The transition ring has a notch.

[0036] The conductive filling layer includes a main body and a connecting part. The main body is located inside the adapter ring and is spaced apart from the adapter ring. The connecting part is connected to the main body and extends out of the adapter ring through the notch, and is spaced apart from the adapter ring. The connecting part is used to receive aging voltage signals.

[0037] According to one aspect of this disclosure, the display panel is the display panel described above, and the manufacturing method includes:

[0038] Forming a drive backplate;

[0039] A first electrode layer comprising a plurality of spaced first electrodes is formed on one side of the drive back plate;

[0040] A pixel definition layer is formed on the side of the drive backplate where the first electrode layer is provided, exposing each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the drive backplate, the thickness of the fill layer is less than that of the first electrode layer, and it is located outside the first electrodes;

[0041] An aging voltage signal is applied to the conductive filling layer and maintained for a specified duration;

[0042] A partition groove located outside the first electrode and a first cut-off groove located on the sidewall of the partition groove are formed in the cut-off layer;

[0043] A light-emitting layer is formed covering the cut-off layer and the first electrode layer;

[0044] A second electrode is formed to cover the light-emitting layer.

[0045] According to one aspect of this disclosure, a method for manufacturing a display panel is provided, comprising:

[0046] Forming a drive backplate;

[0047] A first electrode layer comprising a plurality of spaced first electrodes is formed on one side of the drive back plate;

[0048] A pixel definition layer is formed on the side of the driving backplate on which the first electrode layer is formed, exposing each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the driving backplate, the thickness of the fill layer is less than that of the first electrode layer and is located outside the first electrodes; the cut-off layer is provided with a partition groove located outside the first electrodes, and the sidewall of the partition groove is provided with a first cut-off groove.

[0049] A light-emitting layer is formed covering the cut-off layer and the first electrode layer;

[0050] A second electrode is formed to cover the light-emitting layer.

[0051] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0052] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0053] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0054] Figure 1 This is a partial cross-sectional view of one embodiment of the display panel of this disclosure.

[0055] Figure 2 This is a partial cross-sectional view of another embodiment of the display panel of this disclosure.

[0056] Figure 3 This is a partial cross-sectional view of a portion of the film layer in one embodiment of the display panel of this disclosure.

[0057] Figure 4 This is a partial cross-sectional view of a portion of the film layer in another embodiment of the display panel of this disclosure.

[0058] Figure 5 This is a schematic diagram of a light-emitting unit in one embodiment of the display panel of this disclosure.

[0059] Figure 6 This is a partial top view of one embodiment of the display panel of this disclosure.

[0060] Figure 7 This is a schematic diagram of a light-emitting unit in one embodiment of the display panel of this disclosure.

[0061] Figure 8This is a partial cross-sectional view of one embodiment of the display panel of this disclosure.

[0062] Figure 9 This is a schematic diagram of an adapter ring and a conductive filling layer in one embodiment of the display panel of this disclosure. Detailed Implementation

[0063] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0064] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0065] Any “slope” in this application is a straight line in a section perpendicular to the drive backplate, and the slope angle of such “slope” (e.g., Figure 3 In this context, α1, α2, β, γ, and δ can be defined as the angle between the straight line or its extension and the surface on which the slope lies, with respect to the angle closest to the first electrode surrounded by the slope. It should be noted that, considering the influence of process errors, the aforementioned straight line may not be an absolute straight line, but rather a curve extending approximately along a straight line. This curve may have multiple tangent lines, each of which makes an angle with the surface on which the slope lies. The slope angle of this curve can be the largest of these angles or the average of the angles.

[0066] In related technologies, silicon-based OLED display panels include a driving backplane and a light-emitting functional layer. The light-emitting functional layer is disposed on one side of the driving backplane and includes multiple light-emitting units. Each light-emitting unit may include one or more light-emitting devices connected in series. The light-emitting devices may be organic light-emitting diodes, which may include a first electrode (anode), a light-emitting layer, and a second electrode (cathode) stacked sequentially in the direction away from the driving backplane. By applying an electrical signal to the first electrode and the second electrode, the light-emitting layer can be driven to emit light. The specific light-emitting principle of the light-emitting device will not be detailed here.

[0067] Furthermore, the light-emitting layers of each light-emitting device can be directly deposited using a fine mask (FMM), and the light-emitting layers of each device are spaced apart and emit light independently, achieving color display. However, due to limitations in the manufacturing process of fine masks, it is difficult to achieve a high PPI (pixel density). Therefore, color display can also be achieved by using monochromatic light or white light in conjunction with a color filter. That is, each light-emitting device shares the same continuous light-emitting layer, which can emit white light or other monochromatic light. The color filter layer has multiple filters that correspond one-to-one with the light-emitting units. One filter and its corresponding light-emitting unit can constitute a sub-pixel, and multiple sub-pixels constitute one pixel. Different filters can transmit different colors of light, allowing different sub-pixels to emit different colors. The same pixel includes multiple sub-pixels of different colors. For example, a pixel can include three sub-pixels with red, green, and blue emission colors respectively. Thus, color display can be achieved through multiple pixels.

[0068] However, if the light-emitting layer is a continuous monolithic structure, leakage can easily occur between one light-emitting unit and surrounding light-emitting units, leading to color crosstalk. Each light-emitting unit may include multiple light-emitting devices connected in series. The light-emitting devices in the same light-emitting unit share a first electrode and a second electrode. There are multiple light-emitting sub-layers between the first electrode and the second electrode, and at least two adjacent light-emitting sub-layers can be connected in series through a charge generation layer. Positive charges (holes) can be transferred between two adjacent light-emitting units through the charge generation layer. For example, when the light-emitting unit in the red filter section of the corresponding color filter layer emits light, due to the effect of leakage, the light-emitting unit in the green filter section of the corresponding color filter layer will also emit light, resulting in a decrease in the light emission purity of a single pixel and a decrease in the color gamut of the entire display panel.

[0069] This disclosure provides a display panel, such as... Figure 1 and Figure 2 As shown, the display panel may include a driving backplane BP, a first electrode layer FE, a pixel definition layer PDL, a light-emitting layer OL, and a second electrode CAT, wherein:

[0070] The first electrode layer FE is disposed on one side of the driving backplate BP and includes a plurality of first electrodes ANO distributed at intervals. The pixel definition layer PDL is disposed on the same side of the driving backplate BP as the first electrode layer FE, and exposes each first electrode ANO. The pixel definition layer PDL includes a fill layer PBR and a cut-off layer PCL stacked in a direction away from the driving backplate BP. The thickness of the fill layer PBR is less than that of the first electrode layer FE and it is located outside the first electrodes ANO. The cut-off layer PCL has a partition groove SES located outside the first electrodes ANO, and the sidewall of the partition groove SES has a first cut-off groove CUS1. The light-emitting layer OL covers the cut-off layer PCL and the first electrode layer FE. The second electrode CAT covers the light-emitting layer OL.

[0071] In the display panel of this embodiment, any first electrode ANO, its corresponding light-emitting layer OL, and second electrode CAT can constitute a light-emitting unit SUP. A pixel definition layer PDL can separate each light-emitting unit SUP, defining the range of each light-emitting unit SUP. Because the sidewall of the partition groove SES has a first cut-off groove CUS1, even if the light-emitting layer OL is recessed into the partition groove SES, it is difficult for it to be continuously formed within the first cut-off groove CUS1. That is, at least a portion of the film layer of the light-emitting layer OL can be broken in the first cut-off groove CUS1, thereby reducing the risk of mutual leakage between adjacent light-emitting units SUP and improving color crosstalk. Furthermore, the filler layer PBR can be used to limit the depth of the partition groove SES, preventing difficulty in controlling the etching depth during the etching of the partition groove SES, which is beneficial for improving the uniformity of different driving backplanes BP.

[0072] The following is a detailed description of the structure by which the display panel of this disclosure implements its display function:

[0073] like Figure 1 and Figure 2 As shown, the driving backplate BP may include a pixel area and a peripheral area, with the peripheral area located outside the pixel area and potentially surrounding it. The driving backplate BP is used to form the driving circuit for driving the light-emitting unit SUP to emit light. This driving circuit may include pixel circuitry and peripheral circuitry, wherein:

[0074] The number of pixel circuits and light-emitting units (SUPs) can both be multiple, and at least some of the pixel circuits are located within the pixel area. The pixel circuits can be 2T1C, 4T1C, etc., as long as they can drive the light-emitting units (SUPs) to emit light; their structure is not specifically limited here. The number of pixel circuits is the same as the number of first electrodes (ANOs), and they are connected to the first electrodes (ANOs) one-to-one to control the light emission of each light-emitting unit (SUP). Here, nTmC indicates that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). Of course, the same pixel circuit can also drive multiple light-emitting units (SUPs).

[0075] The peripheral circuitry is located in the peripheral area and connected to the pixel circuitry. The peripheral circuitry may include a light-emitting control circuit, a gate driving circuit, and a source driving circuit. Additionally, it may include a power supply circuit connected to the second electrode CAT for inputting a power signal to the second electrode CAT. The peripheral circuitry can input signals to the first electrode ANO and the second electrode CAT via the pixel circuitry, thereby causing the light-emitting unit SUP to emit light.

[0076] In some embodiments of this disclosure, such as Figure 1 and Figure 2As shown, the driving backplane BP may include a substrate SU, which may be a silicon substrate. The driving circuit described above can be formed on the silicon substrate using semiconductor processes. For example, both the pixel circuit and the peripheral circuit can include multiple transistors. A well region WL can be formed in the silicon substrate using a doping process. The well region WL has two doped regions DR spaced apart. Taking one well region WL as an example: a gate GATE is provided on one side of the driving backplane BP. The orthogonal projection of the gate GATE on the driving backplane BP is located between the two doped regions DR. The well region WL and the gate GATE can form a transistor. The doped regions DR of the well region WL are the first and second electrodes of the transistor, respectively. The well region WL between the two doped regions DR is the channel region of the transistor.

[0077] The driving backplane BP may also include at least one wiring layer TL and a planarization layer PLN. The wiring layer TL is located on the substrate SU side, and the planarization layer PLN covers the wiring layer TL. At least one wiring layer TL is connected to each doped region DR.

[0078] For example: Figure 1 and Figure 2 As shown, there are two wiring layers TL, located within a planarization layer PLN. For example, the wiring layers TL include a first wiring layer TL1 and a second wiring layer TL2. The first wiring layer TL1 is disposed on one side of the substrate SU, and a portion of the planarization layer PLN is disposed between it and the substrate SU. The second wiring layer TL2 is disposed on the side of the first wiring layer TL1 away from the substrate SU, and is separated from the first wiring layer TL1 by a portion of the planarization layer PLN. At least a portion of the second wiring layer TL2 is connected to the first wiring layer TL1.

[0079] Each trace layer (TL) can be formed by sputtering. The planarization layer (PLN) can be made of silicon oxide, silicon oxynitride, or silicon nitride, and is formed layer by layer through multiple deposition and polishing processes. In other words, the planarization layer (PLN) can be composed of multiple insulating film layers stacked together.

[0080] like Figure 1 and Figure 2 As shown, the light-emitting units (SUPs) array of the display panel are distributed on one side of the driving backplane BP. For example, each light-emitting unit (SUP) is disposed on the surface of the planarization layer PLN facing away from the substrate SU. Each light-emitting unit (SUP) may include a first electrode ANO, a second electrode CAT, and a light-emitting layer OL located between the first electrode ANO and the second electrode CAT. Both the first electrode ANO and the second electrode CAT can be connected to the wiring layer TL. A driving signal is applied to the first electrode ANO and a power signal is applied to the second electrode CAT through the driving backplane BP, thereby driving the light-emitting layer OL to emit light.

[0081] To achieve color display, each light-emitting unit (SUP) can emit light of the same color. This, combined with the color filter layer (CF) located on the side of the second electrode (CAT) away from the driving backplate (BP), enables color display. The embodiments disclosed herein are described using this type of color display scheme as an example.

[0082] In some embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, multiple light-emitting units (SUPs) can be formed through the first electrode layer FE, the pixel definition layer PDL, the light-emitting layer OL, and the second electrode CAT, wherein:

[0083] The first electrode layer FE is disposed on one side of the driving backplane BP. For example, the first electrode layer FE is disposed on the surface of the planarization layer PLN facing away from the substrate SU. The first electrode layer FE may include a plurality of spaced first electrodes ANO. The orthogonal projection of each first electrode ANO on the driving backplane BP is located in the pixel area and is connected to the pixel circuit. One first electrode ANO is connected to one pixel circuit.

[0084] The first electrode layer FE can be a single layer or a multi-layer structure, and its material is not specifically limited here.

[0085] For example:

[0086] like Figure 1 and Figure 2 As shown, in some embodiments of this disclosure, the first electrode ANO may include a first conductive layer ANO1, a second conductive layer ANO2, and a third conductive layer ANO3 sequentially stacked in a direction away from the driving backplate BP. The first conductive layer ANO1 and the third conductive layer ANO3 may both be made of metal or metal oxides, such as titanium or titanium nitride; the materials may be the same or different. The second conductive layer ANO2 may be made of a different metal material than the first conductive layer ANO1 and the third conductive layer ANO3, and its resistivity is lower than that of the first conductive layer ANO1 and the third conductive layer ANO3. For example, the material of the second conductive layer ANO2 may be aluminum.

[0087] In some other embodiments of this disclosure, the first electrode ANO may further include a fourth conductive layer, which may be disposed on the surface of the third conductive layer away from the driving backplate BP, and the fourth conductive layer may be made of a transparent conductive material such as ITO (indium tin oxide).

[0088] like Figure 3 and Figure 4 As shown, the pixel definition layer PDL and the first electrode layer FE are disposed on the same surface of the driving backplane BP, that is, the surface of the planarization layer PLN facing away from the substrate SU, and the pixel definition layer PDL exposes each of the first electrodes ANO. Specifically, the pixel definition layer PDL may have multiple pixel openings PO that expose each of the first electrodes ANO.

[0089] The orthographic projection of any pixel opening PO onto the driving backplane BP can be located within its exposed first electrode ANO. In other words, the pixel opening PO is not larger than its exposed first electrode ANO. For example, the boundary of the pixel opening PO is located inside the boundary of its exposed first electrode ANO, that is, the area of ​​the pixel opening PO is smaller than the area of ​​its exposed first electrode ANO.

[0090] like Figure 6 As shown, the shape of the pixel opening PO can be a rectangle, pentagon, hexagon, or other polygon, but it does not have to be a regular polygon. The shape of the pixel opening PO can also be an ellipse or other shapes, without any special restrictions here.

[0091] like Figure 1 and Figure 2 As shown, the light-emitting layer OL covers the pixel definition layer PDL and the first electrode ANO. The area where the light-emitting layer OL and the first electrode ANO are stacked is used to form the light-emitting unit SUP. That is, each light-emitting unit SUP can share the same light-emitting layer OL, and the parts of the light-emitting layer OL that are stacked on different first electrodes ANO belong to different light-emitting units SUP. In addition, since each light-emitting unit SUP shares the light-emitting layer OL, the light emitted by different light-emitting units SUP is the same.

[0092] In some embodiments of this disclosure, such as Figure 1 , Figure 2 and Figure 7 As shown, a light-emitting unit SUP may include multiple light-emitting devices LD in series. Each light-emitting unit SUP includes a first electrode ANO, a second electrode CAT, and multiple light-emitting sublayers OLP between the first electrode ANO and the second electrode CAT. Each light-emitting device LD in the same light-emitting unit SUP may share the same first electrode ANO and the same second electrode CAT. That is to say, the same light-emitting unit SUP may have only one first electrode ANO and one second electrode CAT.

[0093] For example: Figure 1 , Figure 2 and Figure 7 As shown, the light-emitting layer OL may include multiple light-emitting sub-layers OLP connected in series along the direction away from the driving backplate BP, and at least one light-emitting sub-layer OLP is connected in series with an adjacent light-emitting sub-layer OLP through a charge generation layer CGL. When an electrical signal is applied to the first electrode ANO and the second electrode CAT, each light-emitting sub-layer OLP can emit light, and different light-emitting sub-layers OLP can be used to emit light of different colors.

[0094] Furthermore, such as Figure 7As shown, any light-emitting sublayer OLP may include a hole injection layer HIL, a hole transport layer HTL, a light-emitting material layer EML, an electron transport layer ETL, and an electron injection layer EIL distributed along the direction away from the driving backplane BP. The specific light-emitting principle will not be detailed here.

[0095] The number of hole injection layers (HIL), hole transport layers (HTL), electron transport layers (ETL), and electron injection layers (EIL) is not specifically limited here, and adjacent light-emitting sublayers (OLPs) may share one or more of the following: hole injection layers (HIL), hole transport layers (HTL), electron transport layers (ETL), and electron injection layers (EIL). Furthermore, a charge generation layer (CGL) may be provided between at least two adjacent light-emitting sublayers (OLPs), thereby connecting the two light-emitting sublayers (OLPs) in series.

[0096] In some embodiments of this disclosure, such as Figure 7 As shown, the luminescent layer OL may include three luminescent sublayers OLP of different colors: a first luminescent sublayer OLPr emitting red light, a second luminescent sublayer OLPg emitting green light, and a third luminescent sublayer OLPb emitting blue light. When the first luminescent sublayer OLPr, the second luminescent sublayer OLPg, and the third luminescent sublayer OLPb emit light simultaneously, the luminescent layer OL emits white light. The first luminescent sublayer OLPr and the second luminescent sublayer OLPg share a hole injection layer HIL, a hole transport layer HTL1, an electron transport layer ETL2, and an electron injection layer EIL. The luminescent material layer G-EML of the second luminescent sublayer OLPg is disposed on the surface of the luminescent material layer R-EML of the first luminescent sublayer OLPr, facing away from the driving backplate BP. This allows the first luminescent sublayer OLPr and the second luminescent sublayer OLPg to be directly connected in series, without the need for a dedicated charge generation layer. A charge generation layer CGL may be disposed on the surface of the second luminescent sublayer OLPg facing away from the driving backplate BP. The third luminescent layer OLPb shares an electron injection layer EIL with the first luminescent layer OLPr and the second luminescent layer OLPg. The hole injection layer HIL2 of the third luminescent layer OLPb is disposed on the surface of the charge generation layer CGL facing away from the driving backplane BP. The hole transport layers HTL2 and HTL3 of the third luminescent layer OLPb are stacked on one side of the charge generation layer CGL facing away from the driving backplane BP, thus connecting the third luminescent layer OLPb in series with the second luminescent layer OLPg and the first luminescent layer OLPr. Furthermore, a hole filling layer HBL can be disposed between the electron transport layer HYL and the luminescent material layer BEML of the third luminescent layer OLPb.

[0097] The above-described light-emitting layer OL structure is merely an illustrative example and does not constitute a limitation on its film layers. It may include only two light-emitting sublayers OLP, or more, or only one light-emitting sublayer OLP, as long as it can work with the color filter layer CF to achieve color display.

[0098] like Figure 1 , Figure 2 and Figure 7 As shown, the second electrode CAT covers the light-emitting layer OL, and the orthographic projection of the second electrode CAT onto the driving backplane BP can cover the pixel area and extend into the peripheral area. Each light-emitting unit SUP can share the same second electrode CAT. The light emission of the light-emitting layer OL can be controlled by controlling the voltage of the power signal input to the second electrode CAT and the driving signal input to the first electrode ANO.

[0099] like Figure 1 and Figure 2 As shown, the display panel may further include a color filter layer (CF), which may be disposed on the side of the second electrode (CAT) facing away from the driving backplate (BP), and includes multiple color filter units (CFU). Each first electrode (ANO) and each color filter unit (CFU) are arranged opposite to each other in a direction perpendicular to the driving backplate (BP), that is, the orthogonal projection of a color filter unit (CFU) on the driving backplate (BP) at least partially coincides with a first electrode (ANO). Each color filter unit (CFU) includes at least three color filter units, for example, a color filter unit (CFU) that transmits red light, a color filter unit (CFU) that transmits green light, and a color filter unit (CFU) that transmits blue light. The light emitted by each light-emitting unit (SUP) is filtered by the color filter units (CFU) to obtain monochromatic light of different colors, thereby realizing color display. A color filter unit (CFU) and its corresponding light-emitting unit (SUP) can constitute a sub-pixel. The color emitted by any sub-pixel is the color of the light transmitted by its color filter unit (CFU). Multiple sub-pixels can constitute a pixel, and the color emitted by each sub-pixel of the same pixel is different.

[0100] The color filter layer (CF) may also include a light-shielding portion separating the color filter units (CFUs). This light-shielding portion is opaque and blocks the area between the two light-emitting units (SUPs). The color filter units (CFUs) can be directly spaced from each other using a light-shielding material; or, as... Figure 1 and Figure 2 As shown, in some embodiments of this disclosure, adjacent filter units (CFUs) can be stacked in the area corresponding to two adjacent light-emitting units (SUPs), and the colors of the light transmitted by the two units are different, so that the stacked area is opaque.

[0101] Furthermore, in some embodiments of this disclosure, in order to improve the brightness of the image, the color filter layer CF may also include a transparent portion, which may be disposed opposite to a light-emitting unit SUP in a direction perpendicular to the substrate, so that the color filter layer CF can also transmit white light, thereby increasing the brightness through white light.

[0102] To improve light extraction efficiency, a light extraction layer can be covered on the side of the second electrode CAT away from the driving backplate BP to increase brightness. Furthermore, the light extraction layer can directly cover the surface of the second electrode CAT away from the driving backplate BP.

[0103] To facilitate the connection of the second electrode CAT to the driving circuit, in some embodiments of this disclosure, the first electrode layer FE further includes a transition ring. The orthographic projection of the transition ring on the driving backplane BP is located in the peripheral region. The transition ring can be connected to the peripheral circuit and surrounds the pixel region. The second electrode CAT can be connected to the transition ring, thereby connecting the second electrode CAT to the peripheral circuit through the transition ring so that a driving signal can be applied to the second electrode CAT by the peripheral circuit. The pattern of the transition ring can be the same as the pattern of the first electrode ANO in the pixel region to improve the uniformity of the pattern of the first electrode layer FE.

[0104] In some embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the display panel of this disclosure may further include a first encapsulation layer TFE1, which may be disposed on the side of the second electrode CAT away from the driving backplane BP, and located between the color filter layer CF and the second electrode CAT, for blocking external water and oxygen erosion. The first encapsulation layer TFE1 may be a single-layer or multi-layer structure. For example, the first encapsulation layer TFE1 may include a first encapsulation sub-layer, a second encapsulation sub-layer, and a third encapsulation sub-layer stacked sequentially in the direction away from the driving backplane BP. The materials of the first and second encapsulation sub-layers may be inorganic insulating materials such as silicon nitride and silicon oxide, and the second encapsulation sub-layer may be formed using ALD (Atomic layer deposition) technology; the material of the third encapsulation sub-layer may be an organic material, which may be formed using MLD (Molecular Layer Deposition) technology. Of course, the first encapsulation layer TFE1 may also adopt other structures, and no special limitation is made to the structure of the first encapsulation layer TFE1 here.

[0105] Furthermore, in some embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, the display panel of this disclosure may further include a second encapsulation layer TFE2, which can cover the surface of the color filter layer CF away from the driving backplane BP to achieve planarization, facilitate the covering of a transparent cover, and improve the encapsulation effect, further blocking water and oxygen. The second encapsulation layer can be a single-layer or multi-layer structure, and may include inorganic materials such as silicon nitride and silicon oxide, or may include organic materials. No special limitation is made to the structure of the second encapsulation layer here.

[0106] In addition, the display panel may also include a transparent cover plate, which may cover the side of the second encapsulation layer TFE2 away from the driving backplane BP. The transparent cover plate may be a single layer or a multi-layer structure, and its material is not specifically limited here.

[0107] Based on the analysis of related technologies above, since each light-emitting unit (SUP) shares the light-emitting layer OL, charge carriers (e.g., holes) in one SUP may migrate to other SUPs through the charge generation layer CGL and other film layers, especially to adjacent SUPs, resulting in leakage current. This affects the purity of light emission and causes cross-coloring. Therefore, such as... Figure 1 and Figure 2 As shown, by setting a partition groove SES in the cut-off layer PCLSL and opening a first cut-off groove CUS1 on the sidewall of the partition groove SES, the light-emitting layer OL is difficult to be continuous within the first cut-off groove CUS1 during its formation, thus being interrupted within the partition groove SES. This prevents carriers from moving between the light-emitting units SUP, thereby avoiding color crosstalk caused by leakage. Furthermore, to limit the depth of the partition groove SES and prevent it from extending into the driving backplane BP, and to address the significant depth differences between different display panels, the etching depth of the filler layer PBR during its formation can be limited. That is, the depth of the partition groove SES is limited by the filler layer PBR, which helps to improve the structural uniformity of different driving backplanes BP.

[0108] The following is a detailed explanation of the solution to the color mixing problem in the display panel disclosed herein:

[0109] like Figure 1 and Figure 2As shown, to achieve the above objectives, the pixel definition layer (PDL) may include at least two layers: a filler layer (PBR) and a cutoff layer (PCL). The filler layer (PBR) may be directly stacked on the driving backplane (BP). The filler layer (PBR) may be co-located with the first electrode layer (FE) on the surface of the planarization layer (PLN) away from the substrate, and the filler layer (PBR) is located outside the first electrode layer (FE) and separates each first electrode (ANO). In other words, the filler layer (PBR) can be regarded as a film layer with multiple vias, and each first electrode (ANO) may be disposed in a corresponding via. Simultaneously, to provide sufficient recess space for the separator grooves (SES) on the cutoff layer (PCL), the thickness of the filler layer (PBR) is smaller than that of the first electrode (ANO). For example, for a first electrode ANO comprising a first conductive layer ANO1, a second conductive layer ANO2, and a third conductive layer ANO3, the thickness of the filler layer PBR can be greater than the thickness of the first conductive layer ANO1, but less than the sum of the thicknesses of the second conductive layer ANO2 and the first conductive layer ANO1. That is, the surface of the filler layer PBR facing away from the drive backplane BP is located between the surface of the second conductive layer ANO2 facing away from the drive backplane BP and the first conductive layer ANO1. Furthermore, the material of the filler layer PBR can be an inorganic insulating material such as silicon oxide or silicon nitride, or other insulating materials. Additionally, the filler layer PBR can contact the sidewall of the first electrode ANO, i.e., the sidewall of the through-hole is attached to the sidewall of the first electrode ANO inside it. Since the material of the filler layer PBR is an insulating material, it will not be electrically connected to the first electrode ANO, thus avoiding short circuits between adjacent first electrodes ANO.

[0110] like Figure 1 and Figure 2 As shown, the cut-off layer PCL can be stacked on the surface of the filler layer PBR away from the drive backplane BP, and each first electrode ANO is exposed. The sum of the thicknesses of the cut-off layer PCL and the filler layer PBR can be greater than the thickness of the first electrode layer FE.

[0111] In some embodiments of this disclosure, such as Figure 3As shown, a portion of the cut-off layer PCL can extend to the surface of the first electrode ANO facing away from the driving backplate BP, but does not completely cover the first electrode ANO. Accordingly, the cut-off layer PCL may include a cut-off portion PDLc and an extension portion PDLe. The cut-off portion PDLc may be located outside the first electrode ANO, and the extension portion PDLe is located on the surface of the first electrode ANO facing away from the driving backplate BP. The pixel definition layer PDL and the orthographic projection of the first electrode ANO onto the driving backplate BP have an overlapping area. The pixel opening PO can be formed in the extension portion PDLe to expose the first electrode ANO. Since the thickness of the first electrode ANO is greater than that of the filler layer PBR, the cut-off layer PCL needs to climb a slope when extending from the cut-off portion PDLc to the extension portion PDLe; that is, the surface of the extension portion PDLe facing away from the first electrode ANO is located on the side of the surface of the cut-off portion PDLc facing away from the driving backplate BP. Furthermore, in this embodiment, the sidewall of the pixel opening PO can be a slope that expands in the direction away from the driving backplate BP.

[0112] In other embodiments of this disclosure, the cut-off layer PCL may not include the extension PDLe, but only the cut-off portion PDLc. The cut-off portion PDLc can separate each first electrode ANO, that is, the boundaries of the projections of the cut-off portion PDLc and the fill layer PBR on the driving backplane BP can coincide. The pixel opening PO can be a through-hole penetrating the cut-off portion PDLc and the fill layer PBR, and there is no overlapping area between the orthographic projections of the pixel definition layer PDL and the first electrode ANO on the driving backplane BP.

[0113] like Figure 1 and Figure 2 As shown, the cut-off layer PCL has a partition groove SES, which is located outside the first electrode ANO. The partition groove SES can be an annular groove surrounding the first electrode ANO, and each first electrode ANO can have one partition groove SES surrounding it. The partition grooves SES surrounding two adjacent first electrode ANOs can share a portion of their area, allowing only one partition groove SES between two adjacent first electrode ANOs. One side wall of the partition groove SES surrounds one electrode, and both side walls of the partition groove SES are also present. Alternatively, the partition grooves SES surrounding two adjacent first electrode ANOs can be independently formed without any shared portion. Furthermore, the side walls of the partition groove SES can be slopes that expand in the direction away from the drive backplate BP, meaning the distance between the two side walls of the partition groove SES gradually increases in the direction away from the drive backplate BP, and the slope angle of the side walls of the partition groove SES is less than or equal to 90°.

[0114] like Figure 1 and Figure 2As shown, the sidewall of the partition groove SES is provided with a first cut-off groove CUS1. The first cut-off groove CUS1 can be recessed from the sidewall of the partition groove SES toward the first electrode ANO surrounded by the partition groove SES. The direction of the recess is its depth direction. The depth of the first cut-off groove CUS1 can be less than the distance between its sidewall and the first electrode ANO. That is to say, the first cut-off groove CUS1 does not penetrate the cut-off layer PCL in its depth direction.

[0115] like Figure 1 and Figure 2 As shown, the first cut-off groove CUS1 extends along the extension direction of the separator groove SES, thereby forming an annular groove on the sidewall of the separator groove SES. The light-emitting layer OL covers the cut-off layer PCL and the first electrode layer FE, and is recessed into the separator groove SES. However, due to the presence of the first cut-off groove CUS1, the charge generation layer CGL or other film layers of the light-emitting layer OL are difficult to form within the first cut-off groove CUS1, and are broken on the sidewall of the separator groove SES. For example, the portion of the charge generation layer CGL corresponding to the first electrode ANO and the portion corresponding to the separator groove SES are broken. This prevents color cross-contamination between adjacent light-emitting units SUP.

[0116] To ensure the blocking effect, first cut-off grooves CUS1 can be provided on both sides of the partition groove SES, and one or more first cut-off grooves CUS1 can be opened on the same side wall. If multiple first cut-off grooves CUS1 are opened on one side wall, the first cut-off grooves CUS1 can be distributed at intervals along the direction away from the drive backplate BP.

[0117] The specific method for forming the first cutoff groove CUS1 is described in detail below:

[0118] like Figure 1 and Figure 2 As shown, in some embodiments of this disclosure, the cut-off layer PCL includes multiple insulating layers stacked along the direction away from the drive backplane BP. The material of each insulating layer can be an insulating inorganic material such as silicon oxide or silicon nitride; no special limitation is made here. Different insulating layers may have the same or different materials. The partition groove SES can expose the filler layer PBR, meaning the partition groove SES penetrates each insulating layer. The first cut-off groove CUS1 can be formed in an insulating layer, and the insulating layer it is located in can be any insulating layer other than the insulating layer farthest from the drive backplane BP. For example, the number of insulating layers in the cut-off layer PCL can be three, namely, a first insulating layer CL1, a second insulating layer CL2, and a third insulating layer CL3 stacked sequentially along the direction away from the drive backplane BP. The first cut-off groove CUS1 can be formed in the second insulating layer CL2. Figure 3As shown, the partition groove SES penetrates the first insulating layer CL1 and the third insulating layer CL3. The sidewall of the partition groove SES located in the first insulating layer CL1 can be a slope that expands in the direction away from the drive backplate BP. The sidewall of the partition groove SES located in the third insulating layer CL3 can also be a slope that expands in the direction away from the drive backplate BP. The slope angles α1 and α2 of the two slopes are not greater than 90°, and they can be the same.

[0119] The material of the insulating layer to be formed into the first cut-off groove CUS1 can be different from the materials of other insulating layers. When forming the first cut-off groove CUS1, the partition groove SES and the first cut-off groove CUS1 are formed by etching different degrees of different materials through an etching process. Of course, other processes can also be used, as long as they can form the partition groove SES and the first cut-off groove CUS1.

[0120] like Figure 3 As shown, the two side walls of the first cutoff groove CUS1 can be distributed in a direction away from the drive backplate BP. A bottom surface is located between the two side walls, surrounding the first electrode ANO. This bottom surface can be a slope that reduces the depth of the first cutoff groove CUS1 in the direction away from the drive backplate BP. In other words, the bottom surface of the first cutoff groove CUS1 surrounding the first electrode ANO is an annular surface that expands in the direction away from the drive backplate BP, meaning the slope angle β of the bottom surface of the first cutoff groove CUS1 is greater than 90°. Alternatively, the bottom surface of the first cutoff groove CUS1 can be perpendicular to the drive backplate BP.

[0121] like Figure 3 As shown, the slope angle β of the bottom surface of the first cut-off groove CUS1 is greater than the slope angle α1 of the side wall of the partition groove SES located in the first insulating layer CL1, and greater than the slope angle α2 of the side wall of the partition groove SES located in the third insulating layer CL3. Furthermore, the sum of the slope angle β of the bottom surface of the first cut-off groove CUS1 and the slope angle α1 of the side wall of the partition groove SES located in the first insulating layer CL1 is not greater than 90°, for example, 50°, 60°, etc. Simultaneously, the sum of the slope angle β of the bottom surface of the first cut-off groove CUS1 and the slope angle α2 of the side wall of the partition groove SES located in the third insulating layer CL3 is not greater than 90°. In other embodiments of this disclosure, the slope angles of the two slope surfaces can be different. Furthermore, as... Figure 3 As shown, the sum of the slope angle δ of the sidewall of the pixel opening PO and the slope angle β of the bottom surface of the first cut-off groove CUS1 is not less than 90°.

[0122] In some embodiments of this disclosure, one side wall of the first cut-off groove CUS1 is located in the first insulating layer CL1, and the other side wall is located in the third insulating layer CL3. This allows the included angle γ of the extended surfaces of the two side walls of the partition groove SES to be an acute angle, making the side wall located in the third insulating layer CL3 shorter than the side wall located in the first insulating layer CL1. In other words, the suspended portion of the third insulating layer CL3 corresponding to the first cut-off groove CUS1 is shorter than the portion of the first insulating layer CL1 corresponding to the first cut-off groove CUS1. While cutting off the light-emitting layer OL, this reduces the risk of the third insulating layer CL3 breaking due to the presence of the first cut-off groove CUS1.

[0123] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, for a pixel definition layer PDL with an extension PDL, a second cutoff groove CUS2 can be provided on the sidewall of at least a portion of the pixel opening PO. Since the pixel opening PO is located on the extension PDL, the second cutoff groove CUS2 is actually formed on the extension PDL. The charge generation layer CGL can be disconnected through the second cutoff groove CUS2, further preventing color crosstalk. The specific implementation of the second cutoff groove CUS2 can refer to the first cutoff groove CUS1. For example, the second cutoff groove CUS2 is formed on the second insulating layer CL2, and the third insulating layer CL3 is suspended at the second cutoff groove CUS2. At the same time, in order to avoid the extension PDL from causing large obstruction to the first electrode ANO, the range of the extension PDL is small. Correspondingly, the depth of the second cutoff groove CUS2 needs to be limited. Therefore, the maximum depth of the first cutoff groove CUS1 can be greater than the maximum depth of the second cutoff groove CUS2. While ensuring that the second cutoff groove CUS2 can cut off at least a portion of the light-emitting layer OL, it avoids its depth being too large and cutting off the extension PDL, which is beneficial to maintaining the stability of the structure.

[0124] Furthermore, a second cutoff groove CUS2 can be formed on the extension PDL of each first electrode ANO; alternatively, a second cutoff groove CUS2 can be formed on the extension PDL of the first electrode ANO of a specific light-emitting unit SUP. For example, in the color filter layer CF, the range of the blue filter CFU is larger than the range of the red and green filter CFUs, meaning that the area of ​​the blue filter CFU projected onto the driving backplane BP is larger than the area of ​​the red and green filter CFUs projected onto the driving backplane BP. The second cutoff groove CUS2 can be formed on the sidewall of the pixel opening PO of the blue sub-pixel, while the second cutoff groove CUS2 can be omitted from the pixel opening PO of the red and green sub-pixels.

[0125] In some embodiments of this disclosure, such as Figure 4As shown, for the first cut-off groove CUS1 and the second cut-off groove CUS2 formed in the second insulating layer CL2, the portion of the sidewall of the third insulating layer CL3 used to form the first cut-off groove CUS1 is inclined towards the drive back plate BP, and the inclination angle is a first inclination angle θ1. That is, the two sidewalls of the first cut-off groove CUS1 may not be parallel. The portion of the sidewall of the third insulating layer CL3 used to form the second cut-off groove CUS2 is inclined towards the drive back plate BP, and the inclination angle is a second inclination angle θ2. That is, the two sidewalls of the second cut-off groove CUS2 may not be parallel. The first inclination angle θ1 may be greater than the second inclination angle θ2, that is, the third insulating layer CL3 is more inclined in the region of the first cut-off groove CUS1 than in the region of the second cut-off groove CUS2.

[0126] like Figure 5 As shown, based on the morphology of the pixel definition layer (PDL) and the light-emitting layer (OL) described above, the second electrode CAT can form a flat portion CATp in the region corresponding to the first electrode ANO, and a recessed portion CATg in the region corresponding to the separator groove (SES). The recessed portion CATg and the flat portion CATp can be smoothly connected, avoiding sharp edges on the second electrode CAT. Due to the filling of the separator groove (SES) by the light-emitting layer (OL), the depth of the recessed portion CATg of the second electrode CAT is less than the depth of the separator groove (SES). Furthermore, the depth of the recessed portion CATg can be greater than the thickness of the filling layer (PBR).

[0127] Furthermore, in some embodiments of this disclosure, such as Figure 8 and Figure 9 As shown, for the case where the light-emitting layer OL is set up in the whole layer, that is, each light-emitting unit SUP shares the light-emitting layer OL, the impedance of the light-emitting layer OL between the light-emitting units SUP can be increased by aging treatment, thereby reducing the transverse conduction capability of the light-emitting layer OL and weakening the leakage current between adjacent light-emitting units SUP.

[0128] For example, the filler layer PBR may include a filler insulating layer PBRRi and a filler conductive layer PBRc stacked in a direction away from the drive backplane BP, wherein:

[0129] The material of the insulating layer PBR can be an insulating material such as silicon nitride or silicon oxide, and the insulating layer PBR is in contact with the sidewall of the first electrode ANO. The material of the conductive layer PBRc can be a metal or other conductive material, and it is spaced apart from the sidewall of the first electrode ANO, thereby insulating it from the first electrode ANO. In this case, the bottom of the partition groove SES does not have to be a plane; it can include the area of ​​the insulating layer PBR facing away from the drive backplate BP that is not covered by the conductive layer PBRc, and it also includes the surface of the conductive layer PBRc facing away from the drive backplate BP. The first cutoff groove CUS1 is located on the side of the conductive layer PBRc facing away from the drive backplate BP, that is, above the conductive layer PBRc. The cutoff layer PCL can cover the conductive layer PBRc or be located outside the conductive layer PBRc, as long as it does not affect the formation of the first cutoff groove CUS1.

[0130] The first electrode layer FE may further include a transition ring CR. The orthographic projection of the transition ring CR on the driving backplane BP is located in the peripheral area and surrounds the pixel area. The transition ring CR is connected to the peripheral circuit. The second electrode CAT is connected to the transition ring CR. The transition ring CR can be referred to the above-described embodiment and will not be repeated here. The transition ring CR is provided with a notch CRh to disconnect it.

[0131] The conductive filling layer PBRc may include a main body PBRc1 and a connecting part PBRc2. The main body PBRc is located inside the transition ring CR and is spaced apart from the transition ring CR, thereby insulating it from the transition ring CR. The connecting part PBRc2 is connected to the main body PBRc1 and extends out of the transition ring CR through a notch CRh, and is also spaced apart from the transition ring CR, meaning that the connecting part PBRc2 does not contact the notch CRh, thereby insulating it from the transition ring CR. The main body PBRc1 and the connecting part PBRc2 may be an integral structure and may be formed simultaneously.

[0132] The connecting part PBRc2 can be connected to the external circuit to receive the aging voltage signal. This allows it to cooperate with the second electrode CAT to apply an aging voltage to the light-emitting layer OL, causing the area of ​​the light-emitting layer OL corresponding to the main body PBRc1 to age, thus increasing its impedance. The aging voltage can be determined based on the material and thickness of the light-emitting layer OL; for example, it can be greater than 8V, 15V, 20V, 30V, etc., without special limitation, as long as it can age the light-emitting material OL. Furthermore, the duration of the aging voltage can be controlled to a specified duration, i.e., the duration of the aging voltage signal can be a specified duration. This specified duration can be no greater than 10 seconds, but can also be longer, as long as it can age the light-emitting material OL.

[0133] This disclosure also provides a method for manufacturing a display panel, which can be any of the display panels described in the above embodiments, and its structure will not be detailed here. The manufacturing method may include steps S110-S140, wherein:

[0134] Step S110: Form the drive backplane;

[0135] Step S120: A first electrode layer comprising a plurality of spaced first electrodes is formed on one side of the drive backplate.

[0136] Step S130: A pixel definition layer exposing each first electrode is formed on the side of the driving backplate on which the first electrode layer is formed; the pixel definition layer includes a filling layer and a cut-off layer stacked in a direction away from the driving backplate, the thickness of the filling layer is less than that of the first electrode layer and is located outside the first electrode; the cut-off layer is provided with a partition groove located outside the first electrode, and the sidewall of the partition groove is provided with a first cut-off groove.

[0137] Step S140: Form a light-emitting layer covering the cut-off layer and the first electrode layer;

[0138] Step S150: Form a second electrode covering the light-emitting layer.

[0139] Based on the above-described display panel having a filled insulating layer PBRi and a filled conductive layer PBRc, in some embodiments of this disclosure, the manufacturing method may include steps S110-S170, wherein:

[0140] Step S110: Form the drive backplane;

[0141] Step S120: A first electrode layer comprising a plurality of spaced first electrodes is formed on one side of the drive backplate.

[0142] Step S130: A pixel definition layer is formed on the side of the drive backplate where the first electrode layer is provided, exposing each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the drive backplate, the thickness of the fill layer is less than that of the first electrode layer, and it is located outside the first electrodes;

[0143] Step S140: Apply an aging voltage signal to the filled conductive layer and continue for a specified duration;

[0144] Step S150: Form a partition groove located outside the first electrode and a first cut-off groove located on the sidewall of the partition groove in the cut-off layer;

[0145] Step S160: Form a light-emitting layer covering the cut-off layer and the first electrode layer;

[0146] Step S170: Form a second electrode covering the light-emitting layer.

[0147] Since the details of the structures involved in each step of the above manufacturing method have been described in detail in the above-described implementation of the display panel, their details and beneficial effects will not be described in detail here.

[0148] It should be noted that although the various steps of the manufacturing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0149] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. The specific structure and beneficial effects of this display panel have been described in detail in the embodiments of the display panel above, and will not be repeated here. The display device of this disclosure can be used in electronic devices with image display functions such as watches, bracelets, mobile phones, and tablet computers, and will not be listed individually here.

[0150] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, wherein, include: Drive backplane; The first electrode layer is disposed on one side of the drive back plate and includes a plurality of first electrodes spaced apart. A pixel definition layer is disposed on the same side of the driving backplate as the first electrode layer, and exposes each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the driving backplate, the thickness of the fill layer is less than that of the first electrode layer, and it is located outside the first electrodes; the cut-off layer has a partition groove located outside the first electrodes, and the sidewall of the partition groove has a first cut-off groove; the fill layer includes a fill insulating layer and a fill conductive layer stacked in a direction away from the driving backplate, the fill insulating layer is in contact with the sidewall of the first electrode, and the fill conductive layer is spaced apart from the sidewall of the first electrode; A light-emitting layer covers the cut-off layer and the first electrode layer; The second electrode covers the light-emitting layer.

2. The display panel according to claim 1, wherein, The cut-off layer includes a plurality of insulating layers stacked in a direction away from the drive backplate, and the partition groove exposes the filling layer; the first cut-off groove is formed in an insulating layer, and the insulating layer in which the first cut-off groove is located is any insulating layer other than the insulating layer farthest from the drive backplate.

3. The display panel according to claim 1, wherein, The insulating layer of the cut-off layer includes a first insulating layer, a second insulating layer and a third insulating layer stacked sequentially in a direction away from the drive back plate, and the first cut-off groove is formed in the second insulating layer.

4. The display panel according to claim 3, wherein, The sidewall of the partition groove is a slope that expands in a direction away from the drive back plate.

5. The display panel according to claim 4, wherein, The bottom surface of the first cut-off groove is a slope that reduces its depth in the direction away from the drive back plate.

6. The display panel according to claim 5, wherein, The slope angle of the bottom surface of the first cut-off groove is greater than the slope angle of the partition groove on the side wall of the first insulating layer, and also greater than the slope angle of the partition groove on the side wall of the third insulating layer.

7. The display panel according to claim 5, wherein, The sum of the slope angle of the bottom surface of the first cutting groove and the slope angle of the side wall of the dividing groove located in the first insulating layer is not greater than 90°.

8. The display panel according to claim 5, wherein, The sum of the slope angle of the bottom surface of the first cut-off groove and the slope angle of the side wall of the partition groove located in the third insulating layer is not greater than 90°.

9. The display panel according to claim 4, wherein, The included angle between the extended surfaces of the two side walls of the partition groove is an acute angle.

10. The display panel according to claim 5, wherein, The cut-off layer includes a cut-off portion and an extension portion. The cut-off portion is located outside the first electrode, and the extension portion is located on the surface of the first electrode opposite to the driving backplate, and has a pixel opening that exposes the first electrode. The sidewall of the pixel opening is a slope that expands in a direction away from the drive backplate.

11. The display panel according to claim 10, wherein, The sum of the slope angle of the sidewall of the pixel opening and the slope angle of the bottom surface of the first cut-off groove is not less than 90°.

12. The display panel according to claim 10, wherein, At least a portion of the pixel openings have a second cut-off groove on their sidewalls.

13. The display panel according to claim 12, wherein, The maximum depth of the first cut-off groove is greater than the maximum depth of the second cut-off groove.

14. The display panel according to claim 13, wherein, The portion of the third insulating layer that forms the sidewall of the first cut-off groove is inclined toward the drive back plate, and the inclination angle is a first inclination angle. The portion of the third insulating layer that forms the second cut-off groove is inclined toward the drive back plate, and the inclination angle is the second inclination angle. The first tilt angle is greater than the second tilt angle.

15. The display panel according to any one of claims 1-14, wherein, The second electrode forms a flat portion in the region corresponding to the first electrode and a recessed portion in the region corresponding to the dividing groove, the recessed portion and the flat portion transitioning smoothly.

16. The display panel according to claim 15, wherein, The depth of the recess is less than the depth of the dividing groove.

17. The display panel according to claim 15, wherein, The depth of the recess is greater than the thickness of the filling layer.

18. The display panel according to any one of claims 1-14, wherein, The filling layer is in contact with the sidewall of the first electrode.

19. The display panel according to claim 15, wherein, The light-emitting layer further includes multiple light-emitting sub-layers connected in series, at least one of the light-emitting sub-layers being connected in series with an adjacent light-emitting sub-layer through a charge generation layer; the portion of the charge generation layer corresponding to the first electrode and the portion corresponding to the separator groove are disconnected.

20. The display panel according to claim 1, wherein, The driving backplane includes a pixel area and a peripheral area located outside the pixel area; the pixel area has a pixel circuit for driving the light-emitting layer to emit light, and the peripheral area has a peripheral circuit; The first electrode layer further includes a transition ring, the orthographic projection of which on the driving backplate is located in the peripheral area and surrounds the pixel area. The transition ring is connected to the peripheral circuit, and the second electrode is connected to the transition ring. The transition ring has a notch. The conductive filling layer includes a main body and a connecting part. The main body is located inside the adapter ring and is spaced apart from the adapter ring. The connecting part is connected to the main body and extends out of the adapter ring through the notch, and is spaced apart from the adapter ring. The connecting part is used to receive aging voltage signals.

21. A method for manufacturing a display panel, wherein the display panel is the display panel of claim 20, the manufacturing method comprising: Forming a drive backplate; A first electrode layer comprising a plurality of spaced first electrodes is formed on one side of the drive back plate; A pixel definition layer is formed on the side of the drive backplate where the first electrode layer is provided, exposing each of the first electrodes; the pixel definition layer includes a fill layer and a cut-off layer stacked in a direction away from the drive backplate, the thickness of the fill layer is less than that of the first electrode layer, and it is located outside the first electrodes; An aging voltage signal is applied to the conductive filling layer and maintained for a specified duration; A partition groove located outside the first electrode and a first cut-off groove located on the sidewall of the partition groove are formed in the cut-off layer; A light-emitting layer is formed covering the cut-off layer and the first electrode layer; A second electrode is formed to cover the light-emitting layer.

22. A display device, wherein, Includes the display panel as described in any one of claims 1-20.

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