Low-power data acquisition system and control method to improve serial data communication performance

Abstract

This invention discloses a low-power acquisition system and control method for improving serial data communication performance, relating to the field of electronic communication. The system includes: a serial-in / serial-out FIFO memory block, a host serial signal path selector, a host serial signal control block, a slave serial signal control block, a CPU serial communication peripheral host, and an ADC serial communication slave. Through a host serial signal path selector, the CPU can control in real-time to enter two modes: a pass-through state where the serial communication signal line of the host serial communication peripheral is directly connected to the ADC serial communication slave; or a FIFO state where the host serial signal control block controls the serial signal path selector, and the serial interfaces of the host and slave are respectively connected to the serial-in / serial-out FIFO memory block to buffer the FIFO state of data uploaded by the ADC serial communication slave. This invention can automatically switch signal paths, perform timing protection, and clear the buffered data in the FIFO memory unit based on changes in the signal path selected by the CPU in real time.

Description

Technical Field

[0001] This invention relates to the field of electronic communication technology, and in particular to a low-power acquisition system and control method for improving the performance of serial data communication. Background Technology

[0002] For low-power data acquisition systems, especially wearable devices, many applications require circuit designs that are adapted to analog-to-digital data acquisition needs. This necessitates designing a stable ADC (Analog-to-digital converter) readout interface with sufficient bandwidth, a perennial topic in mixed-signal circuit design. Currently, when striving to maximize performance while maintaining low power consumption, interface engineering issues arise, limiting absolute performance gains. This is particularly evident in specialized wearable monitoring fields requiring high performance specifications, especially in portable medical data acquisition devices (AEEG, EMG, multi-channel Holter monitoring). Medical high-performance data acquisition ADCs, due to their low sampling rate and small package size, employ serial output, with the SPI interface currently being the mainstream design. Serial output timing requirements are complex, and in multi-channel, master-slave read applications, the overhead of frequently switching slaves using the bus's I / O mechanism is significant. Often, additional designs such as daisy-chain logic are needed to fully utilize the advantages of the serial bus. Σ-Δ type ADCs output sampled data at equal time intervals. Within a sampling interval, the quantized sampled data must be read promptly; otherwise, it will be overwritten by the next data, causing acquisition errors. This is strictly prohibited in medical data acquisition, as it can produce false positive waveforms and interfere with judgment.

[0003] The Σ-Δ ADC suitable for high-performance medical data acquisition requires a specific clock to drive the Σ-Δ modulator (usually a specially designed crystal oscillator with a power of 2 frequency) in order to obtain an integer sampling rate for subsequent digital domain algorithm processing. Therefore, the digital interface of the ADC often has strict timing requirements and has cross-clock domain characteristics (crossing the serial bus clock and the ADC sampling master clock). When synchronously reading data and writing instructions, special timing requirements need to be met, and additional waiting time needs to be inserted at necessary points to allow the ADC's timing / clock stretching operation to complete.

[0004] To meet low-power requirements, the digital system used to forward primary data on the read side is typically implemented using a low-power MCU, or even a communication-type System-on-Chip (SoC). While these systems are highly energy efficient and feature-rich, their integrated SPI bus host read section is generally quite simple. When handling the complex timing requirements mentioned above, the CPU often needs to be fully involved in the ADC's I / O, leading to additional power consumption. Furthermore, CPU time is frequently consumed by sampling completion interrupts, significantly compressing the processing time available for data forwarding I / O. Ultimately, as the sampling rate increases, the CPU clock speed limits the digital system's performance. This is the main reason for the performance limitations of low-power wearable devices currently on the market: the lighter and lower the power consumption, the lower the level of the CPU system used, resulting in lower performance.

[0005] Using a serial bus similar to SPI to achieve data interaction between the CPU chip and the ADC chip can be divided into two tasks: Most of the time, the ADC acts as a slave, outputting sampled data to the CPU chip at equal time intervals; in rare instances (system power-on initialization, user modification of acquisition parameters, etc.), the CPU, acting as the master, needs to set the ADC chip's acquisition parameters (such as sampling rate, analog switch status, etc.) and send start / stop commands for acquisition. The data reading task is simple but runs repeatedly at sampling intervals, directly consuming considerable CPU resources. Adding automated digital reading logic and FIFO logic can significantly improve reading efficiency. The configuration time for the ADC chip is relatively short, and the acquisition system generally does not require parameter modification without interrupting acquisition. Therefore, the flexibility and ease of delay in CPU programming can be fully utilized to perform traditional CPU sequential programming to complete this task.

[0006] Therefore, addressing the performance bottleneck of low-power ADC acquisition-forward systems, the urgent issues to be resolved include: how to automate the reading of periodic sampling results with minimal hardware cost and cache them in FIFO logic for high-speed CPU access; how to balance efficiency with minimal changes to the debugging methods and routine code of the CPU-based ADC configuration task, which involves a large amount of programming; and how to design the switching logic for the two parts of digital logic corresponding to the two tasks and the corresponding digital logic circuit design and implementation methods. Summary of the Invention

[0007] The purpose of this invention is to provide a low-power acquisition system that improves the performance of serial data communication, adapts to the data interface of an external ADC chip, enables controlled switching of signal communication, and provides automated data acquisition reading and caching functions based on a FIFO storage unit. The system is characterized by minimizing changes to the existing hardware circuitry of the acquisition system, preserving the existing driver code debugging results to the greatest extent, and achieving a significant improvement in acquisition performance and energy efficiency.

[0008] To achieve the above objectives, the present invention provides the following solution: A low-power data acquisition system for improving serial data communication performance includes: a serial-in / serial-out FIFO storage block, a host serial signal path selector, a host serial signal control block, a slave serial signal control block, a CPU serial communication peripheral host, and an ADC serial communication slave. The CPU serial communication peripheral host is connected to the host serial signal path selector. The host serial signal path selector is connected to the ADC serial communication slave via one line and to the serial-in / serial-out FIFO storage block via another line. The serial-in / serial-out FIFO storage block is connected to the ADC serial communication slave. The serial-in / serial-out FIFO storage block is also connected to the host serial signal control block and the slave serial signal control block. The host serial signal control block is connected to the host serial signal path selector and controls the host serial signal path selector to switch between two operating states: pass-through mode and FIFO mode.

[0009] Furthermore, the maximum speed of the serial communication interface of the CPU serial communication peripheral host is greater than the maximum speed of the serial communication interface of the ADC serial communication slave.

[0010] Furthermore, the host serial signal control block uses a 1-bit dedicated signal to control the host serial signal path selector, switching between two working states: direct-through and FIFO.

[0011] This invention also provides a control method for a low-power acquisition system to improve the performance of serial data communication, the method comprising: Step S1: Enter FIFO state: Configure the operating parameters of the CPU serial communication peripheral master and slave communication control block; Step S2: Logic enters pass-through state: The host serial signal control block controls the serial signal path selector to pass through the serial interface between the CPU serial communication host and the ADC serial communication slave. The CPU in the CPU serial communication host directly controls the chip select timing and data transmission and reception process of the serial bus. Step S3: Configure ADC operating parameters via serial pass-through; Step S4: Command the ADC to start continuous data acquisition; Step S5: Logic enters FIFO state: The host serial signal control block controls the serial signal path selector to connect the serial interfaces of the CPU serial communication peripheral host and the ADC serial communication slave to the serial-in serial-out FIFO storage block respectively; the slave serial signal control block detects the "data ready" signal at the slave end. If the "data ready" signal is detected, the slave serial signal control block generates a serial synchronization clock on its behalf. The ADC end of the ADC serial communication slave reads the data that has been converted in this time and pushes the data bit by bit into the serial-in serial-out FIFO storage block. Step S6: Determine whether the data in the serial-in / serial-out FIFO storage block is full. If yes, the CPU serial communication peripheral host reads the data in the serial-in / serial-out FIFO storage block and proceeds to the next step S7; otherwise, return to step S6. Step S7: The CPU calls the DMA hardware to perform a burst read of the data stored in the FIFO. Step S8: During the data reading interval, the CPU determines at any time whether the parameters need to be modified; if yes, it enters the pass-through state and returns to step S2; if no, it returns to step S6.

[0012] Furthermore, the method also includes: When transitioning from the pass-through state to the FIFO state: The ADC chip of the ADC serial communication slave is configured and sends a start acquisition command in the pass-through state, ready to receive data; at this time, the serial-in serial-out FIFO storage block read / write pointer is automatically reset, and the slave's "data ready" signal detection mechanism is enabled, ready to receive the converted data at any time; When transitioning from FIFO state to pass-through state: the conversion of the ADC chip of the ADC serial communication slave is interrupted, and a stop acquisition command is sent in pass-through mode; at this time, the slave serial signal control block will stop working, ignore the subsequent "data ready" signal, and hand over the bus control to the sequential program of the CPU serial communication peripheral host for instruction control.

[0013] Furthermore, the CPU serial communication peripheral host configures the host serial signal control block and the slave serial signal control block. The configuration process operates in FIFO mode. Specifically, in FIFO mode, the CPU serial communication host configures the corresponding control registers of the host serial signal control block and the slave serial signal control block through the specified synchronous serial communication protocol, completes the configuration of the operating parameters required during operation, and can perform readback query confirmation.

[0014] According to specific embodiments provided by the present invention, the following technical effects are disclosed: The present invention proposes a low-power acquisition system that improves the performance of serial data communication, balancing the control requirements of the CPU and ADC with the CPU reading requirements for continuous data output from the ADC, achieving a simultaneous improvement in both absolute acquisition performance and energy efficiency of the overall low-power acquisition system; due to the adoption of a simple host control bus data path selector scheme, the additional digital logic hardware required to complete this design is very small, and it is easy to instantiate in low-cost, small-scale programmable devices and low-power CPU peripheral digital logic designs; this digital logic design can be inserted without significantly changing the existing CPU's debugged adaptation code, making full use of existing software development resources and routines. The present invention can push the data throughput limit of the ADC acquisition-transfer system to the speed limit of the serial interface peripheral of the host CPU; during non-host reading times, the host CPU can process forwarding tasks and promptly hibernate when idle, reducing power consumption. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a structural diagram of a low-power acquisition system for improving serial data communication performance according to an embodiment of the present invention; Figure 2 This is a flowchart of a low-power acquisition method for improving serial data communication performance according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The purpose of this invention is to provide a low-power acquisition system that improves the performance of serial data communication. It can realize automatic switching of signal paths, timing protection, and clearing of data cached in FIFO storage units. At the same time, it can minimize changes to the hardware circuit of existing acquisition systems, preserve the existing driver code debugging results to the greatest extent, and achieve a significant improvement in acquisition performance and energy efficiency.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1 As shown in the figure, the low-power acquisition system for improving serial data communication performance provided by this embodiment of the invention includes: a serial-in / serial-out FIFO storage block, a host serial signal path selector, a host serial signal control block, a slave serial signal control block, a CPU serial communication peripheral host, and an ADC serial communication slave; the CPU serial communication peripheral host is connected to the host serial signal path selector; the host serial signal path selector is connected to the ADC serial communication slave through one line and to the serial-in / serial-out FIFO storage block through another line, and the serial-in / serial-out FIFO storage block is connected to the ADC serial communication slave; the serial-in / serial-out FIFO storage block is also connected to the host serial signal control block and the slave serial signal control block, the host serial signal control block is connected to the host serial signal path selector, and the host serial signal control block controls the host serial signal path selector to switch between two working states: direct-through state and FIFO state.

[0021] This invention is based on a master-slave serial communication architecture and is a lightweight supplement to existing commonly used serial communication buses. The basic requirements for applying this invention are very low; it only requires that the maximum speed of the serial communication interface of the CPU serial communication peripheral host is greater than the maximum speed of the serial communication interface of the ADC serial communication slave. The host serial signal control block uses a 1-bit dedicated signal to control the host serial signal path selector, switching between two working states: pass-through and FIFO.

[0022] like Figure 2 As shown, the control method for a low-power acquisition system that improves serial data communication performance provided in this embodiment of the invention includes: Step S1: Enter FIFO state: Configure the operating parameters of the CPU serial communication peripheral master and slave communication control block; Step S2: Logic enters pass-through state: The host serial signal control block controls the serial signal path selector to pass through the serial interface between the CPU serial communication host and the ADC serial communication slave. The CPU in the CPU serial communication host directly controls the chip select timing and data transmission and reception process of the serial bus. Step S3: Configure ADC operating parameters via serial pass-through; Step S4: Command the ADC to start continuous data acquisition; Step S5: Logic enters FIFO state: The host serial signal control block controls the serial signal path selector to connect the serial interfaces of the CPU serial communication peripheral host and the ADC serial communication slave to the serial-in serial-out FIFO storage block respectively; the slave serial signal control block detects the "data ready" signal at the slave end. If the "data ready" signal is detected, the slave serial signal control block generates a serial synchronization clock on its behalf. The ADC end of the ADC serial communication slave reads the data that has been converted in this time and pushes the data bit by bit into the serial-in serial-out FIFO storage block. Step S6: Determine whether the data in the serial-in / serial-out FIFO storage block is full. If yes, the CPU serial communication peripheral host reads the data in the serial-in / serial-out FIFO storage block and proceeds to the next step S7; otherwise, return to step S6. Step S7: The CPU calls hardware such as DMA to perform a burst read of the data already stored in the FIFO; Step S8: During the data reading interval, the CPU determines at any time whether the parameters need to be modified; if yes, it enters the pass-through state and returns to step S2; if no, it returns to step S6.

[0023] The control method for improving the performance of a low-power data acquisition system provided in this embodiment further includes: When transitioning from pass-through state to FIFO state: The ADC chip of the ADC serial communication slave device is configured and sends a start acquisition command in pass-through state, ready to receive data; at this time, the serial-in serial-out FIFO storage block read / write pointer is automatically reset, and the slave device's "data ready" signal detection mechanism is enabled, ready to receive the converted data at any time; When transitioning from FIFO state to pass-through state: the conversion of the ADC chip of the ADC serial communication slave is interrupted, and a stop acquisition command is sent in pass-through mode; at this time, the slave serial signal control block will stop working, ignore the subsequent "data ready" signal, and hand over the bus control to the sequential program of the CPU serial communication peripheral host for instruction control.

[0024] In this embodiment, when the FIFO storage capacity is sufficient, the real-time periodic reading and pushing of ADC serial communication slave data into the FIFO requires no intervention from the host CPU. The host CPU can query the FIFO's usage status through the host serial signal control block, or use a programmable interrupt mode to have the host serial signal control block output an interrupt to notify the CPU of the current FIFO usage status. When the FIFO is not full, the CPU uses high-speed data transfer methods such as DMA, which consume almost no CPU resources, to read the data stored in the FIFO in a short time using burst transmission, so that the slave serial signal control block can continue to push new acquired data.

[0025] In this embodiment, before the system operates, the host needs to properly configure the host serial signal control block and the slave serial signal control block. The configuration process operates in FIFO mode to avoid misconfiguration on the slave side. In FIFO mode, the host can configure the corresponding control registers of the host and slave serial signal control blocks via a common serial communication line using the synchronous serial communication protocol specified in this digital logic. This completes the initial configuration of the operating parameters required during operation and allows for readback confirmation. Commonly used host serial signal control block operating parameters include: maximum FIFO bit storage depth, current FIFO storage usage (read-only), and CPU interrupt signal trigger threshold when storage is full. Commonly used ADC serial communication slave serial signal control block operating parameters include: slave data read clock frequency, ADC serial communication slave serial signal clock polarity and data polarity, and the number and edge polarity of data bits automatically read when a "data ready" signal is triggered.

[0026] The remaining technical features in this embodiment can be flexibly selected by those skilled in the art to meet different specific practical needs. However, it is obvious to those skilled in the art that these specific details are not necessary to implement the present invention. In other instances, to avoid obscuring the present invention, well-known components, structures, or parts are not specifically described, and all are within the scope of technical protection defined by the claims of the present invention.

[0027] Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of this invention should be within the protection scope of the appended claims. In the above description, numerous specific details have been set forth to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, to avoid obscuring the invention, well-known techniques, such as specific construction details, operating conditions, and other technical conditions, have not been specifically described.

[0028] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A low-power data acquisition system for improving serial data communication performance, characterized in that, include: The system includes a serial-in / serial-out FIFO storage block, a host serial signal path selector, a host serial signal control block, a slave serial signal control block, a CPU serial communication peripheral host, and an ADC serial communication slave; the CPU serial communication peripheral host is connected to the host serial signal path selector. The host serial signal path selector is connected to the ADC serial communication slave through one line and to the serial-in serial-out FIFO storage block through another line. The serial-in serial-out FIFO storage block is connected to the ADC serial communication slave. The serial-in serial-out FIFO storage block is also connected to the host serial signal control block and the slave serial signal control block. The host serial signal control block is connected to the host serial signal path selector and controls the host serial signal path selector to switch between two working states: direct-through state and FIFO state. The control method for the low-power acquisition system that improves serial data communication performance includes the following steps: Step S1: Enter FIFO state: Configure the operating parameters of the CPU serial communication peripheral master and slave serial signal control block; Step S2: Logic enters pass-through state: The host serial signal control block controls the host serial signal path selector to pass through the serial interface between the CPU serial communication peripheral host and the ADC serial communication slave. The CPU in the CPU serial communication peripheral host directly controls the chip select timing and data transmission and reception process of the serial bus. Step S3: Configure ADC operating parameters via serial pass-through; Step S4: Command the ADC to start continuous data acquisition; Step S5: Logic enters FIFO state: The host serial signal control block controls the host serial signal path selector to connect the serial interfaces of the CPU serial communication peripheral host and the ADC serial communication slave to the serial-in serial-out FIFO storage block respectively; the slave serial signal control block detects the "data ready" signal at the slave end. If the "data ready" signal is detected, the slave serial signal control block generates a serial synchronization clock on its behalf. The ADC end of the ADC serial communication slave reads the data that has been converted in this time and pushes the data bit by bit into the serial-in serial-out FIFO storage block; Step S6: Determine whether the data in the serial-in / serial-out FIFO storage block is full. If yes, the CPU serial communication peripheral host reads the data in the serial-in / serial-out FIFO storage block and proceeds to the next step S7; otherwise, return to step S6. Step S7: The CPU calls the DMA hardware to perform a burst read of the data stored in the serial-in / serial-out FIFO storage block; Step S8: During the data reading interval, the CPU determines at any time whether the parameters need to be modified; if yes, it enters the pass-through state and returns to step S2; if no, it returns to step S6.

2. The low-power acquisition system for improving serial data communication performance according to claim 1, characterized in that, The maximum speed of the serial communication interface of the CPU serial communication peripheral host is greater than the maximum speed of the serial communication interface of the ADC serial communication slave.

3. The low-power acquisition system for improving serial data communication performance according to claim 1, characterized in that, The host serial signal control block uses a 1-bit dedicated signal to control the host serial signal path selector, switching between two working states: direct-through and FIFO.

4. The low-power acquisition system for improving serial data communication performance according to claim 1, characterized in that, The method further includes: When transitioning from pass-through state to FIFO state: The ADC chip of the ADC serial communication slave is configured and sends a start acquisition command in pass-through state to prepare to receive data; at this time, the serial-in serial-out FIFO storage block read / write pointer is automatically reset and the slave's "data ready" signal detection mechanism is enabled, ready to receive the converted data at any time; When transitioning from FIFO state to pass-through state: the conversion of the ADC chip of the ADC serial communication slave is interrupted, and a stop acquisition command is sent in pass-through mode; at this time, the slave serial signal control block will stop working, ignore the subsequent "data ready" signal, and hand over the bus control to the sequential program of the CPU serial communication peripheral host for instruction control.

5. The low-power acquisition system for improving serial data communication performance according to claim 1, characterized in that, The method further includes: The CPU serial communication peripheral host configures the host serial signal control block and the slave serial signal control block. The configuration process operates in FIFO mode. Specifically, in FIFO mode, the CPU serial communication peripheral host configures the corresponding control registers of the host serial signal control block and the slave serial signal control block through the specified synchronous serial communication protocol. This completes the configuration of the operating parameters required during operation and allows for readback and confirmation.

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