Trim method for flash memory devices

Abstract

The application discloses a trim method of a flash memory device, which comprises the following steps: receiving a current trim command issued by a host; detecting whether the trim command is an erase command for all logical addresses; if yes, directly resetting the mapping relationship of all map tables; if not, performing the following steps; detecting whether the trim command is an erase command across at least one map table; if yes, directly resetting the mapping relationship in the crossed map table, and then erasing the mapping relationship corresponding to the remaining logical address in the trim command; if not, performing the following steps; counting a plurality of trim commands, sorting the logical addresses in the plurality of trim commands to form a logical unit; and when the logical unit satisfies a first preset condition, erasing the mapping relationship in the map table corresponding to the logical unit. After the above scheme is adopted, the erase can be performed according to different types of trim commands, and high erase efficiency can be provided for each type of trim command.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more particularly to a trim method for a flash memory device. Background Technology

[0002] Flash memory is a semiconductor-based memory with advantages such as low power consumption, large capacity, high access speed, no mechanical failures, and non-volatility of data. With the rapid increase in flash memory storage capacity, people are placing increasingly higher demands on the flexibility of data operations, making data storage management in flash memory an unavoidable issue. Flash memory, especially NAND flash, is widely used in mobile storage devices such as USB flash drives, SD (Secure Digital Memory Card) cards, and SSD (Solid State Disk) hard drives. Due to the characteristics of flash memory, the same page cannot be reprogrammed; it must be erased before reprogramming.

[0003] Currently, when erasing a trim command issued by a host, it is generally necessary to traverse the corresponding mapping table, first find and read the mapping table, then rewrite the mapping relationship, and finally write the mapped data back. The entire erasure process is inefficient, resulting in slow write speeds. Summary of the Invention

[0004] The purpose of this application is to provide a trim method for flash memory devices to improve erasure efficiency.

[0005] This application discloses a trim method for a flash memory device, including the following steps:

[0006] Receive the current trim command issued by the host;

[0007] The system checks whether the trim command erases all logical addresses on the disk; if so, it directly resets the mapping relationships of all map tables; if not, it proceeds to the next steps.

[0008] Detect whether the trim command is an erase command that spans at least one map table; if so, directly reset the mapping relationship in the map tables it spans, and then erase the mapping relationship corresponding to the remaining logical address in the trim command; if not, proceed to the next steps.

[0009] Counting multiple trim commands, sorting the logical addresses of the multiple trim commands to form logical units; and

[0010] When the logic unit meets the first preset condition, the mapping relationship in the map table corresponding to the logic unit is erased.

[0011] Optionally, when it is detected that the trim command is an erase command that spans at least one map table; the steps of detecting whether the trim command is an erase command that spans at least one map table; if yes, directly reset the mapping relationship in the map tables that are spanned, and then erase the mapping relationship corresponding to the remaining logical address in the trim command; if no, the subsequent steps include:

[0012] Align the start of the logical address in the trim command with the data in the first map table, and align the end of the logical address in the trim command with the data in the second map table; and

[0013] The mapping relationship in the map tables between the first map and the second map table is directly reset.

[0014] Optionally, after resetting the mapping relationship in the map tables between the first map and the second map table, the first map table is traversed to erase the start end of the logical address corresponding to the trim command, and the second map table is traversed to erase the end end of the logical address corresponding to the trim command.

[0015] Optionally, after resetting the mapping relationship in the map tables between the first map and the second map tables, the start end and the end end of the logical address in the trim command are counted in the logical unit.

[0016] Optionally, the step of counting multiple trim commands and sorting the logical addresses of the multiple trim commands to form logical units includes:

[0017] The received trim command is temporarily stored in a register; and

[0018] The logical addresses in the trim commands are arranged sequentially according to their logical address size relationship, so that the arranged logical addresses form a logical unit.

[0019] Optionally, multiple trim commands correspond to different map tables; when the map tables corresponding to multiple trim commands are arranged adjacently in sequence, the logic unit satisfies the first preset condition.

[0020] Optionally, when the logical address in the logical unit spans the entire map table, the mapping relationship in the map table being spanned is directly reset.

[0021] Optionally, multiple trim commands may correspond to the same map table; when the logical addresses of multiple trim commands are connected, the logical unit satisfies the first preset condition.

[0022] Optionally, the first preset condition is a preset number of trim commands, or an accumulated preset number of logical addresses.

[0023] Optionally, in the step of counting multiple trim commands and sorting the logical addresses of the multiple trim commands to form a logical unit, if the data read by the host is the data corresponding to the trim command being counted, then empty data is responded according to the bus protocol.

[0024] The technical solution adopted in this application has strong applicability to full disk erasure, erasure across the entire map table, and partial erasure; moreover, it can perform targeted erasure according to different types of trim commands, and can provide high erasure efficiency for each type of trim command. Attached Figure Description

[0025] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0026] Figure 1 This is a schematic flowchart of a trim method for a flash memory device provided in an embodiment of this application;

[0027] Figure 2 This is a flowchart illustrating a specific step based on step S2, as provided in an embodiment of this application.

[0028] Figure 3 This is a flowchart of a specific step based on step S4 provided in an embodiment of this application. Detailed Implementation

[0029] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0030] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Furthermore, terms indicating orientation or positional relationships, such as "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," are based on the orientation or relative positional relationships shown in the accompanying drawings and are merely for the purpose of simplifying the description of this application. They do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting this application.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] like Figure 1 As shown, this application embodiment provides a trim method for a flash memory device, including the following steps:

[0033] S1: Receive the current trim command issued by the host;

[0034] S2: Detect whether the trim command is an erase command for the entire disk's logical address; if yes, directly reset the mapping relationship of all map tables and complete the current trim command; if no, proceed to the next step S3;

[0035] S3: Detect whether the trim command is an erase command that spans at least one map table; if yes, directly reset the mapping relationship in the map table that it spans, and then erase the mapping relationship corresponding to the remaining logical address in the trim command to complete the current trim command; if no, proceed to the next step S4.

[0036] S4: Count the multiple trim commands, and sort the logical addresses in the multiple trim commands to form a logical unit;

[0037] S5: When the logic unit satisfies the first preset condition, the mapping relationship in the map table corresponding to the logic unit is erased.

[0038] Currently, the common practice for full-disk data trimming is to traverse all mapping tables and erase them one by one, except for write-protected tables. This application, for full-disk data trimming, directly resets the mapping relationships of all map tables, eliminating the need to traverse each table individually, thus improving erasure efficiency. Specifically, when it is determined that a full-disk data trimming is required, the firmware (the software embedded in the device that handles business logic) directly clears data mapping tables, FTL management tables, and physical block data description tables in the flash memory device, thereby directly resetting all mapping relationships and restoring the flash memory device to a new disk state.

[0039] For a Trim operation spanning an entire map table, the common approach is to traverse all logical addresses in the map table and erase each address individually. This application, however, directly resets the mapping relationships within the map table it spans, eliminating the need to erase each logical address and thus improving erasure efficiency.

[0040] When the current trim command issued by the host is neither a full disk data trim nor a trim that spans an entire map table, then only scattered trims remain. This means the logical addresses in the trim are distributed only within a single mapping table or adjacent mapping tables. For scattered trims, the common practice is for the host to execute the command immediately upon issuance. Specifically, upon receiving a trim command, the mapping relationship corresponding to the logical address in the trim command is immediately erased. This involves first finding and reading the mapping table corresponding to the logical address, then rewriting the mapping relationship, and finally writing the mapped data back. This application, however, does not directly erase the mapped data for scattered trims. Instead, it first records the logical address corresponding to the trim, as well as the logical addresses corresponding to multiple subsequent scattered trims. Then, it sorts these logical addresses. When a first preset condition is met, the overall mapped data can be erased sequentially according to the sorted relationship, without frequently erasing the mapped data in different mapping tables, thus also improving erasure efficiency.

[0041] The technical solution of this application can be applied to a variety of different erasure schemes and has strong applicability; moreover, it can perform targeted erasure according to different types of trim commands and provide high erasure efficiency for each type of trim command.

[0042] Specifically, such as Figure 2 As shown, in step S2, when the trim command is detected to be an erase command that spans at least one map table, the specific steps include the following:

[0043] S21: Align the start of the logical address in the trim command with the data in the first map table, and align the end of the logical address in the trim command with the data in the second map table;

[0044] S22: Directly reset the mapping relationship in the map table between the first map and the second map table.

[0045] For ease of understanding, the embodiments of this application are illustrated with the following example: the logical address range of map table A is 0-99, the logical address range of map table B is 100-199, the logical address range of map table C is 200-299, and the logical address range configured by the trim command is 56-255. If the technical solution of this embodiment is adopted, 56 will be used as the start of the logical address in the trim command, and 255 will be used as the end of the logical address in the trim command; the start of the logical address in the trim command will be aligned with the logical address 56 in map table A, and the end of the logical address in the trim command will be aligned with the logical address 255 in map table C. Since map table B is spanned by the logical address range configured by the trim command, the mapping relationship in map table B can be directly reset without needing to traverse the mapping relationship in map table B one by one. Of course, the range 56-99 in the logical address configured by the trim command can also be regarded as the start of the logical address in the trim command, and the range 200-255 in the logical address configured by the trim command can be regarded as the end of the logical address in the trim command.

[0046] Furthermore, after resetting the mapping relationships in map table B, for the logical address range of 56-99 in map table A and the logical address range of 200-255 in map table C, the mapping tables can be traversed individually for one-by-one erasure. Alternatively, the trim command corresponding to the logical address of this part of the mapping relationship to be erased can be directly transmitted to step S4 for processing. That is, the start end and end end of the logical address in the trim command are counted into the logical unit. Subsequently, multiple trim commands are counted and arranged together before erasure.

[0047] like Figure 3 As shown, step S4 specifically includes the following steps:

[0048] S41: Temporarily store the received trim command in a register;

[0049] S42: Arrange the logical addresses in the trim commands in sequence according to the size relationship of the logical addresses, so that the arranged logical addresses form a logical unit.

[0050] For scattered trims, the firmware needs to modify the values ​​of hardware registers, perform additional processing for the data accessed by the firmware using these logical addresses, and sort and record the logical addresses already issued by the host. Once the recorded trim logical addresses meet certain conditions, an action to unmap the relationships is triggered, saving additional map reads and traversals.

[0051] During the S4 step, if the host reads data, it first checks whether the data is trim data. If the data read by the host is the data corresponding to the trim command being counted, it responds with empty data according to the bus protocol.

[0052] In step S42, if multiple trim commands correspond to different map tables, and the map tables corresponding to multiple trim commands are arranged sequentially adjacent to each other, the logic unit satisfies the first preset condition.

[0053] For example, assuming a mapping table contains 1000 logical addresses, numbered starting from 0: Command 1 needs to load mapping table numbers 5 and 6, Command 2 needs to load mapping table numbers 0 and 1, Command 3 needs to load mapping table numbers 3, 4, and 5, Command 4 needs to load mapping table number 2, and Command 5 needs to load mapping table number 5. Using the current method, completing commands 1-5 requires loading nine mapping tables sequentially: 5, 6, 0, 1, 3, 4, 5, 2, and 5. However, with the solution of this application embodiment, commands 1-5 are grouped together, and after sorting, only seven mapping tables (0, 1, 2, 3, 4, 5, and 6) are needed. Furthermore, these are arranged into a continuous table that can be processed directly, saving significant time.

[0054] Furthermore, if the logical addresses in multiple commands overlap to form a continuous range of logical addresses, and this range spans the entire map table, the mapping relationship in the spanned map table can be directly reset, thereby further reducing the traversal of the mapping table.

[0055] For example: if the logical address in command 1 is 5001-5599, the logical address in command 2 is 2500-5000, and the logical address in command 3 is 5600-6500; after recording and arranging the logical addresses in the three commands, we get the logical address range of 2500-6500, which is the logical unit; at this time, if the logical unit crosses the three mapping tables corresponding to the logical address range of 3000-4000, the logical address range of 4000-5000, and the logical address range of 5000-6000, we can directly reset these three mapping tables, thereby avoiding the step of traversing the mapping tables.

[0056] In step S42, if multiple trim commands correspond to the same map table, and when the logical addresses of multiple trim commands are connected, the logical unit satisfies the first preset condition.

[0057] For example: if the logical address in command 1 is 5600-6000, the logical address in command 2 is 100-1599, the logical address in command 3 is 3000-5000, the logical address in command 4 is 1600-2999, and the logical address in command 5 is 5001-5599; after these five commands are recorded in memory for caching, they are arranged as command 2 (100-1599), command 4 (1600-2999), command 3 (3000-5000), command 5 (5001-5599), and command 1 (5600-6000). Since the logical addresses in the arranged commands are consecutive, the first preset condition is met, and therefore, erasure can be performed directly. Of course, if the condition of crossing map tables is met, the map tables crossed can also be reset.

[0058] Alternatively, in step S42, if the number of received trim commands reaches a certain requirement, i.e., the first preset condition is a preset number of trim commands, then even if the logical addresses in the arranged commands are not consecutive, as long as the size sorting is satisfied, the preset condition is still met, and the erase can be performed according to the arrangement order of the map table, thus saving the process of searching back for the map.

[0059] Alternatively, in step S42, if the accumulated logical addresses in the received trim command reach a certain level, that is, the preset number of accumulated logical addresses also meet the preset conditions, then they are arranged in ascending order and erased.

[0060] Of course, other arrangements can be used for the Trim parameter temporarily stored in the register, as long as they can save extra map reading and traversal, reduce time consumption, and thus meet the protection scope of the embodiments of this application.

[0061] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0062] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A trim method for a flash memory device, characterized in that, Including the following steps: Receive the current trim command issued by the host; The system checks whether the trim command erases all logical addresses on the disk; if so, it directly resets the mapping relationships of all map tables; if not, it proceeds to the next steps. Detect whether the trim command is an erase command that spans at least one map table; if so, directly reset the mapping relationship in the map tables it spans, and then erase the mapping relationship corresponding to the remaining logical address in the trim command. Specifically, align the start end of the logical address in the trim command with the data in the first map table, and align the end end of the logical address in the trim command with the data in the second map table. And directly reset the mapping relationship in the map tables between the first map and the second map table. Then, traverse the first map table to erase the start end of the logical address corresponding to the trim command, and traverse the second map table to erase the end end of the logical address corresponding to the trim command; otherwise, proceed to the next step. The system counts multiple trim commands and sorts the logical addresses of these commands to form logical units; specifically, it temporarily stores the received trim commands in a register. And the logical addresses in the trim commands are arranged sequentially according to the size relationship of the logical addresses, so that the arranged logical addresses form a logical unit; as well as When the logic unit meets the first preset condition, the mapping relationship in the map table corresponding to the logic unit is erased. The first preset condition is a preset number of trim commands, or a preset number of accumulated logical addresses.

2. The TRIM method for a flash memory device as described in claim 1, characterized in that, After resetting the mapping relationship in the map tables between the first map and the second map tables, the start end and the end end of the logical address in the trim command are counted in the logical unit.

3. The TRIM method for a flash memory device as described in claim 1, characterized in that, The various trim commands correspond to different map tables; When multiple map tables corresponding to the trim commands are arranged adjacently in sequence, the logic unit satisfies the first preset condition.

4. The trim method for a flash memory device as described in claim 3, characterized in that, When the logical address in the logical unit spans the entire map table, the mapping relationship in the map table being spanned is directly reset.

5. The trim method for a flash memory device as described in claim 1, characterized in that, Multiple trim commands correspond to the same map table; When the logical addresses of multiple trim commands are connected, the logical unit satisfies the first preset condition.

6. The trim method for a flash memory device as described in claim 1, characterized in that, In the step of counting multiple trim commands and sorting the logical addresses of the multiple trim commands to form a logical unit, if the data read by the host is the data corresponding to the trim command being counted, then empty data is responded according to the bus protocol.

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