Power-on timing control method and chip, device, medium and program

Abstract

Embodiments of the application disclose a power-on timing control method and chip, device, medium and program. The chip comprises a digital circuit, an analog circuit and a storage controller. After the digital circuit is in a preset voltage interval, the analog circuit sends a power-on reset (POR) signal, and the POR signal is used to indicate that the chip is powered on and started. The storage controller loads target data of a storage medium and an expected value of a cyclic redundancy check (CRC), and the CRC is used to detect or check errors that may occur in data transmission. The storage controller calculates a check value CRC-16 according to the target data, and the CRC-16 is one of the CRC industry standards.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a method, chip, device, medium, and program for power-on timing control. Background Technology

[0002] The chip's storage medium is crucial for secure boot during the data writing process. Incorrect or failed writing will prevent the phone from booting up, so this process requires more stringent requirements.

[0003] Chips have very strict power-on requirements; various essential power-on conditions must be met in a specific order before proceeding to the next step. If any part of the process fails, the entire power-on process cannot continue. In practical applications, chips typically load data directly using the chip's default clock sequence during power-on. This method has poor anti-interference capabilities, and if voltage or clock jitter during loading causes timing or data transmission errors, the chip will malfunction. Summary of the Invention

[0004] This application provides a method and related apparatus for power-on timing control, which aims to prevent the system from failing to boot due to incorrect loading of the trim value and affecting the user experience by using three CRC checks and trim value protection, in environments with large temperature differences or harsh electromagnetic environments.

[0005] In a first aspect, embodiments of this application provide a method for power-on timing control, characterized in that it is applied to a chip, the chip comprising a digital circuit module, an analog circuit module, and a memory control module, the method comprising:

[0006] After the digital circuit module is in a preset voltage range, the analog circuit module sends a power-on reset (POR) signal, which is used to indicate that the chip is powered on and started.

[0007] The storage control module loads the target data of the storage medium and the expected value of the Cyclic Redundancy Check (CRC). The CRC is used to detect or verify errors that may occur during data transmission.

[0008] The storage control module calculates a CRC-16 checksum based on the target data, where CRC-16 is one of the CRC industry standards.

[0009] If the CRC-16 value matches the expected CRC value, the storage control module determines that the target data verification was successful.

[0010] The storage control module updates the trim value of the interface between the digital circuit module and the analog circuit module. The trim value refers to the parameter that adjusts the behavior of the chip by writing parameter data to the chip.

[0011] After the digital circuit module has loaded the parameter trim value, the digital circuit module sends a system reset signal, which is used to indicate that the power-on is complete.

[0012] Secondly, embodiments of this application provide a power-on timing control device, characterized in that it includes:

[0013] The signal transmitting unit is configured to, after the analog circuit module is in a preset voltage range when the digital circuit module is in a preset voltage range, send a power-on reset (POR) signal to the analog circuit module, and send a system reset signal to the digital circuit module after the digital circuit module has loaded the parameter trim value. The POR signal is used to indicate that the chip is powered on and started, and the system reset signal is used to indicate that the power-on is complete.

[0014] A storage control unit is used to load the target data of the storage medium and the expected value of the Cyclic Redundancy Check (CRC), which is used to detect or verify errors that may occur during data transmission.

[0015] The detection unit is used to calculate a CRC-16 check value based on the target data. The CRC-16 is one of the CRC industry standards. If the CRC-16 matches the expected CRC value, the verification is successful.

[0016] A parameter update unit is used to update the trim value of the interface between digital circuits and analog circuits.

[0017] Thirdly, embodiments of this application provide a chip device, characterized in that it includes:

[0018] The digital circuit module is used to load the parameter trim value and release the system reset after the parameter trim value is loaded.

[0019] An analog circuit module, after the digital circuit module is in a preset voltage range, the analog circuit module sends a power-on reset (POR) signal, which is used to indicate that the chip is powered on and started.

[0020] The storage control module loads the target data and the expected value of the Cyclic Redundancy Check (CRC) from the storage medium, and calculates the check value CRC-16 based on the target data. If the CRC-16 matches the expected CRC value, the storage control module determines that the target data has been successfully checked. The update unit updates the trim value of the interface between the digital circuit and the analog circuit. The Cyclic Redundancy Check (CRC) is used to detect or check for errors that may occur during data transmission. The CRC-16 is one of the CRC industry standards. The trim value refers to the parameter that adjusts the behavior of the chip by writing parameter data to the chip.

[0021] The device performs some or all of the steps described in any of the methods of the first aspect of the embodiments of this application.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange. The computer program includes execution instructions for performing some or all of the steps described in any method of the first aspect of this application.

[0023] Fifthly, embodiments of this application provide a computer program product, wherein the computer program product includes a computer program operable to cause a computer to perform some or all of the steps described in any method of the first aspect of this application. The computer program product may be a software installation package.

[0024] As can be seen, this application embodiment provides a power-on timing control method for a chip, wherein the chip includes a digital circuit module and an analog circuit module; after the power required by the digital circuit module stabilizes, the analog circuit module releases the power-on reset (POR); the chip's storage control module loads the target data and the expected value of the cyclic redundancy check (CRC) on the storage medium; the storage control module calculates the check value CRC-16 based on the target data; if CRC-16 matches the expected CRC value, the target data verification is successful; the parameter trim value of the interface between the digital circuit module and the analog circuit module is updated; the digital circuit module loads the parameter trim value; after the parameter trim value is loaded, the digital circuit module releases the system reset; this application embodiment, through three CRC checks and trim value protection, can achieve power-on in environments with large temperature differences or harsh electromagnetic environments, preventing the system from incorrectly loading the trim value and causing power-on failure, thus affecting the user experience. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart illustrating a power-on timing control method provided in an embodiment of this application;

[0027] Figure 2 This is a chip power-on timing diagram provided in an embodiment of this application;

[0028] Figure 3 This is a flowchart illustrating a CRC verification method provided in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the structure of a power-on timing control device provided in an embodiment of this application;

[0030] Figure 5 This is a schematic diagram of a chip device application scenario provided in an embodiment of this application. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0032] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps is not limited to the steps listed, but may optionally include steps not listed, or may optionally include other steps inherent to these processes, methods, products, or apparatuses.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] In the relevant design, the data is loaded directly using the chip's original set clock sequence during the chip power-on process. This method has poor anti-interference capability, and if voltage or clock jitter during the loading process causes loading timing or some data transmission errors, the chip will not work properly.

[0035] To address the aforementioned issues, this application provides a power-on timing control method for a chip, wherein the chip includes a digital circuit module and an analog circuit module. After the power supply required by the digital circuit module stabilizes, the analog circuit module releases the power-on reset (POR). The chip's storage control module loads the target data and the expected value of the cyclic redundancy check (CRC) from the storage medium. The storage control module calculates the check value CRC-16 based on the target data. If CRC-16 matches the expected CRC value, the target data verification is successful. The parameter trim value of the interface between the digital circuit module and the analog circuit module is updated. The digital circuit module loads the parameter trim value. After the parameter trim value is loaded, the digital circuit module releases the system reset. This application, through three CRC checks and trim value protection, can prevent the system from failing to boot due to incorrect trim value loading, thus avoiding impacting user experience, even in environments with large temperature differences or harsh electromagnetic environments.

[0036] To better understand the power-on timing control method and apparatus disclosed in the embodiments of the present invention, the embodiments of the present invention will be described in detail below.

[0037] The following is a description of the flowchart applicable to the embodiments of the present invention. Please refer to... Figure 1 , Figure 1 This application provides a method for power-on timing control, characterized in that it is applied to a chip, the chip including a digital circuit module, an analog circuit module, and a memory control module, such as... Figure 1 As shown, this power-on timing control method includes the following operation flow:

[0038] Step 101: After the digital circuit module is in a preset voltage range, the analog circuit module sends a power-on reset (POR) signal, which is used to indicate that the chip is powered on and started.

[0039] Specifically, the analog circuit module supplies power to the IO through IO_VCC, and PAD_SWIRE is pulled up by default to enable the external backlight.

[0040] Furthermore, the analog circuit will only release the power-on reset POR after the power supply required by the mobile phone chip, including VDD11_D, VDD11_M, VDD15, OSC, etc., has stabilized.

[0041] Step 102: The storage control module loads the target data of the storage medium and the expected value of the Cyclic Redundancy Check (CRC). The CRC is used to detect or verify errors that may occur during data transmission.

[0042] For example, the above-mentioned storage medium may be, but is not limited to, one-time programmable (OTP) memory, electric-fuse (eFuse) and other storage media, which cannot be changed or erased after data is burned into the storage medium by a program.

[0043] Furthermore, to ensure the accuracy of data writing, cyclic redundancy verification of data transmission is required.

[0044] Specifically, Cyclic Redundancy Check (CRC) is one of the most commonly used error-checking codes in data communication. To maximize the accuracy of data received by the receiver, error detection is performed on the data before it is received. The receiver only accepts the data if and only if the detection result is correct. There are various detection methods, such as parity check, Internet check, and CRC. Its principle is as follows: To avoid signal interference and to determine whether the data code read by the receiver is the same as the original data code from the sender, check data is added to the original data code from the sender. This check data is the CRC checksum.

[0045] Step 103: The storage control module calculates the check value CRC-16 based on the target data. The CRC-16 is one of the CRC industry standards.

[0046] For example, the process of verifying target check data is as follows: At the sending end, based on the k-bit binary code sequence to be transmitted, an r-bit binary check code is generated for verification according to a certain rule, which is the expected value of the Cyclic Redundancy Check (CRC). This check code is appended to the target data to form a new binary code containing a sequence number of k+r bits, and then the data is sent. At the receiving end, a verification is performed according to the verification rule between the target data and the expected value of the CRC. A CRC-16 check code is generated according to this rule, which is theoretically named the "generator polynomial". The expected value of the CRC and the CRC-16 check code are compared to determine whether an error has occurred during data transmission.

[0047] Specifically, in a possible CRC check application scenario, let the original information polynomial before encoding be P(x), and the highest power of P(x) plus 1 equals k; the generator polynomial be G(x), and the highest power of G(x) equals r; the CRC polynomial be R(x); and the encoded information polynomial with CRC be T(x).

[0048] Decoding method for receiver: Divide T(x) by G(x). If the remainder is 0, it means that no error occurred during transmission; otherwise, it means that there was an error in transmission.

[0049] For example, suppose the information code is 1100 and the generator polynomial is 1011, that is, P(x) = x 3 +x 2 G(x) = x 3 +x+1, the process of calculating CRC is as follows:

[0050]

[0051] That is, R(x) = x. Where the highest power of G(x) is r = 3, the CRC is 010.

[0052] Therefore:

[0053] T(x)=(x 6 +x 5 )+(x)=x 6 +x 5 +x

[0054] That is, 1100000 + 010 = 1100010

[0055] If the transmission is error-free, then the following calculations are performed:

[0056]

[0057] There were no remainders.

[0058] For example, common CRC checksum types use internationally accepted standards and are generally classified according to the order m of the polynomial, referring to CRC algorithms as CRC-m, such as CRC-8, CRC-16, CRC-32, CRC-64, etc. Different CRC-m algorithms have different checksum codes and corresponding polynomials. This scheme selects CRC-16, with a corresponding polynomial of x. 16 +x 12 +x 5 The binary code corresponding to +1 is 1010 00000000 0001. The specific CRC-16 calculation method is as follows:

[0059] 1. A 16-bit register is preset to hexadecimal FFFF, which is all 1s;

[0060] Specifically, the above register is referred to as the CRC register;

[0061] 2. XOR the first 8-bit binary data, i.e. the first byte of the communication information frame, with the lower 8 bits of the 16-bit CRC register, and put the result into the CRC register.

[0062] 3. Shift the contents of the CRC register one bit to the right, fill the most significant bit with 0, and check the shifted-out bits after the right shift;

[0063] 4. If the shifted-out bit is 0: Repeat step 3 (shift right by one bit again);

[0064] 5. If the shift-out bit is 1: the CRC register is XORed with polynomial A001 (1010 0000 0000 0001);

[0065] 6. Repeat steps 3 and 4 until the data is shifted right 8 times, thus processing all 8 bits of data;

[0066] 7. Repeat steps 2 to 5 to process the next byte of the communication information frame;

[0067] 8. After calculating all bytes of the communication information frame according to the above steps, swap the high and low bytes of the resulting 16-bit CRC register;

[0068] 9. The final CRC register content is the CRC checksum.

[0069] Step 104: If the CRC-16 value matches the expected CRC value, the storage control module determines that the target data verification is successful.

[0070] Step 105: The storage control module updates the trim value of the interface between the digital circuit module and the analog circuit module. The trim value refers to the parameter that adjusts the behavior of the chip by writing parameter data to the chip.

[0071] For example, if the results of the above CRC check process are consistent, it indicates that there are no hardware or software errors in the target area of ​​the current storage medium.

[0072] Furthermore, update the trim value of the interface parameter between the current digital circuit module and the analog circuit module.

[0073] In practical applications, the above method also includes: performing high-temperature testing on the storage medium and using CRC checksum to determine whether the target data in the storage medium has been lost after high-temperature baking. This includes: verifying the default trim value and the expected CRC value; if the checksum calculated from the trim value matches the expected CRC value, it indicates that the target data in the storage medium has not been lost after the baking test.

[0074] Specifically, the default trim value mentioned above refers to the parameter value for burning target data onto the storage medium under normal temperature conditions.

[0075] Similarly, the above methods also include verification tests under low-temperature conditions. The process is similar to the methods described above and will not be elaborated here.

[0076] Step 106: After the digital circuit module has loaded the parameter trim value, the digital circuit module sends a system reset signal, which is used to indicate that the power-on is complete.

[0077] For example, the above-mentioned parameter trim value is a behavior of adjusting certain parameters of the chip by writing data from the outside into the chip after the chip manufacturing is completed.

[0078] For example, the digital circuit first loads the trim value of the OTP, and only releases the system reset after the trim value has been loaded.

[0079] Specifically, the digital flowchart of the power-on timing in practical applications is as follows: Figure 2 As shown. Figure 2 The diagram shown is a power-on timing diagram for a chip.

[0080] Specifically, IOVCC is the power supply voltage of the external input power supply, VCC is the chip operating voltage, which is 3.3V, BL indicates that the chip's power supply voltage is 4.6V, and the reset signal is released after all digital circuit voltages are stable. The AP terminal _reset indicates that the system signal is reset after the chip is powered on.

[0081] As can be seen, in this embodiment, a power-on timing control method for a chip is provided, wherein the chip includes a digital circuit module and an analog circuit module; after the power required by the digital circuit module stabilizes, the analog circuit module releases the power-on reset (POR); the chip's storage control module loads the target data of the storage medium and the expected value of the cyclic redundancy check (CRC); the storage control module calculates the check value CRC-16 based on the target data; if CRC-16 matches the expected CRC value, the target data verification is successful; the parameter trim value of the interface between the digital circuit module and the analog circuit module is updated; the digital circuit module loads the parameter trim value; after the parameter trim value is loaded, the digital circuit module releases the system reset; this embodiment, through three CRC checks and trim value protection, can achieve power-on in environments with large temperature differences or harsh electromagnetic environments, preventing the system from incorrectly loading the trim value and causing power-on failure, thus affecting the user experience.

[0082] In one possible example, if the CRC-16 value is inconsistent with the expected CRC value, the target data verification fails; the storage control module reloads the target data in the storage medium for verification.

[0083] For example, if the CRC check is performed in step 102 above, If the result has a remainder, it indicates that the current data transmission is incorrect and the target data verification has failed.

[0084] The specific process is as follows: Figure 3 As shown, Figure 3 This is a flowchart illustrating a CRC verification method provided in an embodiment of this application:

[0085] Step 301: Read the expected CRC value and target data of the storage medium, and calculate CRC-16.

[0086] Step 302: Determine if the CRC check is correct: If the CRC check is correct, set the CRC status to the pass bit; load the trim value into the register.

[0087] Specifically, the CRC check calculation process described above is the same as the process described in steps 102 and 103 above, so it will not be repeated here.

[0088] Step 303: If the CRC check fails, determine whether the CRC process has been performed 3 times.

[0089] Step 304: If yes, set the CRC Fail status bit and end the current verification process; if no, return to step 301.

[0090] Furthermore, if the target data verification result fails when the CRC-16 calculation result is inconsistent with the expected CRC value, the trim value of the digital-analog interface will not be updated, and the default trim value will remain unchanged.

[0091] As can be seen, in this embodiment of the application, the CRC check result is used to determine whether to update the current trim value, which can ensure the security and stability of the data transmission process and prevent the mistransmission of data from overwriting the original data, thus causing abnormal chip startup.

[0092] In one possible example, after the storage control module reloads the target data of the storage medium for verification, the method further includes: if the verification still fails after three consecutive verification cycles, then the default parameter trim value is retained.

[0093] For example, in designing a method for automatic hardware CRC verification, if an electrostatic discharge (ESD) occurs during the loading of the trim value, causing an error in data loading, the CRC will show a target data verification failure.

[0094] Furthermore, the hardware will recalculate the CRC-16 checksum until three calculations fail to match the expected CRC value. Because ESD is a transient error, three CRC calculations are sufficient to ensure the correct loading of the trim value.

[0095] As can be seen from the embodiments of this application, by using three CRC checks and trim value protection, it is possible to enable the system to boot up in environments with large temperature differences or in the event of ESD, ensuring that the system does not fail to boot up due to incorrect loading of trim value, thus affecting the user experience.

[0096] In one possible example, the above method includes: the CRC check field is located at a specific location on the storage medium; the length of the check field can be flexibly configured.

[0097] For example, a characteristic of CRC checksums is that the lengths of the information field and the check field can be arbitrarily selected, enabling flexible configuration.

[0098] As can be seen, in this embodiment of the application, the selected CRC check can be arbitrarily selected in terms of the length of its information field and check field, thereby increasing the flexibility of the configuration.

[0099] In one possible example, before the storage control module loads the target data and the expected value of the cyclic redundancy check (CRC) of the storage medium, the method further includes: determining whether the storage medium is in an empty chip state; if so, retaining the default parameter trim value and setting the chip to an empty chip state; if not, determining whether the CRC has been performed 3 times; if so, retaining the default parameter trim value.

[0100] Specifically, during the initial power-on process of the electronic device, the chip reads the voltage field data from the storage medium and sends it to the external power manager. The power manager provides a standard voltage before the chip's initial power-on and adjusts the voltage after receiving the voltage field data from the storage medium. Therefore, before the chip powers on, the bootloader determines whether the storage medium is in a blank state, i.e., whether there is a voltage field value in the storage medium.

[0101] Furthermore, if the storage medium is not empty, the voltage field data in the storage medium is read. Then it is determined whether the current data has undergone three CRC check processes. If three CRC checks have been completed, the default parameter trim value will be retained; if the storage medium is not empty, it jumps to the initial status bit judgment until the read data is not empty.

[0102] Furthermore, after the power supply voltage adjustment is completed, the chip will perform a power-on reset operation.

[0103] As can be seen, in this embodiment of the application, by determining whether the current storage medium is an empty chip, it is further determined whether to perform CRC verification to ensure that after the current electronic device is powered on, the chip has read the target data and can correctly load the target data, thereby ensuring the normal power-on timing and normal data loading, so that the chip can work normally.

[0104] In one possible example, after the digital circuit module has finished loading the parameter trim value and before the digital circuit module releases the system reset, the method further includes: the digital circuit module issuing a power-on timing signal for the storage medium, the power-on timing signal being used to ensure the correctness of loading the parameter value trim; the power-on timing signal having 20% ​​redundancy added to the default timing signal; and the default slowest clock frequency used by the digital circuit module during the loading of the parameter trim value.

[0105] For example, when generating timing signals for the storage medium, the digital circuit module adds a 20% redundancy beyond meeting the timing requirements of the storage medium to ensure the correctness of the loaded parameter value trim. Simultaneously, the digital circuit module uses the slowest default clock frequency during the loading of the trim value.

[0106] For example, the chip is designed with the lowest possible OSC trim value and has 20% redundancy to ensure that trim value readings can function under the design process conditions.

[0107] As can be seen, in this embodiment, the 20% redundancy ensures that the trim value reading can work under the design process conditions. At the same time, the method of three CRC automatic verifications is adopted to ensure the normal power-on sequence and data loading. Furthermore, it can enable the system to start up in environments with large temperature differences or harsh electromagnetic environments without the system failing to load the trim value incorrectly, thus affecting the user experience.

[0108] In one possible example, after the analog circuit module issues a power-on reset (POR) signal after the digital circuit module is in a preset voltage range, the method further includes: the chip executing a startup program configured in the chip, the startup program being used to load system applications.

[0109] For example, after the chip powers on normally, a built-in bootloader is needed to load the electronic device's applications to enable normal user operation. The bootloader is a piece of program loading code embedded in storage media, connecting the underlying hardware and the application. Its main functions are to initialize the processor and peripheral circuits for normal operation, establish memory space mapping, bring the system's hardware and software environment to a suitable state, and load the system program from flash memory. The bootloader runs after each power-on reset.

[0110] As can be seen from the embodiments of this application, after the power-on is completed normally, the chip loads the boot program to complete the initialization work for the normal operation of the processor and peripheral circuits, establish the mapping of memory space, and bring the system's hardware and software environment to a suitable state, so that users can use electronic devices normally.

[0111] With the above Figure 1 The embodiments shown are consistent; please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of a power-on timing control device provided in an embodiment of this application, as shown below. Figure 4 As shown:

[0112] A power-on timing control device, the device comprising:

[0113] 401: Signal transmitting unit, wherein the signal transmitting unit is used to send a power-on reset (POR) signal after the analog circuit module is in a preset voltage range when the digital circuit module is in a preset voltage range, and to send a system reset signal after the digital circuit module has loaded the parameter trim value. The POR signal is used to indicate that the chip is powered on and started, and the system reset signal is used to indicate that the power-on is complete.

[0114] 402: Storage control unit, which is used to load target data and expected value of cyclic redundancy check (CRC) of storage medium, wherein the CRC is used to detect or verify errors that may occur during data transmission.

[0115] 403: Detection unit, the detection unit is used to calculate the check value CRC16 based on the target data, the CRC-16 is one of the CRC industry standards, and if the CRC-16 is consistent with the expected CRC value, the verification is successful.

[0116] 404: Parameter update unit, which is used to update the trim value of the interface between digital circuits and analog circuits.

[0117] 405: Digital circuit unit, which is used to load the parameter value trim, and release the system reset after the parameter trim value is loaded.

[0118] As can be seen, this application provides a power-on timing control method for a chip, wherein the chip includes a digital circuit module and an analog circuit module; after the power required by the digital circuit module stabilizes, the analog circuit module releases the power-on reset (POR); the chip's storage control unit loads the target data of the storage medium and the expected value of the cyclic redundancy check (CRC); the storage control module calculates the check value CRC-16 based on the target data; if CRC-16 matches the expected CRC value, the target data verification is successful; the parameter trim value of the interface between the digital circuit module and the analog circuit module is updated; the digital circuit module loads the parameter trim value; after the parameter trim value is loaded, the digital circuit module releases the system reset; this application embodiment, through three CRC checks and trim value protection, can achieve power-on in environments with large temperature differences or harsh electromagnetic environments, preventing the system from incorrectly loading the trim value and causing power-on failure, thus affecting the user experience.

[0119] Specifically, in this application embodiment, the power-on timing control device can be divided into functional units according to the above method example. For example, each function can be divided into its own functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division; in actual implementation, there may be other division methods.

[0120] With the above Figure 1 The embodiments shown are consistent; please refer to [link / reference]. Figure 5 , Figure 5 This is a schematic diagram of another chip device application scenario provided in the embodiments of this application, such as... Figure 5 As shown:

[0121] A chip device, characterized in that it comprises:

[0122] A digital circuit module is used to load the parameter trim value and release the system reset after the parameter trim value is loaded.

[0123] An analog circuit module, after the digital circuit module is in a preset voltage range, sends a power-on reset (POR) signal to indicate that the chip is powered on and started.

[0124] The storage control module loads the target data and the expected value of the Cyclic Redundancy Check (CRC) from the storage medium, and calculates the check value CRC-16 based on the target data. If the CRC-16 matches the expected CRC value, the storage control module determines that the target data has been successfully checked. The update unit updates the trim value of the interface between the digital circuit and the analog circuit. The Cyclic Redundancy Check (CRC) is used to detect or check for errors that may occur during data transmission. The CRC-16 is one of the CRC industry standards. The trim value refers to the parameter that adjusts the behavior of the chip by writing parameter data to the chip.

[0125] The device performs some or all of the steps described in any of the methods of the first aspect of the embodiments of this application.

[0126] In one possible embodiment, in practical application scenarios, the above-mentioned chip can also be used in mobile phone screen replacement scenarios.

[0127] For example, the chip described above can be mounted on a mobile phone screen. Through the functions achieved by the above steps, it can ensure that the mobile phone can power on normally and complete the boot process after the screen is replaced, and improve the stability of the mobile phone's power-on and the security of data loading after the screen is replaced.

[0128] The aforementioned chip device acts as a transcoding chip, receiving MIPI video data sent by the AP and responding to the AP's commands. After processing by reducing the frame rate and resolution, the data is converted into HD@60Hz high-definition video adapted for Touch and Display Driver Integration (TDDI) displays, and then the video is sent to the screen via MIPI.

[0129] Furthermore, the aforementioned chip device also supports the conversion of touch feedback protocols and screen backlight adjustment protocols. Touch data fed back from Touch and Display Driver Integration (TDDI) and backlight adjustment data are converted by the chip into a format supported by the main chip. The aforementioned chip device performs protocol conversion; the specific TDDI display driver, touch calculation, and other functions are all completed using separate chips.

[0130] It should be noted that the specific application scenarios of the chip device in this embodiment include, but are not limited to, the mobile phone screen replacement application scenario mentioned above. Application methods in other scenarios will not be elaborated here.

[0131] This application provides a computer-readable storage medium storing a computer program for electronic data exchange. The computer program includes execution instructions for performing some or all of the steps of any of the power-on timing control methods described in the above-described power-on timing control method embodiments. The computer includes an electronic terminal device.

[0132] This application provides a computer program product, which includes a computer program operable to enable the computer to perform some or all of the steps of any power-on timing control method described in the above method embodiments. The computer program product may be a software installation package.

[0133] It should be noted that, for the sake of simplicity, each of the aforementioned embodiments of the power-on timing control method is described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0134] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principle and implementation of a power-on timing control method and related devices of this application. The description of the above embodiments is only for the purpose of helping to understand the method and its core ideas of this application. At the same time, for those skilled in the art, based on the ideas of a power-on timing control method and related devices of this application, there will be changes in the specific implementation and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

[0135] This application is described with reference to flowchart illustrations and / or block diagrams of methods, hardware products, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0136] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. Memory may include: flash drives, read-only memory (ROM), random access memory (RAM), hard disks or optical disks, etc.

[0137] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0138] Those skilled in the art will understand that all or part of the steps in the various methods of any of the above-described power-on timing control method embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0139] It is understood that any product that is controlled or configured to execute the processing method of the flowchart described in the embodiment of the power-on timing control method of this application, such as the apparatus and computer program product of the above flowchart, falls within the scope of the related products described in this application.

[0140] Obviously, those skilled in the art can make various modifications and variations to the power-on timing control method and apparatus provided in this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A method of power-on timing control, the method comprising: Applied to a chip, said chip including digital circuits, analog circuits, and a memory controller, the method includes: After the digital circuit is in a preset voltage range, the analog circuit sends a power-on reset (POR) signal, which is used to indicate that the chip is powered on and started. The storage controller loads the target data and the expected value of the Cyclic Redundancy Check (CRC) onto the storage medium. The CRC is used to detect or verify errors that may occur during data transmission. The storage medium includes: a One-Time Programmable Memory (OTP) or an Electronic Fuse (eFuse). The storage controller calculates a CRC-16 checksum based on the target data, where CRC-16 is one of the CRC industry standards. If the CRC-16 value matches the expected CRC value, the storage controller determines that the target data verification was successful. The storage controller updates the trim value of the interface between the digital circuit and the analog circuit. The trim value refers to the parameter that adjusts the behavior of the chip by writing parameter data to the chip. After the digital circuit has loaded the parameter trim value, the digital circuit sends a system reset signal, which is used to indicate that the power-on is complete.

2. The method of claim 1, wherein, include: If the CRC-16 value is inconsistent with the expected CRC value, the storage controller determines that the target data verification has failed. The storage controller reloads the target data on the storage medium for verification.

3. The method of claim 2, wherein, After the storage controller reloads the target data of the storage medium for verification, the method further includes: if the verification still fails after three cyclic verifications, the storage controller retains the default parameter trim value.

4. The method according to any one of claims 1 to 3, characterized in that, include: The CRC check field is located in a specific location on the storage medium; The length of the verification field can be flexibly configured.

5. The method according to any one of claims 1 to 3, characterized in that, Before the storage controller loads the target data and the expected value of the Cyclic Redundancy Check (CRC) from the storage medium, the method further includes: Determine whether the storage medium is in an empty state. If so, retain the default trim value and set the chip to empty state; If not, determine whether the cyclic redundancy check (CRC) has been performed three times. If so, the default trim value will be retained.

6. The method according to any one of claims 1 to 3, characterized in that, The method further includes the following steps: after the digital circuit has loaded the trim value and before the digital circuit releases the system reset: The digital circuit sends a power-on timing signal to the storage medium, which is used to ensure the correctness of loading the trim value. The power-on timing signal has 20% more redundancy than the default timing signal; The digital circuit uses the slowest default clock frequency during the process of loading the trim value of the parameter.

7. The method according to any one of claims 1-3, characterized in that, After the analog circuit is in a preset voltage range and the digital circuit issues a power-on reset (POR) signal, the method further includes: The chip executes a boot program, which is configured in the chip and is used to load system applications.

8. A power-on timing control device, characterized in that, The device is applied to a chip, the chip including digital circuits, analog circuits, and a memory controller; the device includes: A signal transmitting unit is configured to, after the analog circuit is in a preset voltage range in the digital circuit, issue a power-on reset (POR) signal to the analog circuit, and issue a system reset signal to the digital circuit after the digital circuit has loaded the parameter trim value. The POR signal is used to indicate that the chip is powered on and started, and the system reset signal is used to indicate that the power-on is complete. A storage control unit is used to load target data and the expected value of Cyclic Redundancy Check (CRC) onto a storage medium, wherein the CRC is used to detect or verify errors that may occur during data transmission; the storage medium includes: a One-Time Programmable Memory (OTP) or an Electronic Fuse (eFuse); The detection unit is used to calculate a CRC-16 check value based on the target data. The CRC-16 is one of the CRC industry standards. If the CRC-16 matches the expected CRC value, the verification is successful. A parameter update unit is used to update the trim value of the interface between digital circuits and analog circuits.

9. A chip, characterized in that, include: The digital circuit is used to load the parameter trim value and release the system reset after the parameter trim value is loaded. An analog circuit, wherein after the digital circuit is in a preset voltage range, the analog circuit issues a power-on reset (POR) signal, which is used to indicate that the chip is powered on and started. A storage controller is used to load target data and the expected value of a Cyclic Redundancy Check (CRC) from the storage medium, and calculate a check value (CRC-16) based on the target data. If the CRC-16 matches the expected CRC value, the storage controller determines that the target data has been successfully checked. An update unit is used to update the trim value of the interface between the digital and analog circuits. The CRC is used to detect or verify errors that may occur during data transmission. The CRC-16 is one of the CRC industry standards. The trim value refers to a parameter that adjusts the behavior of the chip by writing parameter data to the chip. The storage medium includes: a One-Time Programmable Memory (OTP) or an Electronic Fuse (eFuse). The chip performs the method as described in any one of claims 1-7.

10. A computer-readable storage medium or computer program, characterized in that, The computer program stored in the computer-readable storage medium causes a computer to perform the method as described in any one of claims 1-7, or the computer program causes a computer to perform the method as described in any one of claims 1-7.

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