Processing system, related integrated circuit and method

Abstract

Embodiments of the present disclosure relate to processing systems, related integrated circuits, and methods. A processing system includes configuration registers and a non-volatile memory having memory slots storing configuration data bits and error detection bits. A hardware configuration circuit sequentially reads data bits from the non-volatile memory for storage in corresponding configuration registers by: receiving bits from a current memory slot; selectively asserting an error signal in response to a comparison of a received error detection bit and a computed error detection bit; storing the received bits to a temporary register in which the error signal is de-asserted and in which another error signal is asserted, else asserting the error signal. Otherwise, predetermined configuration data is stored to the temporary register. The contents of the temporary register are then sequentially stored to the configuration registers. A reset signal is generated in response to the another error signal to reset the configuration registers.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Italian Patent Application No. 102022000002093, filed on February 7, 2022, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] Embodiments of this disclosure relate to solutions for managing configuration data within a processing system, for example, in the form of an integrated circuit. Background Technology

[0004] In many processing systems, the behavior of the processing system, especially the behavior of one or more of its sub-circuits, can vary based on configuration data.

[0005] For example, Figure 1 This paper demonstrates possible solutions for reading this configuration data CD from non-volatile memory 12 (e.g., electrically erasable programmable read-only memory (EEPROM) or one-time programmable (OTP) memory) and storing the configuration data CD into multiple registers 112 of processing system 10 (e.g., implemented in integrated circuit 30).

[0006] Specifically, in the considered embodiment, the processing system 10 includes hardware configuration circuitry 108 configured to read configuration data CD from non-volatile memory 12. For example, for this purpose, hardware configuration circuitry 108 may include data read circuitry 1080 configured to sequentially read a given number of bits from non-volatile memory 12 of configuration data CD and generate a signal DATA containing the given number of bits read from memory 12.

[0007] In the considered example, the hardware configuration circuit 108 also includes control circuitry 1082, implemented, for example, via a finite state machine (FSM), configured to control the operation of the hardware configuration circuitry 108. Essentially, control circuitry 1082 implements state control circuitry that manages the operation of the hardware configuration circuitry 108 and scheduling circuitry configured to forward configuration data CD to register 112.

[0008] For example, in the considered instance, processing system 10 includes a reset circuit 116 configured to generate a reset signal RST in response to a given event (e.g., power-on of processing system 10). Therefore, in response to the reset signal RST, control circuit 1082 may generate one or more control signals CTRL to instruct data read circuit 1080 to sequentially read configuration data CD from non-volatile memory 12.

[0009] For example, to allocate configuration data CD to register 112, such as a given number N of registers REG1, ..., REGN, each register REG1, ..., REGN may have an associated corresponding address, and control circuitry 1082 may generate an addressing signal ADR to indicate which register the bits of signal DATA should be stored in. For example, for this purpose, processing system 10 may include address decoder 124 configured to store signal DATA into one of registers REG1, ..., REGN according to addressing signal ADR.

[0010] For example, Figure 1 The address decoder 124 is implemented using a demultiplexer, which is configured to selectively forward the signal DATA to one of registers REG1, ..., REGN according to the addressing signal ADR.

[0011] On the contrary, Figure 2 In this configuration, register 112 is connected to signal DATA via a bus, where signal DATA is provided in parallel to all registers 112, and each register is configured to store a bit of signal DATA when the corresponding write enable signal WEN1, ..., WENN is asserted. Therefore, in this configuration, address decoder 124 can be configured to assert one of the write enable signals WEN1, ..., WENN according to addressing signal ADR. In this configuration, control circuit 1082 preferably also generates a general write enable signal WEN, where address decoder 124 is configured to assert one of the write enable signals WEN1, ..., WENN according to addressing signal ADR only when write enable signal WEN is asserted by control circuit 1082.

[0012] For example, such a solution is disclosed in U.S. Patent Application Publication No. 2020 / 0169459, which is incorporated herein by reference. For example, in this document, the configuration data CD is stored in the form of a configuration data frame, also identified as a Device Configuration Format (DCF), where a first subset of bits indicates the address of register 112, for example, as part of a more complex configuration data client, while a second subset of bits indicates the configuration data CD to be stored in the corresponding register 112. Thus, in this manner, control circuitry 1082 can generate an addressing signal ADR based on the address included in the configuration data frame, thereby transferring the configuration data CD included in the configuration data frame to the respective registers 112. Typically, register 112 is reset in response to a reset signal RST before the configuration data CD is transferred to register 112.

[0013] Therefore, one or more circuits 110 of the processing system 10 can use configuration data CD stored in register 112. For example, such configuration data CD is typically calibration data used to ensure consistent hardware behavior, thereby compensating for possible manufacturing process tolerances. This is often used, for example, for the calibration of analog components of the processing system, such as temperature sensors, analog-to-digital converters, voltage references, etc. For example, the voltage monitor threshold level of an analog comparator can be “fine-tuned” to a precise expected value by adjusting some levels with configuration / calibration data written by the hardware manufacturer of the processing system. Additionally or optionally, the configuration data CD can be used to selectively configure, for example, activate or deactivate a given function of the processing system 10.

[0014] For example, Figure 3 A block diagram of an exemplary processing system 10, such as a microcontroller, is shown.

[0015] In the considered example, processing system 10 includes a microprocessor (MP) 102 programmed via software instructions, typically a central processing unit (CPU). The software executed by the microprocessor 102 is typically stored in non-volatile program memory (M) 104, such as flash memory or EEPROM. Therefore, memory 104 is configured to store the firmware of processing unit 102, which includes software instructions to be executed by microprocessor 102. Typically, non-volatile memory 104 may also correspond to memory 12 and may also be used to store configuration data CD. Microprocessor 102 is also typically associated with volatile memory (VM) 104b, such as random access memory (RAM). For example, memory 104b may be used to store temporary data. Figure 3 As shown, communication with the memories 104 and / or 104b is typically performed via one or more memory controllers (MCs) 100. The memory controllers 100 may be integrated into the microprocessor 102 or connected to the microprocessor 102 via a communication channel (e.g., the system bus of the processing system 10). Similarly, the memories 104 and / or 104b may be integrated with the microprocessor 102 in a single integrated circuit, or the memories 104 and / or 104b may be in the form of separate integrated circuits and connected to the microprocessor 102, for example, via traces on a printed circuit board.

[0016] In addition to or as a replacement for microprocessor 102, processing system 10 may include one or more (hardware) resources / peripherals 106, selected, for example, from the group consisting of:

[0017] - One or more communication interfaces IF, such as those used for exchanging data via communication system 20, such as Universal Asynchronous Receiver / Transmitter (UART), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (ICI) 2C), Controller Area Network (CAN) bus and / or Ethernet interface; and / or

[0018] - One or more analog-to-digital converters (AD) and / or digital-to-analog converters (DA); and / or

[0019] - One or more dedicated digital components (DCs), such as hardware timers and / or counters, or cryptographic coprocessors; and / or

[0020] - One or more analog components AC, such as comparators, sensors, such as temperature sensors, etc.; and / or

[0021] - One or more mixed signal component MSCs, such as PWM (Pulse Width Modulation) drivers.

[0022] Typically, the dedicated digital component DC can also correspond to a field-programmable gate array (FPGA) integrated in the processing system 10. For example, in this case, the memory 104 may also include program data for such an FPGA.

[0023] For example, in the case of a microcontroller, resource / peripheral device 106 is connected to microprocessor 102 via a suitable communication system such as one or more system buses.

[0024] For example, in such a processing system 10, configuration data CD stored in register 112 can be used to influence the behavior of one or more resource / peripheral devices 106 and / or microprocessor 102 and / or memory controller 100. For example, configuration data CD may include calibration data for one or more sensors, configuration data indicating PWM signal timing, security configuration data indicating whether access to a given memory region is prohibited, etc.

[0025] In this regard, U.S. Patent Application Publication No. 2020 / 0169459 also discloses the possibility of: corresponding error detection and / or correction data ECC associated with each configuration data frame; and / or including one or more error detection data, such as parity bits, in the configuration data CD itself, whereby the configuration data client 112 may include error detection circuitry configured to verify bits stored in the corresponding registers of the configuration data client 112.

[0026] In addition, U.S. Patent Application Publication No. US2019 / 0258493A1 discloses that signature data such as hash codes can be stored in non-volatile memory 12 for all configuration data CDs, the contents of which are incorporated herein by reference.

[0027] Therefore, although the literature cited above discloses solutions for verifying the correctness of configuration data CD at different levels, these solutions are complex and may not always be suitable for certain applications, such as in the case of a low-complexity and low-cost processing system 10.

[0028] There is a need in this field for solutions that reduce complexity in managing the distribution of configuration data within a system. Summary of the Invention

[0029] One or more embodiments relate to processing systems. Embodiments also relate to related integrated circuits, devices, and methods.

[0030] As described above, various embodiments of this disclosure relate to solutions for managing the distribution of configuration data, such as in a processing system integrated into an integrated circuit. Specifically, in various embodiments, the processing system includes a serial non-volatile memory comprising a given number K memory slots, each memory slot having a given number L bits, wherein the L bits of the memory slot include a first number of configuration data and a second number of error detection bits, the second number of error detection bits being calculated based on the corresponding first number of configuration data.

[0031] In various embodiments, the processing system includes a given number of N configuration registers and one or more circuits configured to change operation based on bit values ​​stored in the configuration registers. Specifically, each configuration register has an associated given uniform address and P bits, wherein each configuration register is configured to reset its contents to a corresponding reset value in response to a reset signal generated by reset circuitry (e.g., in response to power-on of the processing system). Thus, a given number of L bits of memory slots corresponds to a given multiple Q of a given number of P bits of configuration registers, where Q = L / P and N = Q × K, wherein Q configuration registers are associated with each memory slot.

[0032] In various embodiments, the processing system further includes hardware configuration circuitry comprising a given number of Q temporary registers, each having P bits. Specifically, the hardware configuration circuitry is configured to sequentially read data from the non-volatile memory and store the read data into the corresponding configuration register in response to the reset signal and / or one or more other trigger signals of signaling events. For this purpose, the hardware configuration circuitry performs a repetitive operation sequence for each of the K memory slots of the non-volatile memory.

[0033] Specifically, in various embodiments, the hardware configuration circuitry determines the index of the current memory slot of the non-volatile memory and receives the corresponding L bits of the current memory slot from the non-volatile memory via serial communication. For example, for this purpose, the hardware configuration circuitry may include a data read circuitry comprising a receive register having L bits and a serial communication interface configured to receive the L bits of the current memory slot from the non-volatile memory via serial communication and to assert a control signal after the corresponding L bits have been received. For example, the serial communication interface may be configured to receive the L bits of the current memory slot by transmitting a read request to the non-volatile memory, the read request containing data identifying the index of the current memory slot of the non-volatile memory. In various embodiments, the serial communication interface also generates a signal indicating the index of the current memory slot of the non-volatile memory.

[0034] Once the corresponding L bits of the current memory slot are received, the hardware configuration circuitry, for example, uses an error detection circuitry to calculate another error detection bit based on the received configuration data, and selectively asserts an error signal by comparing the received error detection bit with the calculated error detection bit.

[0035] In various embodiments, the hardware configuration circuitry is configured to verify whether an error signal has been asserted, and in response to determining that an error signal has been asserted, assert another error signal. Thus, the other error signal indicates whether data from at least one memory slot that has been read includes an error. Specifically, in various embodiments, the hardware configuration circuitry is configured to verify whether the other error signal has been asserted, and when the other error signal is deasserted, store the received L bits in a temporary register. Conversely, when the other error signal is asserted, the hardware configuration circuitry stores predetermined configuration data in the temporary register. For example, for this purpose, the hardware configuration circuitry may include control circuitry that includes selection circuitry configured to provide the received L bits or predetermined configuration data to the temporary register according to the other error signal. For example, the temporary register may be configured to store data provided by the selection circuitry in response to a control signal generated by a serial communication interface.

[0036] In various embodiments, the hardware configuration circuit then sequentially stores the contents of each of the Q temporary registers into the respective Q configuration registers by providing the contents of one of the temporary registers and generating an addressing signal with an address associated with the respective configuration register via a counter. For example, for this purpose, the hardware configuration circuit may include sequential logic circuitry implementing a state machine, wherein the state machine is configured to sequentially increment a count value for Q consecutive clock cycles in response to a control signal generated by a serial communication interface, wherein the addressing signal corresponds to the count value, or is determined by combining bits of the count value with bits of a signal indicating the index of the current memory slot.

[0037] Therefore, in various embodiments, in the event of an error in the configuration data for a given memory slot, the hardware configuration circuitry provides predetermined configuration data for that memory slot and all subsequent memory slots to the configuration register. Thus, in various embodiments, the hardware configuration circuitry can be configured to: once data for K memory slots has been received, check whether another error signal has been asserted, and generate another reset signal for resetting at least a portion of the contents of the configuration register, thereby also resetting the configuration register that has been programmed with the configuration data. For example, for this purpose, the state machine can be configured to, for instance, determine whether all memory slots have been transferred to the configuration register based on a count value and a signal optionally indicating the index of the current memory slot of the non-volatile memory. Next, in response to determining that all memory slots have been transferred to the configuration register, the state machine can assert another reset signal based on another error signal.

[0038] In various embodiments, hardware configuration circuitry (e.g., selection circuitry) is configured to store the received L bits of error detection bits, along with predetermined configuration data, into a temporary register in response to determining that another error signal has been asserted. This stores the error detection bits received for K memory slots into predetermined positions in the configuration register. Therefore, to prevent these error detection bits from being reset by another reset signal, the configuration register can be configured to reset its contents in response to a reset signal, and to reset the contents of configuration registers other than the predetermined positions in response to another reset signal. For example, in this manner, the error detection bits can still be read. For this purpose, for instance, the processing system may include a communication interface, such as a debug interface, configured to transmit the contents of one or more configuration registers in the configuration register to an external device.

[0039] Alternatively, the hardware configuration circuitry (e.g., data read circuitry) can be configured to store the received L bits of error detection bits into another register, which is configured to be reset in response to a first reset signal and retain its contents when a second reset signal is asserted. In this case, the bits of the configuration register used to provide the error detection bits can be implemented using a shadow register connected to the other register used to store the error detection bits. Attached Figure Description

[0040] Embodiments of this disclosure will now be described with reference to the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0041] Figure 1 A first example of a processing system configured to read configuration data from non-volatile memory is shown;

[0042] Figure 2 A second example of a processing system configured to read configuration data from non-volatile memory is shown;

[0043] Figure 3 An example of a processing system, such as a microcontroller, is shown;

[0044] Figure 4 An embodiment of a processing system including hardware configuration circuitry is shown, the hardware configuration circuitry being configured to read configuration data from non-volatile memory and store the configuration data in a register;

[0045] Figure 5 It shows Figure 4 An embodiment of non-volatile memory, wherein the non-volatile memory stores configuration data and error detection data;

[0046] Figure 6 It shows Figure 4 An embodiment of the data reading circuit of the hardware configuration circuit;

[0047] Figure 7 It shows Figure 4 An example of the control circuit of the hardware configuration circuit;

[0048] Figure 8 and 9 It shows Figure 7 Examples of various sub-circuits of the control circuit;

[0049] Figure 10 It shows a method suitable for reading from the storage Figure 4 An embodiment of a processing system for processing configuration data in the registers of a processing system;

[0050] Figure 11 and Figure 12 It shows Figure 4 Another embodiment of the registers of the processing system; and

[0051] Figure 13 and Figure 14 It shows Figure 7 An example of the operation of the control circuit. Detailed Implementation

[0052] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of these specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0053] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] The headings provided in this document are for convenience only and do not explain the scope or meaning of the embodiments.

[0055] In the following Figures 4 to 14 In the middle, it will be noted that it has already been referred to Figure 1 and 3 The parts, elements, or components described are indicated by the same reference numerals used previously in these figures; in order not to overburden the detailed description of the invention, the description of these previously described elements will not be repeated below.

[0056] As described above, various embodiments of this disclosure relate to solutions for managing the distribution of configuration data within a processing system.

[0057] Figure 4 An embodiment of the processing system 10a according to the present invention is shown. Specifically, the general architecture of the processing system 10a corresponds to the reference... Figures 1 to 3 The architecture is described, and the corresponding description applies as a whole.

[0058] Specifically, in the same case, the integrated circuit 30a of the processing system 10a includes: a reset circuit 116 configured to generate a reset signal RST in response to power-on of the processing system 10a; and a plurality of registers 112, such as N registers REG1, ..., REGN, wherein each register 112 is configured to reset its contents to a corresponding reset value in response to the reset signal RST. Therefore, one or more circuits 110 of the processing system 10a (e.g., peripheral devices / resources 106 and / or microprocessor 102 and / or memory controller 100) can be configured to change their operation based on configuration data stored in the registers 112. Typically, as Figure 4 As schematically shown, the reset signal RST can also be used to reset register 112 and / or one or more circuits 110.

[0059] Therefore, in the same case, the hardware configuration circuit 108a is configured to read configuration data CD from the non-volatile memory 12a in response to the reset signal RST, and store the configuration data CD read from the non-volatile memory 12a into the register 112, thereby rewriting the reset value. As previously described, in order to store the configuration data read from the non-volatile memory 12a into the register 112, the hardware configuration circuit 108a may generate an addressing signal ADR and an optional write enable signal WEN, and the processing system 10a may include an address decoder 124. Typically, the address decoder 124 may also be integrated into the hardware configuration circuit 108a. Furthermore, the non-volatile memory 12a may be external or internal relative to the integrated circuit 30a.

[0060] and Figure 1 and Figure 2 In contrast, the non-volatile memory 12a not only stores the configuration data CD of the register 112, but also stores additional error detection data PD, such as one or more parity bits.

[0061] For example, Figure 5 An embodiment of a non-volatile memory 12a including a memory region 120 and a memory interface circuit 122 is shown.

[0062] For example, memory region 120 can be organized into a given number of K memory slots, where each memory slot has a given number of L bits, also referred to below as memory word size or page size. For example, memory 12a may have a memory word size of 32, 64, or 128 bits. For example, in various embodiments, memory region 120 has K = 4 memory slots, where L = 128 bits.

[0063] In the considered embodiment, the memory interface (IF) circuit 122 is therefore configured to read L bits of a memory slot and provide the read data having L bits to the processing system 10a, particularly the data read circuit 1080a, via the communication channel SER. Specifically, in various embodiments, the communication channel SER is a serial communication channel, wherein the memory interface circuit 122 sequentially transmits L bits of a given slot. Therefore, the memory interface circuit 122 may include a serial interface, such as an asynchronous serial interface, like a UART, wherein the memory interface circuit 122 generates a serial transmission signal in response to an internal clock signal; or preferably a synchronous serial interface, such as an I... 2 The interface is either C or SPI, wherein the memory interface circuit 122 generates a serial transmission signal in response to a clock signal provided via a dedicated clock line.

[0064] Typically, such serial non-volatile memories are well known in the art. For example, in this context, reference may be made to serial EEPROMs such as the M95010, M95020, or M95040 series manufactured by STMicroelectronics, which have SPI or I... 2 C communication interface.

[0065] like Figure 5 As shown, in various embodiments, each memory slot stores a given number of M bits of error detection data PD, for example, error detection data PD1, ..., PD4 for K=4 memory slots, and the remaining (L-M) bits of the slot are used to store configuration data, for example, configuration data CD1, ..., CD4 for K=4 memory slots.

[0066] Typically, the error detection data PD for a given slot can be calculated using any suitable error detection code scheme and may include, for example, one or more parity bits. For instance, in various embodiments, the number of bits L of the memory slot is divided into M substrings, each substring having L / M bits (e.g., 16 bits in the case of L=128 and M=8). In this case, each substring of L / M bits may include a single parity bit calculated for the other (L / M-1) bits of the configuration data.

[0067] Generally, the L bits of the error detection data PD can be interleaved with the (M-L) bits of the configuration data for a given memory slot, or as follows: Figure 5 As shown, configuration data and error detection data can be arranged in separate consecutive bit sequences.

[0068] in this regard, Figure 6 An embodiment of the data reading circuit 1080a of the hardware configuration circuit 108a is shown.

[0069] As previously described, the data read circuit 1080a of the hardware configuration circuit 108a can be configured to sequentially read bits from each of the K memory slots. Typically, without loss of generality, based on the number of registers 112, the data read circuit 1080a may also read only a subset of the actual number of memory slots in the memory 12a. Therefore, the number K should be interpreted as the number of memory slots actually transferred from the memory 12a to the registers 112.

[0070] Specifically, in various embodiments, the data read circuit 1080a includes a receive register (RR) 1081 with L bits and a communication interface (IF) 1083, the communication interface (IF) 1083 being configured to receive L bits of a given memory slot and store the received bits into the receive register 1081.

[0071] As described above, the memory interface circuit 122 can actually be configured to transmit L bits of a given memory slot via a serial communication protocol. Therefore, the communication interface 1083 can be a serial communication interface, such as a UART, I... 2 C or SPI interface. In this regard, any suitable communication protocol can be implemented in the memory interface circuit 122 and the communication interface 1083 to read data from the memory 12a. For example, the data read circuit 1080a can transmit via the (serial) communication channel SER: a command indicating the index of one of the K memory slots to be read, and the memory interface circuit 122 can provide the corresponding M bits of the requested memory slot in response via one or more (physical link) transmission frames; and / or a command requesting the transfer of all bits of the memory 12a, and the memory interface circuit 122 can provide the bits of the K memory slots sequentially in response via one or more transmission frames.

[0072] In various embodiments, the data read circuit 1080a may thus generate: a signal DATA providing L bits (e.g., 128 bits) to be stored in register 1081, such as the bit of the last memory slot read; a signal LOAD_OK indicating that a new memory slot has been read / stored in register 1081; optionally, a signal SECT indicating the number of memory slots last read, such as having 2 bits for indicating an index of K=4 memory slots; and optionally, a signal LOAD indicating that not all memory slots have been read.

[0073] As previously described, the hardware configuration circuit 108a is configured to read data from the memory 12a in response to the reset signal RST. Therefore, the data read circuit 1080a can be configured to initiate a read operation directly in response to the reset signal RST, or indirectly in response to the start signal START generated by the control circuit 1082a in response to the reset signal RST.

[0074] like Figure 6 As shown, in various embodiments, the data read circuit 1080a includes an error detection (ED) circuit 1086. Specifically, the error detection circuit 1086 is configured to calculate an additional M error detection bits based on the (L-M) bits of the configuration data CD stored in register 1081, i.e., the last memory slot received from the non-volatile memory 12a, according to the error detection scheme used. Furthermore, the error detection circuit 1086 compares the additional M error detection bits with the M error detection bits stored in register 1081. In response to determining that the additional M error detection bits correspond to the M error detection bits stored in register 1081, the error detection circuit 1086 de-asserts the error signal PD_ERR. Furthermore, in response to determining that the additional M error detection bits do not correspond to the M error detection bits stored in register 1081, the error detection circuit 1086 asserts the error signal PD_ERR.

[0075] For example, in various embodiments, the error detection circuit 1086 is configured to generate a single error signal PD_ERR indicating whether the current data stored in register 1081 (and provided via signal DATA) contains an error. However, specifically, where the data read circuit 1080a also generates a signal SECT, the error detection circuit 1086 can be configured to generate an error signal PD_ERR with multiple bits to indicate the error state of each of the K memory slots, such as a K-bit error signal PD_ERR, where the corresponding bits are associated with each of the K memory slots. For example, this is in Figure 6 The diagram schematically illustrates an example where, for the case of K=4 memory slots, the error signal PD_ERR has 4 bits.

[0076] Therefore, as Figure 7 As shown, in various embodiments, the control circuit 1082a of the hardware configuration circuit 108a is configured to receive the aforementioned signal DATA and the additional control signals LOAD_OK and PD_ERR, and optionally receive the signals LOAD and / or SECT.

[0077] Based on these signals, control circuitry 1082a generates signals to forward bits of signal DATA to the corresponding register 112. Specifically, as previously described, in various embodiments, each memory slot has a memory word size of L bits. In various embodiments, the register has P bits corresponding to a fraction of L (also indicated hereinafter as register word size), where the number L of bits in the memory slot is a multiple of the P bits in register 112 used to store configuration data within processing system 10a. For example, in various embodiments, register 112 has 16 or 32 bits, such as P=16 and L=128.

[0078] Therefore, in various embodiments, the control circuit cannot directly forward the L bits received via the signal DATA to a single register 112. Instead, the control circuit 1082a must generate Q = L / P write requests to store the L bits into Q registers 112, each write request having P bits. Thus, the number N of registers 112 also corresponds to K × Q. For example, in the exemplary cases of P = 16 and L = 128, the control circuit 1082a would be configured to generate Q = 8 write requests to store the L bits of the signal DATA into Q = 8 corresponding registers 112. For example, for this purpose, the control circuit 1082a may include a state machine 1096, implemented, for example, with sequential logic circuitry, configured to detect whether the signal LOAD_OK (and optionally the signal LOAD) indicates that the signal DATA includes new data. For example, when using the signals LOAD_OK and LOAD, the control circuit 1082a may include a logic gate 1094, such as an AND gate, which is configured to: assert the signal LOAD_OK' when the signal LOAD is asserted and the signal LOAD_OK is asserted; and cancel the assertion of the signal LOAD_OK when the signal LOAD is deasserted or the signal LOAD_OK is deasserted.

[0079] Therefore, in response to the detection of the signal LOAD_OK (or LOAD_OK') being asserted, state machine 1096 can, for example, sequentially increment the counter value CNT by 1 for Q clock cycles in response to the clock signal CLK. With the signal SECT omitted, the address signal ADR can therefore correspond to the count value CNT. Conversely, as... Figure 7As shown, when using the signal SECT, the count value can provide only a subset of the bits ADR1 of the addressing signal ADR, while the remaining bits of the addressing signal ADR can correspond to the signal SECT. For example, the signal SECT can correspond to the least significant bit (LSB) or the most significant bit (MSB) of the addressing signal ADR. For instance, in an exemplary embodiment, the addressing signal ADR has 5 bits, of which 2 bits are provided by the signal SECT and 3 bits ADR1 are provided by the counter of state machine 1096, which thus cyclically counts from 0 to (Q-1).

[0080] like Figure 7 As shown, in various embodiments, state machine 1096 may also generate (optionally) a write enable signal WEN. For example, in response to the signal LOAD_OK (or LOAD_OK'), signal WEN can be asserted for Q clock cycles, wherein for each of the Q clock cycles, signal ADR1 (or direct signal ADR) increments by 1, thereby indicating the address of a different register 112.

[0081] In various embodiments, the control circuit 1082a may also include a register or latch RSECT, which is configured to store the signal SECT, for example, in response to the signal LOAD_OK (or LOAD_OK'). For example, in the considered embodiment, the register RSECT is configured to: reset the value of the register RSECT to a reset value in response to the reset signal RST, and store the value of the signal SECT in response to the clock signal CLK and when the assertion signal LOAD_OK (or LOAD_OK') is triggered.

[0082] Therefore, in various embodiments, the control circuit 1082a is also configured to generate a signal DATA2 with P bits, wherein the signal DATA2 is used to provide the bits to be written to a given register 112 selected via the addressing signal ADR (see also...). Figure 4 For example, in various embodiments, bits of the signal DATA are selectively stored in (temporary) registers 1098 of the control circuit 1082a, specifically Q registers R1, ..., RQ, each with P bits. Therefore, a subset of the P bits of the signal DATA can be stored in each of the registers R1, ..., RQ. Thus, in this case, the data signal DATA2 can provide P bits from one of the registers R1, ..., RQ. For example, in the considered embodiment, for this purpose, the control circuit 1082a includes a multiplexer 1100 configured to generate the signal DATA2 by selecting the contents of one of the registers R1...RQ according to a count value CNT (e.g., a bit corresponding to bit ADR1).

[0083] like Figure 7 As shown, in various embodiments, the signal DATA is not directly provided to register 1098, but is processed by selection circuit 1104. Specifically, in various embodiments, selection circuit 1104 is configured to determine whether data read circuit 1080a has signaled an error by signal PD_ERR, and: in response to determining that signal PD_ERR has not signaled an error, provide signal DATA to register 1098; or in response to determining that signal PD_ERR has signaled an error, provide signal DATA' including predetermined configuration data to register 1098.

[0084] Therefore, in various embodiments, register 1098 may be configured to: reset the values ​​of registers R1, ..., RQ to reset values ​​in response to the reset signal RST, and store the value of the signal provided by selection circuit 1104 in response to the clock signal CLK and when the assertion signal LOAD_OK (or LOAD_OK') is invoked.

[0085] In this regard, such as Figure 7 As shown, when the signal PD_ERR includes multiple bits, the selection circuit 1104 may have an associated error handling (EP) circuit 1092, which is configured to assert a single error signal PD_ERR' when the error signal PD_ERR emits any error signal, for example, when at least one of the bits of the signal PD_ERR is asserted.

[0086] For example, this is in Figure 8 As shown, the error handling circuit 1092 includes a logic OR gate 1106 that receives the bit of the error signal PD_ERR at its input. Therefore, the error signal PD_ERR' may correspond to the signal at the output of the OR gate 1106, or the signal PD_ERR' may be generated via a latch or flip-flop 1108 that receives the signal at the output of the OR gate 1106 at its input. For example, in the considered embodiment, the error handling circuit 1092 includes a set-reset latch (or flip-flop) that receives the signal at the output of the OR gate 1106 at its set input and a reset signal RST at its reset input.

[0087] As previously described, the selection circuit 1104 is configured to provide bits 'DATA', including predetermined configuration data, when an error in the configuration data is signaled via the signal PD_ERR. For example, as Figure 7 As shown, in various embodiments, the selection circuit 1104 includes circuitry 1090 configured to provide bit DATA′ and multiplexer 1088 configured to provide signal DATA or signal DATA′ based on signal PD_ERR′.

[0088] In this regard, in various embodiments, the signal 'DATA' provides predetermined configuration data. For example, Figure 9 An embodiment of circuit 1090 is shown. Specifically, in the considered embodiment, selection circuit 1104, and in particular circuit 1090, is configured to generate signal DATA' by: holding L bits of the error detection bit PD of signal DATA; and rewriting the remaining (M-L) bits of configuration data with a reset value RV.

[0089] For example, in the simplest case, the reset value RV can be fixed for all K memory locations and can correspond to, for example, a bit sequence with all bits set to low. However, circuit 1090 can also be configured to determine the bits of the reset value RV based on the memory slot, for example, based on the signal SECT indicating the last memory slot read.

[0090] Therefore, in various embodiments, if the data read circuit detects an error in the bit read from a given memory slot, the control circuit 1082a stores the modified bit DATA′ in register 1098, and thus the modified bit DATA′ is transmitted to the corresponding register 112 via signal DATA2 and address signal ADR.

[0091] In various embodiments, for example by using the combined error signal PD_ERR', the modified bit DATA' will therefore also be used for subsequent memory slots, even if those memory slots may not contain errors. However, this does not take into account that one or more memory slots may have already been transferred to register 112.

[0092] Therefore, in various embodiments, once K memory slots have been read and processed, state machine 1096 can also generate another reset signal RST2. For example, as Figure 4 As shown, in various embodiments, this additional reset signal RST2 can be used to reset register 112. For example, in Figure 4 The diagram shows a logic OR gate 1160, which asserts the combined reset signal RST' when asserting one of the reset signals RST or RST2. Therefore, in this case, once the configuration data CD has been read from memory 12a and an error is detected in any memory slot, register 112 can be reset in response to the reset signal RST', thereby bringing register 112 to its reset value.

[0093] However, as Figure 9As shown, in various embodiments, the modified signal DATA' actually includes the original error detection bit PD provided via signal DATA, which should correspond to the error detection bit of the corresponding memory slot. Therefore, in this way, even if an error is detected in the bit sequence, the error detection bit PD is always transferred to register 112. In fact, as... Figure 10 As shown, the processing system 10a may include a communication interface 118, such as a debug interface, which allows reading data stored in register 112, for example, for debugging purposes. However, by generating another reset signal RST2, the contents of register 112 will be reset, thereby also rewriting the error detection bit PD stored in register 112.

[0094] Figure 11 Different embodiments of register 112a are shown in this regard.

[0095] Specifically, as described above, the control circuit 1082a is configured to store L bits of the signal DATA (or DATA') into respective Q registers 112 via the signal DATA2, each register having P bits. For example, in Figure 11 The diagram shows eight registers REG1, ..., REG8, each of which has, for example, 16 bits and can be used to store L bits of the first memory slot.

[0096] Therefore, the error detection bit PD will be stored in a predetermined location within register 112. For example, when the error detection bit PD is used in an exemplary location in a given memory slot, the corresponding error detection bit will be transferred to a given subset of the bits of the last register (e.g., register REG8). For example, configuration data CD1 will be stored in the first subset REG8a of 8 bits in registers REG1, ..., REG7 and register REG8, while the error detection bit PD will be stored in the second subset REG8b of 8 bits in register REG8.

[0097] Therefore, in various embodiments, in order to allow reading of error detection bits (e.g., bit PD1), register bits of register 112, which is arranged to store bits of configuration data CD, are configured to reset their contents in response to either or (e.g.) a reset signal RST and a reset signal RST'. Conversely, register bits of register 112, which is arranged to store bits of error detection data PD, are configured to reset their contents in response to a reset signal RST, but not in response to a reset signal RST'. Thus, in this way, even when a reset signal RST2 resets other register bits in response to an error in the data stored in memory 12a, the contents of register bits of register 112 containing the stored error detection bit PD are maintained, and communication interface 118 can be used to read the error detection bit.

[0098] Figure 12 Another embodiment of register 112a is shown.

[0099] Specifically, in the considered embodiment, the control circuit 1082a includes K additional registers 1110, each register having M bits for storing error detection bits PD (e.g., bits PD1, PD2, PD3, and PD4). For example, in the considered embodiment, the control circuit 1082a is configured to, for example, use a signal provided by the register RSECT as an addressing signal for selecting one of the K additional registers, to access the bit sequence PD of the signal DATA (see also...). Figure 9 The data is stored in the corresponding register 1110. For example, in the considered embodiment, demultiplexer 1112 is used to assert a write enable signal for one of the registers 1110 by selectively forwarding the signal WEN according to the signal RESCT, thereby selecting one of the registers 1110 according to the signal RSECT, and storing the bit sequence PD when the WEN signal is asserted. Typically, the signals RSECT and WEN can also be replaced by the signals SECT and LOAD_OK (or LOAD_OK'). Therefore, in the considered embodiment, register 1110 is configured to be reset in response to the reset signal RST, and to retain its contents when the reset signal RST2 is asserted.

[0100] In the considered embodiment, the bits of register 112a used to provide the error detection bit PD are implemented using (e.g., read-only) shadow registers. In this case, the bits of register 112a used to provide the error detection bit PD, such as register REG8b, are implemented using registers (with M bits) that can be read by a read request transmitted to register 112a and whose contents are automatically updated based on the contents of the corresponding register 1110, for example, the contents of register 1110 used to store bit PD1 are automatically stored in register REG8b. Therefore, in this case, even when a reset is performed in response to the signal RST' of the shadow register (e.g., REG8b) used to provide the error detection bit PD, the contents of these registers are automatically updated again in the next clock cycle by transferring the contents of register 1110 to the corresponding register 112a.

[0101] Alternatively, the bits in register 112a used to provide the error detection bit PD can be omitted, for example, register REG8b, and the individual bits can be directly connected to the individual bits in register 1110. Therefore, in this case, the contents of register 1110 can be read by sending a read request to register 112a, for example, sending a read request to register REG8, where the first bit is read from register REG8a, while the second bit (REG8b) is read directly from register 1110 used to store the bit sequence PD1.

[0102] Figure 13 The diagram also shows an embodiment of the operation of the control circuit 1082a, particularly the state machine 1096.

[0103] Specifically, once state machine 1096 is activated at start step 4000, for example after processing system 10a is powered on, state machine 1096 activates the "RESET" state at step 4002. Specifically, in the considered embodiment, state machine 1096 remains in the RESET state until data is received from the first memory slot. As previously described, data reception can be signaled via the signal LOAD_OK (or LOAD_OK' generated by logic gate 1094). This is illustrated, for example, via step 4004, where state machine 1096 verifies whether the signal LOAD_OK (or LOAD_OK') has been asserted. If the signal LOAD_OK (or LOAD_OK') has been deasserted (verification step 4004 outputs "N"), state machine 1096 returns to step 4002.

[0104] Conversely, in the case of the assertion signal LOAD_OK (or LOAD_OK') (verifying the output "Y" of step 4004), state machine 1096 proceeds to step 4006, where the state machine activates the WAIT state, where state machine 1096 waits for a single clock cycle. Typically, the WAIT state is purely optional and is useful when the signals DATA (or DATA') and / or PD_ERR (or PD_ERR') and / or SECT are stored in register 1098 and / or multiplexer 1088 and / or RSECT, respectively. In practice, these registers can store the corresponding signals directly in response to the signal LOAD_OK (or LOAD_OK'), for example, in parallel with the operation of state machine 1096.

[0105] Therefore, in the considered embodiment, state machine 1096 does not leave the RESET state directly in response to the reset signal RST, but rather in response to the signal LOAD_OK (or LOAD_OK'). However, this does not change the operation, because as regarding Figure 6 The data read circuit 1080a may have started reading data from the memory 12a in response to the detection that the reset signal RST has been de-asserted.

[0106] This is also Figure 14 As shown in the figure, Figure 14 It was also shown Figure 7The following are exemplary waveforms of the main signals shown. Specifically, once the reset signal RST is de-asserted, for example, once the signal RST is high, the data read circuit 1080a reads L bits from the first memory slot and then applies the received bits to the signal DATA, checks the contents of the bits, and finally asserts the error signal PD_ERR. Furthermore, the data read circuit 1080a asserts the signal LOAD_OK, thereby advancing the state (STATE) of the state machine 1096 from state reset to state wait.

[0107] In the considered embodiment, state machine 1096 then proceeds to step 4008, where the state machine activates state WE, and state machine 1096 asserts the write enable signal WEN and waits for a single clock cycle. This also... Figure 14 As shown in the diagram. Specifically, when the signal WEN is asserted for the first time, the signal ADR is set to "0", for example because the count value CNT generated by state machine 1096 is set to "0" and the signal SECT provided by data read circuit 1080a is set to "0". This means that the contents of register R1 are stored in register 112 associated with address "0", for example... Figure 11 The register REG1 is shown.

[0108] In the considered embodiment, state machine 1096 then proceeds to step 4010, where state machine 1096 activates state CNT, maintaining the assertion write enable signal WEN, but incrementing the count value CNT by 1. Therefore, the count value CNT and address ADR are incremented by 1, thereby storing the contents of register R2 into register 112 associated with address "1", for example... Figure 11 The register REG2 is shown.

[0109] Therefore, state machine 1096 can remain in state CNT until the value CNT has reached the value (Q-1). This is illustrated, for example, via verification step 4012, where state machine 1096 verifies whether the count value CNT is less than (Q-1). Thus, if the count value CNT is less than (Q-1), state machine 1096 can return to step 4008 / remain in state CNT, thereby sequentially incrementing the count value CNT and correspondingly incrementing the address ADR, thereby writing the data stored in register 1098 into the respective registers 112 indicated by the addressing signal ADR.

[0110] Conversely, when the count value CNT corresponds to or is greater than (Q-1), state machine 1096 proceeds to step 4014, where the state machine activates state LINC, and the state machine releases the assertion written to the enable signal WEN and waits for a single clock cycle.

[0111] State machine 1096 then verifies in step 4016 whether data from another memory slot should be processed, for example by verifying whether the signal SECT is less than the number (K-1). For example, when another memory slot should be processed (verifying the output "Y" of step 4016), for example when the signal SECT is less than the number (K-1), state machine 1096 proceeds to step 4018, where the state machine activates the stop state STOP. Specifically, in the considered embodiment, the state machine remains in the stop state until the data read circuit 1080a signals via the signal LOAD_OK that a bit from a new memory slot has been read. For example, for this purpose, the state machine may verify in step 4020 whether the signal LOAD_OK (or LOAD_OK') is asserted, and return to step 4018 if the signal is not asserted, and return to step 4006 if the signal is asserted. Those skilled in the art will understand that... Figure 13 The reset of the count value CNT is not specifically shown. In fact, in the embodiment under consideration, when a 3-bit counter is used to count 8 cycles, the count value CNT will be automatically reset to the value "0". Alternatively, for example, in step 4006, the count value CNT can also be explicitly reset.

[0112] Therefore, in the considered embodiment, steps 4002-4020 are used only to manage the transfer of bits of the signal DATA or DATA' (as provided by the selection circuit 1104) to register 112 by generating the addressing signal ADR (via the count value CNT) and the write enable signal WEN. In practice, the rewriting of the bits of the signal DATA is managed by the selection circuit 1104, while the selection of the current signal DATA2 is managed by the multiplexer 1100.

[0113] Once all bits of the K memory slots have been processed, state machine 1096 can verify whether an error has occurred. In the considered embodiment, state machine 1096 may use only the signal PD_ERR' (generated by error handling circuitry 1092) that indicates whether any of the memory slots contains an error. For example, when the signal PD_ERR merely signals that the current bit of signal DATA contains an error, error handling circuitry 1092 may be configured to generate signal PD_ERR' by asserting signal PD_ERR' (e.g., via a set-reset flip-flop or latch) once signal PD_ERR is asserted.

[0114] Therefore, in the considered embodiment, when the last memory slot has been processed (verification step 4016 output "N"), for example when the signal SECT corresponds to the number (K-1), state machine 1096 proceeds to verification step 4022, where the state machine verifies the logic level of signal PD_ERR'. If signal PD_ERR' is deasserted (verification step 4022 output "N"), state machine 1096 proceeds to stop step 4026, where the state machine activates the state "End" indicating that the operation is complete. Conversely, if the signal PD_ERR' is asserted (verification step 4022 output "Y"), state machine 1096 proceeds to step 4024, where the state machine activates state ERR, where state machine 1096 asserts signal RST2, and then proceeds to step 4026.

[0115] This is also Figure 14 As shown, the data assertion signal PD_ERR' is for the second memory slot (SECT="1"), but the state machine advances to step ERR, so that the reset signal RST2 is asserted only when the data has been transferred to the last register 112 (e.g., with the associated address "31").

[0116] In fact, as described above, in various embodiments, the hardware configuration circuitry still processes all K memory slots to transfer error detection data to register 112, where register 112 is configured to maintain the error detection data even during the assertion reset signal RST2.

[0117] Therefore, the aforementioned hardware configuration circuit 108a has several advantages. Typically, this solution allows the processing system 10a to be protected from the download of erroneous configuration data. In this regard, by resetting the configuration data via the reset signal RST2 in case of an error, mismatches caused by possible faults between correctly written registers and blanked registers can be avoided. Furthermore, in case of an error, the device can use the default (e.g., safe) configuration RV to allow the device to operate in a normal state. However, the processing system 10a is able to maintain the error detection bit PD to provide the user with the possibility of finding the source of the error by reading the corresponding bit in register 112.

[0118] Of course, without departing from the principles of the invention, the details of the construction and embodiments may vary extensively with respect to what is described and shown herein by way of example only, without departing from the scope of the invention as defined by the appended claims.

[0119] For example, while previous solutions used error detection data PD, this data could also include error correction code (ECC) bits, determined, for example, based on single error correction and double error detection (SECDED) codes. For instance, in this case, the error detection circuit 1086 could be replaced by an error detection and correction circuit, where the signal PD_ERR indicates whether the bits of the signal DATA contain an uncorrectable error.

[0120] The claims are an integral part of the technical teachings disclosed herein.

Claims

1. A processing system, comprising: A serial non-volatile memory includes K memory slots, each memory slot having L bits, wherein the L bits include a first number of configuration data bits and a second number of error detection bits, the second number of error detection bits being calculated based on the corresponding first number of configuration data bits. A reset circuit is configured to generate a reset signal in response to power-on of the processing system; N configuration registers, each associated with a single address and having P bits, wherein each configuration register is reset to a corresponding reset value in response to the reset signal, wherein the L bits of each memory slot correspond to a multiple Q of the P bits of the configuration register, where Q = L / P, and N = Q × K, wherein Q configuration registers are associated with each memory slot; One or more circuits are configured to change their operation based on bit values ​​stored in the configuration register; The hardware configuration circuit includes Q temporary registers, each of which has P bits; The hardware configuration circuitry is configured to, in response to the reset signal, sequentially read data from the serial non-volatile memory and store the read data into the corresponding configuration register by performing the following operations on each of the K memory slots of the serial non-volatile memory: Determine the index of the current memory slot of the serial non-volatile memory, and receive the L bits of the current memory slot from the serial non-volatile memory via serial communication; Once the L bits of the current memory slot have been received: Another error detection bit is calculated based on the received configuration data bits, and an error signal is selectively asserted by comparing the received error detection bit with the calculated error detection bit. Verify whether the error signal is asserted, and in response to determining that the error signal is asserted, assert another error signal, whereby the other error signal indicates whether the data in any read memory slot includes an error; Verify whether the other error signal is asserted, and: a) In response to determining that the other error signal has been de-asserted, the received L bits are stored in the temporary register; as well as b) In response to determining that the other error signal has been asserted, a predetermined configuration data bit is stored in the temporary register; By providing the contents of one of the Q temporary registers and generating an address signal with an address associated with the corresponding configuration register via a counter, the contents of the Q temporary registers are sequentially stored into the corresponding Q configuration registers. The hardware configuration circuit is configured to verify whether the other error signal has been asserted once data has been received from the K memory slots. as well as In response to determining that the other error signal has been asserted, a second reset signal is generated, the second reset signal being used to reset at least a portion of the contents of the configuration register.

2. The processing system according to claim 1, wherein the hardware configuration circuit includes a data reading circuit, the data reading circuit comprising: A receive register with L bits; A serial communication interface is configured to receive the L bits of the current memory slot from the serial non-volatile memory via serial communication, and to assert a control signal in response to the receipt of the corresponding L bits; as well as An error detection circuit is configured to calculate the other error detection bit and selectively assert the error signal.

3. The processing system of claim 2, wherein the serial communication interface is configured to generate a signal indicating the index of the current memory slot of the serial non-volatile memory.

4. The processing system of claim 3, wherein the serial communication interface is configured to receive the L bits of the current memory slot by sending a read request to the serial non-volatile memory, the read request including data identifying the index of the current memory slot of the serial non-volatile memory.

5. The processing system of claim 2, wherein the hardware configuration circuit includes a control circuit, the control circuit includes a selection circuit, the selection circuit being configured to provide the received L bits or the predetermined configuration data bits to the temporary register according to the other error signal, and wherein the temporary register is configured to store data provided by the selection circuit in response to the control signal.

6. The processing system according to claim 3, wherein the hardware configuration circuit includes a sequential logic circuit implementing a state machine, wherein the state machine is configured to: In response to the control signal, the count value is sequentially increased for Q consecutive clock cycles; The addressing signal therein corresponds to the count value.

7. The processing system according to claim 6, wherein the state machine is configured as follows: Based on the count value and the signal indicating the index of the current memory slot of the serial non-volatile memory, it is determined whether all memory slots have been transferred to the configuration register; and In response to determining that all memory slots have been transferred to the configuration register, the other reset signal is asserted based on the other error signal.

8. The processing system of claim 3, wherein the hardware configuration circuit includes a sequential logic circuit implementing a state machine, wherein the state machine is configured to: In response to the control signal, the count value is sequentially increased for Q consecutive clock cycles; The addressing signal is determined by combining bits of the count value and bits of the signal indicating the index of the current memory slot.

9. The processing system according to claim 8, wherein the state machine is configured as follows: Based on the count value and the signal indicating the index of the current memory slot of the serial non-volatile memory, it is determined whether all memory slots have been transferred to the configuration register. In response to determining that all memory slots have been transferred to the configuration register, the other reset signal is asserted based on the other error signal.

10. The processing system of claim 1, wherein the hardware configuration circuit is configured to, in response to determining that the other error signal is asserted, store the received L bits of the error detection bits together with the predetermined configuration data bits into the temporary register, wherein the error detection bits received for the K memory slots are stored in predetermined bit positions of the configuration register, and wherein the configuration register is configured to: The contents of the configuration register are reset in response to the reset signal; and In response to the other reset signal, the contents of the configuration register are reset except for the predetermined bit position.

11. The processing system of claim 1, wherein the hardware configuration circuit is configured to store the received L bits of the error detection bits into another register, wherein the other register is configured to be reset in response to the reset signal and to maintain its contents when the other reset signal is asserted, and wherein the bits of the configuration register for providing the error detection bits are implemented using a shadow register connected to the other register.

12. The processing system of claim 1, further comprising a communication interface configured to transmit the contents of one or more configuration registers in the configuration register to an external device.

13. The processing system of claim 1, further comprising circuitry configured to store a first number of configuration data bits and a second number of error detection bits into each of the K memory slots of the serial non-volatile memory.

14. The processing system of claim 12, further comprising circuitry for activating the processing system to cause the hardware configuration circuitry to operate to sequentially read data from the serial non-volatile memory and store the read data or the predetermined configuration data bits into the corresponding configuration register.

15. The processing system of claim 14, further comprising circuitry configured to read the contents of the configuration register via the communication interface.

16. An integrated circuit, comprising: The processing system according to claim 1.

17. A processing system, comprising: A non-volatile memory includes multiple memory slots, wherein each memory slot stores configuration data bits and error detection bits calculated based on the configuration data bits; Multiple configuration registers, associated with each memory slot; The circuit, the operation of which is controlled according to data stored in the configuration register; Hardware configuration circuitry, including multiple temporary registers; The hardware configuration circuit is configured as follows: Receive the configuration data bits from the memory slot; Calculate another error detection bit based on the received configuration data bits; Compare the received error detection bit with another calculated error detection bit; An error signal is asserted in response to the comparison to indicate that the received configuration data bits contain an error; Data is stored in the configuration register in the following manner: a) In response to the clear assertion of the error signal, the received configuration data bits are stored in the temporary register; b) In response to the assertion of the error signal, store the predetermined configuration data bits into the temporary register; as well as c) Transfer the contents from the temporary register to the configuration register.

18. The processing system of claim 17, wherein the plurality of configuration registers are configured to reset at least a portion of the contents of the configuration registers in response to an assertion of the error signal.

19. The processing system of claim 17, wherein each configuration register is configured to be reset in response to power-on of the processing system.

20. The processing system of claim 17, wherein storing data in the configuration register comprises sequentially storing the contents of the temporary register into the respective configuration register.

21. The processing system according to claim 17, wherein the hardware configuration circuit includes a data reading circuit, the data reading circuit comprising: Receive register; A serial communication interface is configured to receive data from the memory slot via serial communication from the non-volatile memory, and in response to assert control signals. as well as An error detection circuit is configured to calculate the other error detection bit and selectively assert the error signal.

22. The processing system of claim 21, wherein the hardware configuration circuitry further includes a control circuitry, the control circuitry including a selection circuitry configured to provide the configuration data bits or the predetermined configuration data bits to the temporary register according to the error signal, and wherein the temporary registerry is configured to store data provided by the selection circuitry in response to the control signal.

23. An integrated circuit, comprising: The processing system according to claim 17.

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