Chip debugging method, device, system and chip

Abstract

The application relates to the technical field of debugging, and discloses a chip debugging method, device, system and chip, the method comprising the following steps: obtaining a debugging task; performing task division based on the task type of a debugging subtask in the debugging task to obtain a debugging subtask corresponding to the task type; distributing the debugging subtask to a corresponding debugging channel based on the task type of the debugging subtask; obtaining the number of debugging subtasks corresponding to each debugging channel, and adjusting the cache space corresponding to the debugging channel based on the number; and processing the debugging subtask of the debugging channel through the adjusted cache space to obtain a debugging result of the chip. The application can solve the problem of low chip debugging efficiency.

Description

Technical Field

[0001] This invention relates to the field of debugging technology, and specifically to a chip debugging method, apparatus, system, and chip. Background Technology

[0002] In recent years, with the rapid development of semiconductor technology, more and more electronic devices have adopted IC chips. Simultaneously, along with the rapid advancement of chip technology, chip size has become smaller and their functions more complex. Currently, the boundary scan mechanism is mainly used to debug the chip's circuit system. This involves setting a boundary scan structure between the IC chip's input / output pins and the core circuitry, allowing debugging of the chip's internal circuitry from external pins. However, in actual debugging, this method is limited by the SWD or JTAG communication protocol between the chip and the debugging tool. Furthermore, only one debugging path can interact with the external debugging tool at a time, significantly restricting the debugging speed and resulting in low debugging efficiency. Summary of the Invention

[0003] In view of this, the present invention provides a chip debugging method, apparatus, system and chip to solve the problem of low chip debugging efficiency.

[0004] In a first aspect, the present invention provides a chip debugging method, the method comprising:

[0005] Obtain debugging tasks;

[0006] Based on the task type of the debugging subtask in the debugging task, the task is divided to obtain the debugging subtask corresponding to the task type;

[0007] Based on the task type of the debugging subtask, the debugging subtask is assigned to the corresponding debugging channel;

[0008] Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number;

[0009] The debug subtasks of the debug channel are processed using the adjusted cache space to obtain the debug results of the chip.

[0010] In this approach, debugging tasks are divided into debugging subtasks of different task types and assigned to corresponding debugging channels for processing. This allows for parallel processing of debugging subtasks across multiple debugging channels, improving chip debugging efficiency. Furthermore, adjusting the cache space corresponding to each debugging channel based on the number of debugging subtasks allocated to it enables highly efficient utilization of the cache space.

[0011] In one optional implementation, processing the debug subtask of the debug channel using the adjusted cache space to obtain the chip's debug results includes:

[0012] The chip is debugged according to the debug subtask of the debug channel, and the debug data during the debugging process is cached in the cache space corresponding to the debug channel to obtain the debug result of the chip; wherein, the debug data includes data written to the chip memory and / or data read from the chip memory.

[0013] In this approach, when the chip is debugged according to the debug subtask of the debug channel, the debug data during the debugging process is cached in the cache space corresponding to the debug channel. Therefore, the fast data access characteristic of the cache can be fully utilized to further improve the debugging efficiency of the chip.

[0014] In one optional implementation, the step of debugging the chip according to the debugging subtask of the debugging channel, and caching the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip, includes:

[0015] When the debugging subtask is a read task, the data in the chip memory is read according to the debugging subtask of the debugging channel;

[0016] The read data is cached in the cache space corresponding to the debugging channel;

[0017] If the debugging subtask corresponding to the debugging channel is completed, a read message is sent to the external debugging tool to read data from the cache space corresponding to the debugging channel.

[0018] In this approach, on the one hand, data from the chip memory is read in parallel through multiple debugging channels to improve the chip's debugging efficiency; on the other hand, the read chip data is saved to the cache space corresponding to the debugging channel, and then the external debugging tool reads the data from the cache space, thereby achieving high-efficiency utilization of the cache, making full use of the higher efficiency of cache data access, improving the data transmission speed between the chip and the external debugging tool, and thus improving the chip's debugging efficiency.

[0019] In one optional implementation, the step of debugging the chip according to the debugging subtask of the debugging channel and caching the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip further includes:

[0020] When the debugging subtask is a write task, the data in the corresponding cache space is written to the chip memory according to the debugging subtask of the debugging channel;

[0021] Obtain the data write status corresponding to each of the debugging subtasks, and feed back the data write status corresponding to each of the debugging subtasks to the external debugging tool.

[0022] In this approach, since the data to be written to the chip memory corresponding to the debugging subtask has been pre-cached in the corresponding cache space, multiple debugging channels can be parallelized to write the data in their corresponding cache spaces to the chip memory, thereby further improving the chip's debugging efficiency.

[0023] In one optional implementation, assigning the debugging subtask to a corresponding debugging channel based on its task type includes:

[0024] Determine the debugging channel corresponding to the task type of the debugging subtask;

[0025] When the number of debugging channels corresponding to the task type is 1, the debugging subtask is assigned to the debugging channel;

[0026] When the number of debugging channels corresponding to the task type is not 1, the debugging subtask is assigned to the corresponding debugging channel based on the data processing speed or priority configuration of the debugging channel.

[0027] In this approach, debugging subtasks are first assigned to corresponding debugging channels based on their task type. If the number of debugging channels corresponding to a given task type is not 1, the subtasks are further assigned to corresponding debugging channels based on their data processing speed or priority configuration. Therefore, this approach enables debugging channels with faster data processing speeds or higher priority configurations to handle more debugging subtasks, thereby further improving chip debugging efficiency, while allowing multiple debugging channels to process in parallel.

[0028] In one optional implementation, adjusting the cache space corresponding to the debugging channel based on the quantity includes:

[0029] Calculate the ratio of the number of debugging subtasks among the various debugging channels;

[0030] Adjust the cache size corresponding to the debugging channel based on the ratio of the number of channels.

[0031] In this approach, the cache size corresponding to each debug channel is adjusted based on the ratio of the number of debug subtasks allocated between debug channels. Therefore, high-efficiency cache utilization can be achieved.

[0032] In one optional implementation, the method further includes:

[0033] When the cache space corresponding to the debugging channel meets the preset cache threshold condition, cache status information is sent to the external debugging tool so that the external debugging tool can read data from the cache space corresponding to the debugging channel or pause writing data to the cache space corresponding to the debugging channel.

[0034] In this method, when the cache space corresponding to the debugging channel meets the preset cache threshold condition, the external debugging tool is notified to read data from the cache space or to pause writing data to the cache space, thereby avoiding data overflow in the cache space and causing chip debugging errors.

[0035] In a second aspect, the present invention provides a chip debugging apparatus, the apparatus comprising:

[0036] The data receiving module is used to acquire debugging tasks;

[0037] The task partitioning module is used to partition tasks based on the task type of the debugging subtasks in the debugging task, and obtain the debugging subtasks corresponding to the task type.

[0038] The task allocation module is used to allocate the debugging subtask to the corresponding debugging channel based on the task type of the debugging subtask;

[0039] A cache allocation module is used to obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number;

[0040] The task processing module is used to process the debugging subtasks of the debugging channel using the adjusted cache space to obtain the chip's debugging results.

[0041] Thirdly, the present invention provides a chip debugging system, the system comprising:

[0042] External debugging tools;

[0043] The chip is debugged by performing the chip debugging method described in the first aspect above or any of its corresponding embodiments.

[0044] Fourthly, the present invention provides a chip comprising:

[0045] The memory and the processor are interconnected and communicate with each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the chip debugging method of the first aspect or any of its corresponding embodiments described above. Attached Figure Description

[0046] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating a chip debugging method according to an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of a chip data transmission process according to an embodiment of the present invention;

[0049] Figure 3 This is a schematic diagram of the structure of a chip central module according to an embodiment of the present invention;

[0050] Figure 4 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0051] Figure 5 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0052] Figure 6 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0053] Figure 7 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0054] Figure 8 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0055] Figure 9 This is a flowchart illustrating another chip debugging method according to an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of a process for reading chip contents for debugging according to an embodiment of the present invention;

[0057] Figure 11 This is a schematic diagram of a process for debugging the content written to a chip according to an embodiment of the present invention;

[0058] Figure 12 This is a structural block diagram of a chip debugging device according to an embodiment of the present invention;

[0059] Figure 13 This is a schematic diagram of the hardware structure of a chip according to an embodiment of the present invention. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0061] An IC (Integrated Circuit Chip) is a chip made by placing a large number of transistors, resistors, capacitors, and other microelectronic components onto a plastic substrate. IC chips consist of wafer chips and packaged chips, and correspondingly, an IC chip production line comprises two parts: a wafer production line and a packaging production line. Currently, with the rapid development of semiconductor technology, more and more electronic devices are using IC chips, and with the rapid advancement of chip technology, IC chips are becoming smaller and smaller, and their functions are becoming more and more complex. The traditional method of using physical probes to debug the chip's circuit system is no longer applicable; it has been replaced by a virtual probe method, namely, the boundary scan mechanism. The boundary scan mechanism mainly uses a boundary scan structure between the IC chip's input / output pins and the core circuitry, allowing for debugging of the chip's internal components using fewer external pins.

[0062] However, the debugging speed of boundary scan mechanisms is often limited by the communication protocol between the chip and external debugging tools. Only one debugging path can interact with the external tool at a time, significantly restricting debugging speed. This results in substantial time spent waiting for data transmission during large-scale data interactions like chip debugging, greatly impacting debugging efficiency. Therefore, some traditional chip debugging methods improve communication speed by enhancing circuit signal quality. However, this improvement is often minimal and limited by SWD or JTAG communication protocols. To establish a stable connection between the chip and external debugging tools, the chip's maximum communication frequency must be less than 1 / 8 of its operating frequency. Furthermore, some chip debugging methods propose high-speed SWD protocol conversion interface circuits to improve data transmission speed through protocol conversion, but these are still limited by the SWD protocol's debugging speed; the theoretical maximum speed of the SWD protocol is only 50MHz. Therefore, these chip debugging methods have significant speed limitations, failing to achieve high-speed data transmission in large-scale data scenarios, severely restricting chip debugging efficiency.

[0063] Based on this, in order to solve the problem of low chip debugging efficiency caused by the limited speed of existing debugging interfaces, the present invention provides a chip debugging method. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than that shown here.

[0064] This embodiment provides a chip debugging method that can be used for IC chips. Figure 1 This is a flowchart of the chip debugging method according to the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0065] Step S101: Obtain the debugging task.

[0066] In this embodiment of the invention, the debugging task is transmitted to the chip by an external debugging tool via a high-speed communication protocol. Specifically, the communication protocol between the external debugging tool and the chip can be any high-speed communication protocol, such as JTAG, SWD, USB, etc. JTAG (Joint Test Action Group) is the common name for IEEE standard 1149.1, also known as Standard Test Access Port and Boundary Scan Structure, used to verify the functionality of designed and tested printed circuit boards. SWD (Serial Wire Debug) is a serial debugging interface. Compared to JTAG, SWD only requires two wires during debugging: SWCLK and SWDIO, thus reducing the occupation of the microcontroller's GPIO ports. Furthermore, SWD allows for online debugging. USB (Universal Serial Bus) is an external bus standard used to standardize the connection and communication between computers and external devices; it is an interface technology used in the PC field.

[0067] Step S102: Based on the task type of the debugging subtask in the debugging task, the task is divided into debugging subtasks corresponding to the task type.

[0068] In this embodiment of the invention, the debugging task is divided into debugging subtasks corresponding to the task type according to the task type, so as to allocate the debugging subtasks to the corresponding debugging channels, realize the simultaneous debugging of the chip by multiple debugging channels, and improve debugging efficiency.

[0069] Step S103: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel.

[0070] See Figure 2In this embodiment of the invention, the chip is provided with a central module, an on-chip protocol conversion module, and a DAP module (i.e., debug access interface). Specifically, the on-chip protocol conversion module includes an AHB bus conversion module, an APB bus conversion module, and an AXI bus conversion module. The number of on-chip protocol conversion modules and DAP modules depends on the specific situation of the chip. The on-chip protocol conversion modules and DAP modules are mainly used to convert data in communication protocol formats such as JTAG, SWD, and USB between external debugging tools and the chip into the format of the on-chip bus protocol, so that data can be read or written on the chip's on-chip bus to complete the debugging work of the chip. Among them, 1. AHB (Advanced High Performance Bus): mainly used for connection between high-performance modules such as CPU, DMA, and DSP. As the on-chip system bus of SoC, AHB includes the following characteristics: single clock edge operation, non-tri-state implementation, support for burst transmission, support for segmented transmission, support for multiple master controllers, configurable 32-bit to 128-bit bus width, and support for byte, half-word, and word transmission. 2. AXI (Advanced eXtensible Interface): A bus protocol, the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is an on-chip bus designed for high performance, high bandwidth, and low latency. 3. APB (Advanced Peripheral Bus): The chip's peripheral bus. This bus protocol is one of the AMBA bus structures proposed by ARM and has almost become a standard on-chip bus structure. APB is mainly used for connections between low-bandwidth peripheral devices. 4. DAP (Debug Access Port): Composed of DP (debugport), AP (access port), and DAPBUS interconnect components. DP is used to manage connections with external debuggers, AP is used to access on-chip system resources, and multiple APs of each type are possible. DAPBUS interconnect is used to connect DP to one or more APs.

[0071] For example, in actual operation, data can be converted to AHB protocol format via an AHB bus conversion module for reading or writing data on the AHB bus; data can be converted to APB protocol format via an APB bus conversion module for reading or writing data on the APB bus; data can be converted to AXI protocol format via an AXI bus conversion module for reading or writing data on the AXI bus; and data can be converted to the DAP bus interface protocol via a DAP module for reading or writing data on the DAP bus. Understandably, in this invention, the debug channel is the debug branch where the on-chip protocol conversion module and the DAP module reside. In the chip, each debug channel formed by the chip's central module and the various on-chip protocol conversion modules and DAP modules within the chip can perform data read and write operations, and the debug channels can work in parallel. Specifically, the central module breaks down the debug tasks of external debug tools into debug subtasks of different task types, and then selects appropriate on-chip bus conversion modules and / or DAP modules to process the debug subtasks.

[0072] It should be noted that since the access addresses of the AHB bus, AXI bus, APB bus, and DAP bus overlap and differ, in actual operation, the central module needs to be configured differently according to different system designs so that the debugging subtasks can be assigned to the appropriate on-chip bus conversion module or DAP module for processing, in order to be compatible with different external debugging tools.

[0073] Understandably, based on the task type of the debugging subtask, the debugging subtask is assigned to the corresponding debugging channel. The purpose of this is to assign the debugging subtask to the corresponding on-chip protocol conversion module or DAP module so that the debugging subtask is converted into instructions in the on-chip bus protocol format, thereby enabling read and write operations on the chip on the corresponding on-chip bus, and reducing the impact of the speed limitations of communication protocols such as JTAG and SWD on the chip debugging efficiency.

[0074] Step S104: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number.

[0075] For example, see Figure 3 The central module of the chip includes a task distribution module for splitting read and write tasks and a cache module. In this embodiment of the invention, each time a debug task is divided, a corresponding cache division occurs to allocate different cache addresses to different debug channels (i.e., Figure 3 Branches 1 to n shown are used for data read and write caching. Specifically, when only one debug channel in the chip is performing a debug task, that debug channel occupies all the cache space.

[0076] Step S105: The debugging subtask of the debugging channel is processed using the adjusted cache space to obtain the debugging results of the chip.

[0077] The chip debugging method provided in this embodiment divides the debugging task into debugging subtasks of different task types and assigns them to corresponding debugging channels for processing. Therefore, multiple debugging channels can process the debugging subtasks in parallel, thereby improving the chip debugging efficiency. At the same time, by adjusting the cache space corresponding to each debugging channel based on the number of debugging subtasks allocated to each debugging channel, high-efficiency utilization of the cache space can be achieved.

[0078] Figure 4 This is a flowchart of another chip debugging method according to an exemplary embodiment. Figure 4 As shown, the chip debugging method includes the following steps:

[0079] Step S201: Obtain the debugging task. The implementation method is the same as in step S101, and will not be repeated here.

[0080] Step S202 involves dividing the debugging subtasks within the debugging task into subtasks based on their task types, thereby obtaining the debugging subtasks corresponding to the task types. This is the same implementation as step S102 and will not be repeated here.

[0081] Step S203: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be repeated here.

[0082] Step S204: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number. This is the same implementation as step S104 and will not be described again here.

[0083] Step S205: Debug the chip according to the debugging subtask of the debugging channel, and cache the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip; wherein, the debugging data includes data written to the chip memory and / or data read from the chip memory.

[0084] Understandably, if the debugging subtask is a read task, then the debugging data is data read from the chip memory and written to the cache space; if the debugging subtask is a write task, then the debugging data is data cached in the cache space by external debugging tools, waiting to be written to the chip memory.

[0085] The chip debugging method provided in this embodiment caches the debugging data during the debugging process in the cache space corresponding to the debugging channel when debugging the chip according to the debugging sub-task of the debugging channel. Therefore, it can make full use of the fast data access characteristics of the cache to further improve the debugging efficiency of the chip.

[0086] Figure 5 This is a flowchart of yet another chip debugging method proposed according to an exemplary embodiment. For example... Figure 5 As shown, the chip debugging method includes the following steps:

[0087] Step S301: Obtain the debugging task. The implementation method is the same as in step S101, and will not be repeated here.

[0088] Step S302 involves dividing the debugging subtasks within the debugging task into subtasks based on their task types, thereby obtaining the debugging subtasks corresponding to the task types. This is the same implementation as step S102 and will not be repeated here.

[0089] Step S303: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be described again here.

[0090] Step S304: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number. This is the same implementation as step S104, and will not be described again here.

[0091] Step S305: Process the debugging subtask of the debugging channel using the adjusted cache space to obtain the debugging result of the chip.

[0092] Specifically, step S305 includes:

[0093] Step a1: When the debugging subtask is a read task, read the data in the chip memory according to the debugging subtask of the debugging channel;

[0094] Step a2: Cache the read data into the cache space corresponding to the debugging channel;

[0095] Step a3: If the debugging subtask corresponding to the debugging channel is completed, a read message is sent to the external debugging tool to read data from the cache space corresponding to the debugging channel.

[0096] The chip debugging method provided in this embodiment improves chip debugging efficiency by reading data from chip memory in parallel through multiple debugging channels. On the other hand, it saves the read chip data to the cache space corresponding to the debugging channel, and then the external debugging tool reads the data from the cache space. This enables high-efficiency utilization of the cache, fully utilizes the higher access efficiency of cache data, improves the data transmission speed between the chip and the external debugging tool, and thus improves chip debugging efficiency.

[0097] Figure 6 This is a flowchart of yet another chip debugging method proposed according to an exemplary embodiment. For example... Figure 6 As shown, the chip debugging method includes the following steps:

[0098] Step S401: Obtain the debugging task. The implementation method is the same as in step S101, and will not be repeated here.

[0099] Step S402 involves dividing the debugging subtasks within the debugging task into subtasks based on their task types, thereby obtaining the debugging subtasks corresponding to the task types. This is the same implementation as step S102 and will not be repeated here.

[0100] Step S403: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be repeated here.

[0101] Step S404: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number. The implementation method is the same as that of step S104, and will not be repeated here.

[0102] Step S405: Process the debugging subtask of the debugging channel using the adjusted cache space to obtain the debugging result of the chip.

[0103] Specifically, step S405 includes:

[0104] Step b1: When the debugging subtask is a write task, write the data in the corresponding cache space to the chip memory according to the debugging subtask of the debugging channel;

[0105] Step b2: Obtain the data write status corresponding to each of the debugging subtasks, and feed back the data write status corresponding to each of the debugging subtasks to the external debugging tool.

[0106] The chip debugging method provided in this embodiment can improve the chip debugging efficiency by having multiple debugging channels run in parallel and writing the data in their corresponding cache spaces to the chip memory, since the data to be written to the chip memory for the debugging subtasks has been pre-cached in the corresponding cache space.

[0107] Figure 7 This is a flowchart of yet another chip debugging method proposed according to an exemplary embodiment. For example... Figure 7 As shown, the chip debugging method includes the following steps:

[0108] Step S501: Obtain the debugging task. The implementation method is the same as in step S101, and will not be repeated here.

[0109] Step S502 involves dividing the debugging subtasks within the debugging task into subtasks based on their task types, thereby obtaining the debugging subtasks corresponding to the task types. This is the same implementation as step S102 and will not be repeated here.

[0110] Step S503: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be repeated here.

[0111] Step S504: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number. This is the same implementation as step S104 and will not be described again here.

[0112] Step S505 involves processing the debug subtask of the debug channel using the adjusted cache space to obtain the chip's debug result. This is the same implementation as step S105 and will not be repeated here.

[0113] In an optional implementation, step S503 includes:

[0114] Step S5031: Determine the debugging channel corresponding to the task type of the debugging subtask;

[0115] Step S5032: When the number of debugging channels corresponding to the task type is 1, the debugging subtask is assigned to the debugging channel;

[0116] Step S5033: When the number of debugging channels corresponding to the task type is not 1, the debugging subtask is assigned to the corresponding debugging channel based on the data processing speed or priority configuration of the debugging channel.

[0117] For example, if the AXI bus conversion module has a faster data processing speed than the APB, AHB, and DAP bus conversion modules, then for debugging subtasks that can be executed by all four, the debugging subtasks will be allocated more to the AXI bus conversion module according to the data processing speed ratio of the four conversion modules, thus accelerating the processing speed of the debugging subtasks. Similarly, the other three conversion modules will also be allocated different amounts of debugging subtasks according to their different data processing speeds. Alternatively, for some custom special configurations, priority can be configured for different data conversion modules, with higher-priority debugging channels being allocated more debugging subtasks.

[0118] The chip debugging method provided in this embodiment first assigns debugging subtasks to corresponding debugging channels based on their task types. If the debugging channel corresponding to a task type is not 1, the debugging subtasks are further assigned to corresponding debugging channels based on the data processing speed or priority configuration of the debugging channels. Therefore, based on the parallel processing of multiple debugging channels, it is possible to enable debugging channels with faster data processing speeds or higher priority configurations to handle more debugging subtasks, thereby further improving the chip debugging efficiency.

[0119] In another optional implementation, during the process of processing the debug subtasks of the debug channel using the adjusted cache space, the method further includes:

[0120] When any of the debugging channels has completed all the assigned debugging subtasks in advance, the number of unprocessed debugging subtasks of the other debugging channels is obtained;

[0121] Based on the number of unprocessed debugging subtasks in each debugging channel, determine in descending order whether other debugging channels have the same task type as the currently idle debugging channel;

[0122] When the debugging channel has the same task type as the currently idle debugging channel, the unprocessed debugging subtasks in the debugging channel are dynamically assigned to the idle debugging channel for processing.

[0123] In this embodiment of the invention, by dynamically allocating unprocessed debug subtasks to idle debug channels corresponding to their task types, the task processing resources of each debug channel can be fully utilized to achieve efficient parallel processing of debug subtasks, thereby further improving the debugging efficiency of the chip.

[0124] Figure 8 This is a flowchart of yet another chip debugging method proposed according to an exemplary embodiment. For example... Figure 8 As shown, the chip debugging method includes the following steps:

[0125] Step S601: Obtain the debugging task. The implementation method is the same as in step S101, and will not be repeated here.

[0126] Step S602 involves dividing the debugging subtasks within the debugging task into subtasks based on their task types, thereby obtaining the debugging subtasks corresponding to the task types. This is the same implementation as step S102 and will not be repeated here.

[0127] Step S603: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be described again here.

[0128] Step S604: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number.

[0129] Step S605 involves processing the debug subtask of the debug channel using the adjusted cache space to obtain the chip's debug result. This is the same implementation as step S105 and will not be repeated here.

[0130] Specifically, step S604 includes:

[0131] Step 6041: Obtain the number of debugging subtasks corresponding to each debugging channel;

[0132] Step 6042: Calculate the ratio of the number of debugging subtasks among the various debugging channels;

[0133] Step 6043: Adjust the cache space size corresponding to the debugging channel according to the quantity ratio corresponding to the debugging channel.

[0134] The chip debugging method provided in this embodiment adjusts the cache space size corresponding to each debugging channel based on the ratio of the number of debugging subtasks allocated between debugging channels. Therefore, it enables highly efficient utilization of the cache.

[0135] Understandably, in this invention, cache space can be dynamically allocated according to the task size of the debugging subtask corresponding to each debugging channel; wherein, the debugging channels with more allocated debugging subtasks can be allocated more cache space according to the task size ratio, so as to make full use of the chip's cache space.

[0136] Figure 9 This is a flowchart of yet another chip debugging method proposed according to an exemplary embodiment. Further, as... Figure 9 As shown, the chip debugging method includes the following steps:

[0137] Step S701: Obtain the debugging task. This is the same implementation as step S101 and will not be repeated here.

[0138] Step S702: Based on the task type of the debugging subtasks in the debugging task, the task is divided into debugging subtasks corresponding to the task type. This is the same implementation as step S102 and will not be repeated here.

[0139] Step S703: Based on the task type of the debugging subtask, assign the debugging subtask to the corresponding debugging channel. This is the same implementation as step S103 and will not be repeated here.

[0140] Step S704: Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number. This is the same implementation as step S104 and will not be described again here.

[0141] Step S705: The chip is debugged according to the debug subtask of the debug channel, and the debug data during the debugging process is cached in the cache space corresponding to the debug channel to obtain the debug result of the chip; wherein, the debug data includes data written to the chip memory and / or data read from the chip memory. The implementation method is the same as that of step S205, and will not be described again here.

[0142] Step S706: When the cache space corresponding to the debugging channel meets the preset cache threshold condition, send cache status information to the external debugging tool so that the external debugging tool can read data from the cache space corresponding to the debugging channel or pause writing data to the cache space corresponding to the debugging channel.

[0143] The chip debugging method provided in this embodiment notifies the external debugging tool to read data from the cache space or pause writing data to the cache space when the cache space corresponding to the debugging channel meets the preset cache threshold condition, thereby avoiding data overflow in the cache space and causing chip debugging errors.

[0144] It should be noted that when the debugging subtask is a read task, the cache threshold condition is that the amount of data in the cache space reaches a preset cache overflow threshold; when the debugging subtask is a write task, the cache threshold condition is that the cache space is full.

[0145] For example, in a practical application scenario, step S706 above includes:

[0146] If the debugging subtask is a reading task, when the amount of data in the cache space corresponding to the debugging channel reaches a preset cache overflow threshold, cache status information is sent to the external debugging tool so that the external debugging tool can read data from the cache space corresponding to the debugging channel.

[0147] If the debugging subtask is a write task, then when the cache space corresponding to the debugging channel is full, cache status information is sent to the external debugging tool so that the external debugging tool can pause writing data to the cache space corresponding to the debugging channel.

[0148] Furthermore, after sending cache status information to an external debugging tool to cause the external debugging tool to pause writing data to the cache space corresponding to the debugging channel, the method further includes:

[0149] When the amount of data in the cache space of the debugging channel drops to a preset cache safety threshold, a rewrite message is sent to the external debugging tool so that the external debugging tool rewrites data to the cache space corresponding to the debugging channel.

[0150] Specifically, the method further includes:

[0151] Obtain the message transmission delay between the chip and the external debugging tool;

[0152] The cache security threshold is determined based on the message transmission delay and the data write speed of each of the debugging channels.

[0153] Understandably, when performing a write operation on the chip, the data waiting to be written to the chip's memory in the cache space is written in real time by an external debugging tool. Therefore, after the external debugging tool pauses writing data to the cache space corresponding to the debugging channel, the amount of data in the cache space gradually decreases as data is continuously written to the chip's memory, potentially even reaching an empty cache space, causing a write debugging interruption. Therefore, it is necessary to determine a cache safety threshold based on the message transmission latency between the external debugging tool and the chip, as well as the data write speed of each debugging channel. When the amount of data in the cache space drops to the cache safety threshold, the external debugging tool should be notified in advance to resume writing data to the cache space corresponding to the debugging channel, thus ensuring that the cache space is not empty. This allows each debugging channel to continuously write data from the cache space to the chip's memory, thereby improving debugging efficiency.

[0154] For ease of understanding, see Figure 10 and Figure 11 The chip debugging method of the present invention will be described below with two specific embodiments:

[0155] 1. Perform chip content reading and debugging:

[0156] Step S801: Receive the read command sent by the external debugging tool, and then execute step S802;

[0157] Step S802: Divide the debugging task according to the received read instruction to obtain debugging subtasks, and send the debugging subtasks to the corresponding debugging channels, and then execute step S803;

[0158] Step S803: According to the debugging subtasks of each debugging channel, read the data in the chip memory and save it to the cache space corresponding to the debugging channel, and then execute step S804;

[0159] Step S804: Determine whether the cache space has reached the preset overflow trigger threshold or whether the read task has been completed. If yes, proceed to step S805; otherwise, return to step S803.

[0160] Step S805: Notify the external debugging tool to read data from the cache space, and then execute step S806;

[0161] Step S806: After the external debugging tool finishes reading the data in the cache space, determine whether the entire read debugging operation is complete. If yes, the read instruction is complete and the debugging process of reading the chip content ends; otherwise, return to step S803.

[0162] 2. Perform debugging of the chip content writing:

[0163] Step S901: Receive the write command sent by the external debugging tool, and then execute step S902;

[0164] Step S902: Divide the debugging task into debugging subtasks according to the received write command; and send the debugging subtasks to the appropriate debugging channel, and then execute step S903;

[0165] Step S903: Based on the debugging subtasks of each debugging channel, write the data in the corresponding cache space into the chip memory, and then execute step S904;

[0166] Step S904: Determine whether the cache space is full or whether the write task is completed. If yes, proceed to step S905; otherwise, return to step S903.

[0167] Step S905: Notify the external debugging tool to stop writing data to the cache space, and then execute step S906;

[0168] Step S906: Determine whether the entire write debugging operation is complete. If yes, the write instruction is complete and the debugging process of writing chip content ends; otherwise, proceed to step S907.

[0169] Step S907: Based on the unfinished debugging subtasks of the debugging channel, write the data in the corresponding cache space into the chip memory, and then execute step S908;

[0170] Step S908: Determine whether the amount of remaining data in the cache space has dropped to the preset cache safety threshold. If yes, proceed to step S909; otherwise, return to step S907.

[0171] Step S909: Notify the external debugging tool to continue writing data to the cache space, and then return to step S901.

[0172] This embodiment also provides a chip debugging device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0173] This embodiment provides a chip debugging device, such as Figure 12 As shown, it includes:

[0174] Data receiving module 100 is used to acquire debugging tasks;

[0175] The task partitioning module 200 is used to partition tasks based on the task type of the debugging subtasks in the debugging task, and obtain the debugging subtasks corresponding to the task type.

[0176] The task allocation module 300 is used to allocate the debugging subtask to the corresponding debugging channel based on the task type of the debugging subtask;

[0177] The cache allocation module 400 is used to obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number;

[0178] The task processing module 500 is used to process the debugging subtasks of the debugging channel through the adjusted cache space to obtain the debugging results of the chip.

[0179] In some alternative embodiments, the task processing module 500 includes:

[0180] The task execution unit is used to debug the chip according to the debugging sub-task of the debugging channel, and cache the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip; wherein, the debugging data includes data written to the chip memory and / or data read from the chip memory.

[0181] In some optional implementations, the task execution unit includes:

[0182] A chip reading subunit is used to read data from the chip memory according to the debugging subtask of the debugging channel when the debugging subtask is a reading task;

[0183] The data caching subunit is used to cache the read data into the cache space corresponding to the debugging channel;

[0184] The first feedback subunit is used to send a read message to an external debugging tool to read data from the cache space corresponding to the debugging channel if the debugging subtask corresponding to the debugging channel is completed.

[0185] In some optional implementations, the task execution unit further includes:

[0186] The chip write subunit is used to write the data in the corresponding cache space to the chip memory according to the debug subtask of the debug channel when the debug subtask is a write task;

[0187] The second feedback subunit is used to obtain the data writing status corresponding to each of the debugging subtasks and to feed back the data writing status corresponding to each of the debugging subtasks to the external debugging tool.

[0188] In some alternative implementations, the task allocation module 300 includes:

[0189] A channel selection unit is used to determine the debugging channel corresponding to the task type of the debugging subtask.

[0190] The first allocation unit is used to allocate the debugging subtask to the debugging channel when the number of debugging channels corresponding to the task type is 1.

[0191] The second allocation unit is used to allocate the debugging subtask to the corresponding debugging channel based on the data processing speed or priority configuration of the debugging channel when the number of debugging channels corresponding to the task type is not 1.

[0192] In some alternative implementations, the cache allocation module 400 includes:

[0193] The task quantity comparison unit is used to calculate the ratio of the number of debugging subtasks among the various debugging channels;

[0194] The cache adjustment unit is used to adjust the cache space size corresponding to the debug channel according to the quantity ratio corresponding to the debug channel.

[0195] In some alternative embodiments, the apparatus further includes:

[0196] The cache reminder module is used to send cache status information to an external debugging tool when the cache space corresponding to the debugging channel meets the preset cache threshold conditions, so that the external debugging tool can read data from the cache space corresponding to the debugging channel or pause writing data to the cache space corresponding to the debugging channel.

[0197] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0198] In this embodiment, the chip debugging device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0199] This invention also provides a chip debugging system, the system comprising:

[0200] External debugging tools;

[0201] The chip is debugged by executing the chip debugging method of any of the above embodiments.

[0202] Please see Figure 13 , Figure 13 This is a schematic diagram of the structure of a chip provided in an optional embodiment of the present invention, such as... Figure 13 As shown, the chip includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the chip, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interface). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple chips can be connected, each device providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 13 Take a processor 10 as an example.

[0203] Processor 10 may be a central processing unit (i.e., the central module mentioned above), a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GPRS), or any combination thereof.

[0204] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0205] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the chip. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the chip via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0206] Memory 20 may include volatile memory, such as random access memory; memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; memory 604 may also include combinations of the above types of memory.

[0207] The chip also includes a communication interface 30 for communicating with other devices or communication networks.

[0208] The present invention also provides a computer-readable storage medium in which the methods described herein can be implemented in hardware, firmware, or as recordable on a storage medium, or as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium may be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the embodiments described above.

[0209] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A chip debugging method, characterized in that, The method includes: Obtain debugging tasks; Based on the task type of the debugging subtask in the debugging task, the task is divided to obtain the debugging subtask corresponding to the task type; Based on the task type of the debugging subtask, the debugging subtask is assigned to the corresponding debugging channel; Obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number; The debug subtasks of the debug channel are processed using the adjusted cache space to obtain the debug results of the chip.

2. The method according to claim 1, characterized in that, The process of processing the debugging subtasks of the debugging channel using the adjusted cache space to obtain the chip debugging results includes: The chip is debugged according to the debug subtask of the debug channel, and the debug data during the debugging process is cached in the cache space corresponding to the debug channel to obtain the debug result of the chip; wherein, the debug data includes data written to the chip memory and / or data read from the chip memory.

3. The method according to claim 2, characterized in that, The step of debugging the chip according to the debugging subtask of the debugging channel, and caching the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip, includes: When the debugging subtask is a read task, the data in the chip memory is read according to the debugging subtask of the debugging channel; The read data is cached in the cache space corresponding to the debugging channel; If the debugging subtask corresponding to the debugging channel is completed, a read message is sent to the external debugging tool to read data from the cache space corresponding to the debugging channel.

4. The method according to claim 2, characterized in that, The step of debugging the chip according to the debugging subtask of the debugging channel, and caching the debugging data during the debugging process to the cache space corresponding to the debugging channel to obtain the debugging result of the chip, further includes: When the debugging subtask is a write task, the data in the corresponding cache space is written to the chip memory according to the debugging subtask of the debugging channel; Obtain the data write status corresponding to each of the debugging subtasks, and feed back the data write status corresponding to each of the debugging subtasks to the external debugging tool.

5. The method according to claim 1, characterized in that, The process of assigning the debugging subtask to the corresponding debugging channel based on the task type of the debugging subtask includes: Determine the debugging channel corresponding to the task type of the debugging subtask; When the number of debugging channels corresponding to the task type is 1, the debugging subtask is assigned to the debugging channel; When the number of debugging channels corresponding to the task type is not 1, the debugging subtask is assigned to the corresponding debugging channel based on the data processing speed or priority configuration of the debugging channel.

6. The method according to claim 1, characterized in that, The adjustment of the cache space corresponding to the debugging channel based on the quantity includes: Calculate the ratio of the number of debugging subtasks among the various debugging channels; Adjust the cache size corresponding to the debugging channel based on the ratio of the number of channels.

7. The method according to claim 2, characterized in that, The method further includes: When the cache space corresponding to the debugging channel meets the preset cache threshold condition, cache status information is sent to the external debugging tool so that the external debugging tool can read data from the cache space corresponding to the debugging channel or pause writing data to the cache space corresponding to the debugging channel.

8. A chip debugging device, characterized in that, The device includes: The data receiving module is used to acquire debugging tasks; The task partitioning module is used to partition tasks based on the task type of the debugging subtasks in the debugging task, and obtain the debugging subtasks corresponding to the task type. The task allocation module is used to allocate the debugging subtask to the corresponding debugging channel based on the task type of the debugging subtask; A cache allocation module is used to obtain the number of debugging subtasks corresponding to each debugging channel, and adjust the cache space corresponding to the debugging channel based on the number; The task processing module is used to process the debugging subtasks of the debugging channel through the adjusted cache space to obtain the debugging results of the chip.

9. A chip debugging system, characterized in that, The system includes: External debugging tools; The chip is debugged using the chip debugging method as described in any one of claims 1 to 7.

10. A chip, characterized in that, include: A memory and a processor are interconnected, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip debugging method of any one of claims 1 to 7.

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