Method for controlling asynchronous first-in-first-out memory and corresponding data transfer system

Abstract

A control method of an asynchronous first-in-first-out (FIFO) memory is used to control the operation of the asynchronous FIFO memory, including: determining a current depth of the asynchronous FIFO memory according to at least one of a frequency ratio, a burst length and a continuous transmission length, wherein the frequency ratio is a ratio of a frequency of a first frequency signal used by a master device to a frequency of a second frequency signal used by a slave device; configuring one or more entries of the asynchronous FIFO memory used according to the current depth; and controlling a plurality of FIFO frequency signals provided to the asynchronous FIFO memory according to the current depth, wherein one FIFO frequency signal corresponds to one entry, and one or more FIFO frequency signals corresponding to one or more entries not configured according to the current depth are not enabled.

Description

Technical Field

[0001] This invention application relates to a control method for asynchronous first-in-first-out (FIFO) memory and a corresponding data transmission system, so as to realize dynamic adjustment of the depth of asynchronous FIFO memory. Background Technology

[0002] Asynchronous First-In-First-Out (FIFO) memory is widely used for data transfer across clock domains. To address the metastability issue when synchronizing read and write pointers across clock domains in an asynchronous FIFO, the binary-encoded read and write pointers are typically converted to Gray code before sampling. However, this operation requires limiting the FIFO depth to a power of 2, which significantly restricts its application, wastes circuit space, and increases power consumption.

[0003] Therefore, a new depth adjustment method is needed, which modifies the FIFO pointer to make the FIFO depth flexibly set as needed, without being limited to a power of 2, and realizes the dynamic adjustment of asynchronous FIFO depth. Summary of the Invention

[0004] One objective of this invention is to provide a control method for asynchronous first-in-first-out memory to achieve dynamic adjustment of its depth and dynamic adjustment of the frequency signals of each input, thereby effectively reducing power consumption while ensuring continuous data transmission.

[0005] According to an embodiment of the present invention, a control method for an asynchronous first-in-first-out (FIFO) memory is provided for controlling the operation of an asynchronous FIFO memory, wherein the asynchronous FIFO memory is coupled between a master device and a slave device for buffering data written by the master device. The control method includes: determining a current depth of the asynchronous FIFO memory based on at least one of a frequency ratio, a burst length, and a continuous transmission length, wherein the frequency ratio is a ratio of a frequency of a first frequency signal used by the master device to a frequency of a second frequency signal used by the slave device; configuring one or more entries of the asynchronous FIFO memory to be used based on the current depth, wherein the asynchronous FIFO memory includes multiple entries, and the current depth is less than or equal to the total number of entries; and controlling multiple FIFO frequency signals provided to the asynchronous FIFO memory based on the current depth, wherein a FIFO frequency signal corresponds to an entry, and one or more FIFO frequency signals corresponding to one or more entries that are not configured according to the current depth are not enabled.

[0006] According to another embodiment of the present invention, a data transmission system includes a master device and an asynchronous first-in-first-out (FIFO) memory. The asynchronous FIFO memory is coupled between the master device and a slave device and includes multiple entries for buffering data written by the master device. At least one of the master device and the asynchronous FIFO memory determines a current depth of the asynchronous FIFO memory based on at least one of a frequency ratio, a burst length, and a continuous transmission length, wherein the current depth is less than or equal to the total number of entries, and the frequency ratio is a ratio of a frequency of a first frequency signal used by the master device to a frequency of a second frequency signal used by the slave device. The asynchronous FIFO memory configures one or more entries to be used according to the current depth and controls multiple FIFO frequency signals according to the current depth, wherein one FIFO frequency signal corresponds to one entry, and one or more FIFO frequency signals corresponding to one or more entries that are not configured according to the current depth are not enabled. Attached Figure Description

[0007] Figure 1 This describes a data transmission system according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram illustrating an asynchronous FIFO memory according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram illustrating an asynchronous FIFO memory according to an embodiment of the present invention.

[0010] Figure 4 This is a flowchart illustrating a control method for an asynchronous FIFO memory according to an embodiment of the present invention.

[0011] Figure 5 This is a schematic diagram showing a portion of the logic circuitry inside an asynchronous FIFO memory according to an embodiment of the present invention.

[0012] Figure 6 This is a schematic diagram showing another part of the logic circuit inside the asynchronous FIFO memory according to an embodiment of the present invention.

[0013] Figure 7 This is a schematic diagram of an isolated clock gating circuit according to an embodiment of the present invention.

[0014] Figure 8 This is a schematic diagram showing another part of the logic circuit inside the asynchronous FIFO memory according to an embodiment of the present invention.

[0015] Symbol explanation:

[0016] 100: Data transmission system

[0017] 110: Main unit

[0018] 120, 220, Async_FIFO: Asynchronous First-In-First-Out Memory Memory

[0019] 130: From the device

[0020] 505, 510, 515: Multitasking

[0021] 506, 507: Adders

[0022] 508, 509, 604, 605: Processing circuits

[0023] 601, 801: Synchronization circuit

[0024] 602, 603: Subtractors

[0025] 607, 608, 807, 808: Comparators

[0026] 615, 815: Binary code to Gray code circuit

[0027] 625: Gray code to binary code circuit

[0028] 700: Isolated clock gating circuit

[0029] Clk_en: Frequency enable signal

[0030] Clk_FIFO, Clk_FIFO': FIFO frequency signal

[0031] Data[0]~Data[7], payload_in, payload_out: Data

[0032] depth_select: Depth selection signal

[0033] Entry[0]-Entry[7]: Entry

[0034] in_accept: Input accept signal

[0035] in_valid: Valid input data signal

[0036] input_back_to_back_length: Continuous transmission length

[0037] input_burst_length: Burst length

[0038] input_clk_ratio: Frequency ratio

[0039] min_fifo_depth: Minimum depth

[0040] out_accept: Outputs the accepted signal

[0041] out_valid: Valid output data signal

[0042] pop_empty: Empty index

[0043] pop_gray_p, pop_gray_r: Auxiliary read pointers for Gray code encoding.

[0044] pop_gray_sync_b: Gray code-encoded synchronous read pointer

[0045] pop_pt: Read pointer

[0046] pop_pt_p, pop_pt_r: Auxiliary read pointers

[0047] pop_pt_p_temp: Temporary read pointer

[0048] pop_req_n, push_req_n: Selection signals

[0049] pop_sync_b: Synchronous read pointer

[0050] push_full: Full target

[0051] push_gray_p, push_gray_r: Auxiliary write pointers for Gray code encoding.

[0052] push_gray_sync_b: Gray code-encoded synchronous write pointer

[0053] push_pt: Write pointer

[0054] push_pt_p, push_pt_r: Auxiliary write pointers

[0055] push_pt_p_temp: Temporary write pointer

[0056] push_sync_b: Synchronous write pointer Detailed Implementation

[0057] Figure 1This describes a data transmission system according to an embodiment of the present invention. The data transmission system 100 may include a master device 110, an asynchronous first-in-first-out (AFIFO) memory 120, and a slave device 130. The AFIFO memory 120 is coupled between the master device 110 and the slave device 130 to buffer data written by the master device 110, and the slave device 130 can read data buffered by the asynchronous FIFO memory 120.

[0058] The asynchronous FIFO memory 120 contains multiple entries, each of which is an individually addressable storage location. That is, each entry corresponds to a storage space, and each entry can be accessed by both the clock domain of the master device 110 and the clock domain of the slave device 130. The total number of entries contained in the asynchronous FIFO memory 120 is the depth (or maximum depth) of the asynchronous FIFO memory 120. For example, the asynchronous FIFO memory 120 may contain 8 entries, therefore its depth is 8, meaning it can contain 8 addressable storage spaces used to cache data written by the master device 110.

[0059] When the master device 110 needs to perform a write operation on the asynchronous FIFO memory 120, the master device 110 can push the data payload_in to the transmission interface between the master device 110 and the asynchronous FIFO memory 120, for example, a bus (or bus) coupled between the master device 110 and the asynchronous FIFO memory 120, and issue a valid input data signal in_valid to the asynchronous FIFO memory 120. At this time, the valid input data signal in_valid will be set to a predetermined value, for example, the value of the valid input data signal in_valid is equal to 1, to notify the asynchronous FIFO memory 120 that the data on the bus is currently valid data. If the asynchronous FIFO memory 120 is not yet full, it will reply with an input accept signal in_accept to the master device 110, where the input accept signal in_accept will be set to a predetermined value, for example, the value of the input accept signal in_accept is equal to 1, and the data payload_in will be received from the bus.

[0060] Furthermore, the asynchronous FIFO memory 120 can determine whether the current FIFO state is empty. If it is determined that the FIFO is not empty, the data payload_out can be pushed to the transmission interface between the slave device 130 and the asynchronous FIFO memory 120, for example, a bus coupled between the slave device 130 and the asynchronous FIFO memory 120, and a valid output data signal out_valid can be issued to the slave device 130. At this time, the valid output data signal out_valid will be set to a predetermined value, for example, the value of the valid output data signal out_valid is equal to 1, to notify the slave device 130 that the data on the bus is valid. When a read operation needs to be performed on the asynchronous FIFO memory 120, the slave device 130 will reply with an output accept signal out_accept to the asynchronous FIFO memory 120, wherein the output accept signal out_accept will be set to a predetermined value, for example, the value of the output accept signal out_accept is equal to 1, and the data payload_out will be extracted from the bus.

[0061] Figure 2 This is a schematic diagram illustrating an asynchronous FIFO memory with a depth of 8 according to an embodiment of the present invention. The asynchronous FIFO memory 120 / 220 uses a write pointer `push_pt` to indicate the next address that can be written to, and a read pointer `pop_pt` to indicate the next address that can be read from. Each time data is written, the asynchronous FIFO memory 120 / 220 automatically increments the write pointer `push_pt` by 1. Similarly, each time data is read, the asynchronous FIFO memory 120 / 220 automatically increments the read pointer `pop_pt` by 1. Figure 2 In the example, the asynchronous FIFO memory 220 has a total of 8 entries, and therefore a depth of 8, but currently only 6 of them are configured, for example, entries Entry[0]-Entry[5]. Therefore, the currently unconfigured entries Entry[6]-Entry[7] will not be written to.

[0062] like Figure 2As shown, assuming that data Data[0] to Data[7] have been sequentially written to asynchronous FIFO memory 220, since only 6 entries are currently configured, i.e., the current depth is set to 6, after data Data[0] is read out, data Data[6] will be written to entry Entry[0] instead of entry Entry[6]. Similarly, after data Data[1] is read out, data Data[7] will be written to entry Entry[1] instead of entry Entry[7]. After the latest data Data[7] is written to entry Entry[1], the write pointer push_pt will point to entry Entry[2], and after data Data[1] is read out, the read pointer pop_pt will point to entry Entry[2]. Figure 2 In the example, the asynchronous FIFO memory 220 is currently full.

[0063] According to an embodiment of the present invention, at least one of the master device 110 and the asynchronous FIFO memory 120 / 220 can dynamically determine the current depth of the asynchronous FIFO memory 120 / 220 based on at least one of a frequency ratio, a burst length, and a continuous transmission length. The frequency ratio is the ratio of a frequency of a first frequency signal used by the master device 110 to a frequency of a second frequency signal used by the slave device 130. For example, the frequency ratio between the master device 110 and the slave device 130 can be 4:1, 3:1, 2:1, 1:1, 1:2, 1:3, 1:4, etc. The burst length is the number of data entries that the master device 110 can send in response to a write command. Assuming the master device 110 sets the burst length to 4 and each data entry has a bit width of 8 bits, then after issuing a write command, the master device 110 can continuously send four 8-bit data entries in response to the write command. The continuous transmission length, also known as the back-to-back length, refers to the number of write commands that the master device 110 can issue one after another or consecutively. Generally, the continuous transmission length can be predicted or statistically determined from the capabilities of the master device 110. Assuming that the master device 110 has a high data rate or outstanding capabilities, it can be predicted that the continuous transmission length may exceed a critical value, or the continuous transmission length of the master device 110 can be obtained through statistical analysis over a period of time. Here, outstanding capability refers to the ability of the master device 110 to immediately issue the next command before the data has been completely transmitted after issuing the previous command.

[0064] As described above, the master device 110 or the asynchronous FIFO memory 120 / 220 can dynamically determine the current depth of the asynchronous FIFO memory 120 / 220 based on at least one of a frequency ratio, a burst length, and a continuous transmission length, wherein the current depth is less than or equal to the total number of entries contained in the asynchronous FIFO memory 120 / 220. According to one embodiment of the invention, if the master device 110 or the asynchronous FIFO memory 120 / 220 determines, based on the frequency ratio, that the frequency difference between the first frequency signal and the second frequency signal is large, the master device 110 or the asynchronous FIFO memory 120 / 220 can select a smaller current depth. Therefore, the larger the frequency difference shown by the frequency ratio, the smaller the determined current depth can be. According to another embodiment of the invention, if the master device 110 or the asynchronous FIFO memory 120 / 220 determines that the burst length is long, the master device 110 or the asynchronous FIFO memory 120 / 220 can select a larger current depth. Therefore, the longer the set burst length, the larger the determined current depth can be. According to another embodiment of the present invention, if the master device 110 or the asynchronous FIFO memory 120 / 220 determines that the continuous transmission length is long, the master device 110 or the asynchronous FIFO memory 120 / 220 can select a larger current depth. Therefore, the longer the continuous transmission length, the larger the determined current depth can be. According to one embodiment of the present invention, the master device 110 or the asynchronous FIFO memory 120 / 220 can store or have a built-in lookup table, which can record the correspondence between the depth of the asynchronous FIFO memory and parameters such as frequency ratio, burst length, and continuous transmission length. The master device 110 or the asynchronous FIFO memory 120 / 220 can refer to this lookup table to dynamically determine the current depth based on at least one of the frequency ratio, burst length, and continuous transmission length.

[0065] Figure 3This is a schematic diagram of an asynchronous FIFO memory according to an embodiment of the present invention. In addition to the aforementioned valid input data signal `in_valid`, input acceptance signal `in_accept`, valid output data signal `out_valid`, output acceptance signal `out_accept`, and input and output data `payload_in` and `payload_out`, the asynchronous FIFO memory `Async_FIFO` may further receive a depth selection signal `depth_select`. In one embodiment of the present invention, the depth selection signal `depth_select` may be a signal issued by the master device and carries information about the frequency ratio, burst length, or continuous transmission length. The asynchronous FIFO memory `Async_FIFO` can dynamically determine the current depth based on at least one of the frequency ratio, burst length, and continuous transmission length. In another embodiment of the present invention, the master device can dynamically determine the current depth of the asynchronous FIFO memory `Async_FIFO` based on at least one of the frequency ratio, burst length, and continuous transmission length, and transmit this information to the asynchronous FIFO memory `Async_FIFO` via the depth selection signal `depth_select`.

[0066] After determining or obtaining the current depth, the asynchronous FIFO memory can configure the number of currently usable entries based on the current depth, and correspondingly control multiple FIFO frequency signals based on the current depth, where each FIFO frequency signal corresponds to an entry of the asynchronous FIFO memory. In embodiments of the present invention, one or more FIFO frequency signals corresponding to one or more entries that are not configured based on the current depth may be disabled, thereby effectively reducing the power consumption of the asynchronous FIFO memory.

[0067] It should be noted that, Figure 3 This is a simplified schematic diagram of an asynchronous FIFO memory, showing only a portion of its input / output signals. Those skilled in the art will understand that asynchronous FIFO memory includes other input / output signals not shown.

[0068] Figure 4 This is a flowchart illustrating a control method for an asynchronous FIFO memory according to an embodiment of the present invention. The control method for the asynchronous FIFO memory proposed in this invention includes the following steps:

[0069] Step S402: Determine the current depth of the asynchronous FIFO memory based on at least one of a frequency ratio, a burst length, and a continuous transmission length.

[0070] Step S404: Configure one or more entries that will be used in the asynchronous FIFO memory based on the current depth.

[0071] Step S406: Provide the FIFO frequency signal to the asynchronous FIFO memory according to the current depth control.

[0072] In embodiments of the present invention, the selection of the current depth need not be limited to a power of 2 as in the prior art. That is, in step S402, the current depth can be set to any positive integer between 2 and N, where N is the maximum depth of the asynchronous FIFO memory.

[0073] According to one embodiment of the present invention, the read pointer pop_pt and write pointer push_pt of the asynchronous FIFO memory can be represented by multiple characters. The bit width of the read pointer pop_pt and write pointer push_pt can be set to the bit width required to represent the maximum depth of the asynchronous FIFO memory. To determine the current empty / full state of the FIFO, in this embodiment, an additional flag bit is added to the read pointer pop_pt and write pointer push_pt, indicating an auxiliary read pointer pop_pt_p and an auxiliary write pointer push_pt_p. More specifically, assuming the depth or maximum depth of the asynchronous FIFO memory is 8, since the value 8 requires 3 bits when represented in binary, the bit width required to represent the maximum depth of the asynchronous FIFO memory is 3. In this embodiment, based on the bit width required to represent the maximum depth of the asynchronous FIFO memory, the bit width of the read pointer pop_pt and write pointer push_pt of the asynchronous FIFO memory can be set to 3.

[0074] Furthermore, in embodiments of the present invention, based on the bit width required to represent the maximum depth of the asynchronous FIFO memory, an additional bit width can be added to the auxiliary read pointer pop_pt_p and the auxiliary write pointer push_pt_p. That is, when the maximum depth of the asynchronous FIFO memory requires 3 bits to represent, the bit width of the auxiliary read pointer pop_pt_p and the auxiliary write pointer push_pt_p can be set to (3+1)=4. With this setting, even if the current depth is set to a value other than a power of 2, the current empty / full state of the FIFO can be effectively determined using the auxiliary read pointer pop_pt_p and the auxiliary write pointer push_pt_p.

[0075] As described above, asynchronous FIFO memory updates the write pointer `push_pt` in response to a write operation from the master device and the read pointer `pop_pt` in response to a read operation from the slave device. The update operations for the read pointer `pop_pt` and the write pointer `push_pt` will be described below.

[0076] Figure 5This is a schematic diagram showing a portion of the internal logic circuitry of an asynchronous FIFO memory according to an embodiment of the present invention, used to illustrate the operations of updating the write pointer `push_pt` and updating the read pointer `pop_pt`. In this embodiment, the settings of three parameters—frequency ratio `input_clk_ratio`, burst length `input_burst_length`, and continuous transfer length `input_back_to_back_length`—can be input to the multiplexer 505. The multiplexer 505 can use the output of one of these parameters as a reference for determining the current depth of the asynchronous FIFO memory. For example, the multiplexer 505 can use the output of the parameter that has been changed (i.e., differs from the previously set value) as a reference for determining the current depth of the asynchronous FIFO memory. In this embodiment, the determined current depth can be considered as the minimum depth of the asynchronous FIFO memory, `min_fifo_depth`.

[0077] In addition to the aforementioned auxiliary write pointer push_pt_p and auxiliary read pointer pop_pt_p, the asynchronous FIFO memory will also generate another auxiliary write pointer push_pt_r and another auxiliary read pointer pop_pt_r.

[0078] Adder 506 increments the value of another auxiliary write pointer, `push_pt_r`, by 1 (marked as 1'b1) and outputs the result. Adder 507 increments the value of another auxiliary read pointer, `pop_pt_r`, by 1 (marked as 1'b1) and outputs the result. The other auxiliary write pointer, `push_pt_r`, is a delayed version of the aforementioned auxiliary write pointer, `push_pt_p`, and their changes differ by one frequency cycle. That is, when the write pointer value changes, the value of the aforementioned auxiliary write pointer, `push_pt_p`, changes first, and then the value of the other auxiliary write pointer, `push_pt_r`, changes in the next frequency cycle. Similarly, the other auxiliary read pointer, `pop_pt_r`, is a delayed version of the aforementioned auxiliary read pointer, `pop_pt_p`, and their changes differ by one frequency cycle. When the read pointer value changes, the value of the aforementioned auxiliary read pointer, `pop_pt_p`, changes first, and then the value of the other auxiliary read pointer, `pop_pt_r`, changes in the next frequency cycle.

[0079] When data is written to the asynchronous FIFO memory, the selection signal push_req_n is set to another predetermined value, for example, push_req_n equals 0. In this case, the multiplexer 510 selects to output the auxiliary write pointer push_pt_r whose bit value is incremented by 1 as the temporary write pointer push_pt_p_temp. The selection signal push_req_n is the result of the logical AND operation between the input accept signal in_accept and the valid input data signal in_valid, and then the NOT operation is performed, i.e., push_req_n = !(in_accept&in_valid). On the other hand, when the selection signal push_req_n is not set to another predetermined value, the multiplexer 510 selects to output the auxiliary write pointer push_pt_r whose bit value is not incremented by 1 as the temporary write pointer push_pt_p_temp.

[0080] Similarly, when data is read, the selection signal pop_req_n is set to another predetermined value, for example, if the value of pop_req_n is equal to 0. In this case, the multiplexer 515 selects to output the auxiliary read pointer pop_pt_r whose bit value has been incremented by 1 as the temporary read pointer pop_pt_p_temp. Here, the selection signal pop_req_n is the inverted result of the logical AND operation between the output accept signal out_accept and the valid output data signal out_valid, that is, pop_req_n = !(out_accept&out_valid). On the other hand, when the selection signal pop_req_n is not set to another predetermined value, the multiplexer 515 selects to output the auxiliary read pointer pop_pt_r whose bit value has not been incremented by 1 as the temporary read pointer pop_pt_p_temp.

[0081] Processing circuit 509 receives a temporary write pointer `push_pt_p_temp`, a temporary read pointer `pop_pt_p_temp`, and the value of twice the minimum depth `min_fifo_depth` (denoted as `min_fifo_depth*2`). It then compares the values ​​of the temporary write pointer `push_pt_p_temp` and the temporary read pointer `pop_pt_p_temp` with the value of twice the minimum depth `min_fifo_depth`. If the current value of the temporary write pointer `push_pt_p_temp` is equal to twice the minimum depth `min_fifo_depth`, processing circuit 509 resets the auxiliary write pointer `push_pt_p` to 0 and outputs it. If the current value of the temporary write pointer `push_pt_p_temp` is not equal to twice the minimum depth `min_fifo_depth`, processing circuit 509 outputs the temporary write pointer `push_pt_p_temp` as the auxiliary write pointer `push_pt_p`.

[0082] Similarly, if the value corresponding to the temporary read pointer pop_pt_p_temp is equal to twice the minimum depth min_fifo_depth, then the processing circuit 509 resets the auxiliary read pointer pop_pt_p to 0 and outputs it. If the value corresponding to the temporary read pointer pop_pt_p_temp is not equal to twice the minimum depth min_fifo_depth, then the processing circuit 509 outputs the temporary read pointer pop_pt_p_temp as the auxiliary read pointer pop_pt_p.

[0083] If the values ​​of the auxiliary write pointer push_pt_p and the auxiliary read pointer pop_pt_p change, the values ​​of the other auxiliary write pointer push_pt_r and the other auxiliary read pointer pop_pt_r will be changed accordingly in the next frequency cycle. The processing circuit 508 receives the values ​​of the auxiliary write pointer push_pt_r, the auxiliary read pointer pop_pt_r, and the minimum depth min_fifo_depth, and compares the values ​​of the auxiliary write pointer push_pt_r and the auxiliary read pointer pop_pt_r with the currently set minimum depth min_fifo_depth. If the current value of the auxiliary write pointer push_pt_r is less than the minimum depth min_fifo_depth, the processing circuit 508 discards the most significant bit (MSB) of the auxiliary write pointer push_pt_r and outputs it as the write pointer push_pt. If the value corresponding to the auxiliary write pointer push_pt_r is not less than the value of the minimum depth min_fifo_depth, then the processing circuit 509 will subtract the value of the minimum depth min_fifo_depth from the value corresponding to the auxiliary write pointer push_pt_r, discard the most significant bit, and output the result as the write pointer push_pt.

[0084] Similarly, if the current value of the auxiliary read pointer pop_pt_r is less than the minimum depth min_fifo_depth, the processing circuit 508 discards the most significant bit of the auxiliary read pointer pop_pt_r and outputs it as the read pointer pop_pt. If the current value of the auxiliary read pointer pop_pt_r is not less than the minimum depth min_fifo_depth, the processing circuit 508 subtracts the minimum depth min_fifo_depth from the current value of the auxiliary read pointer pop_pt_r, discards the most significant bit of the result, and outputs it as the read pointer pop_pt.

[0085] Figure 6This is a schematic diagram showing another part of the logic circuit inside the asynchronous FIFO memory according to an embodiment of the present invention, used to illustrate the operation of effectively determining the current empty / full state of the FIFO using an auxiliary read pointer pop_pt_p and an auxiliary write pointer push_pt_p. The binary-to-Gray code circuit 615 converts the binary-encoded auxiliary read pointer pop_pt_p into a Gray code-encoded auxiliary read pointer pop_gray_p, and converts the binary-encoded auxiliary write pointer push_pt_p into a Gray code-encoded auxiliary write pointer push_gray_p. The synchronization circuit 601 is used to resample the Gray code-encoded auxiliary read pointer pop_gray_p at the frequency of the write pointer signal to generate a Gray code-encoded synchronous read pointer pop_gray_sync_b, and to resample the Gray code-encoded auxiliary write pointer push_gray_p at the frequency of the read pointer signal to generate a Gray code-encoded synchronous write pointer push_gray_sync_b. The Gray code to binary code circuit 625 converts the resampled read / write pointers from Gray code to binary code, generating a synchronized read pointer pop_sync_b and a synchronized write pointer push_sync_b.

[0086] After this operation, the synchronous read pointer `pop_sync_b` and the auxiliary write pointer `push_pt_r` will be in the same clock domain. Subtractor 602 subtracts the value of the synchronous read pointer `pop_sync_b` from the value of the auxiliary write pointer `push_pt_r` and outputs the result. Subtractor 603 subtracts the value of the auxiliary read pointer `pop_pt_r` from the value of the synchronous write pointer `push_sync_b` and outputs the result.

[0087] Processing circuit 604 receives the output of subtractor 602 and twice the minimum depth (min_fifo_depth), and uses this value to take the absolute value of the output of subtractor 602. For example, if the result of subtracting the value of synchronous read pointer (pop_sync_b) from the value of auxiliary write pointer (push_pt_r) is a positive integer, processing circuit 604 directly outputs the result. If the result of subtracting the value of synchronous read pointer (pop_sync_b) from the value of auxiliary write pointer (push_pt_r) is negative, processing circuit 604 takes the absolute value of the result and outputs it. For example, processing circuit 604 can subtract the difference between synchronous read pointer (pop_sync_b) and auxiliary write pointer (push_pt_r) from twice the minimum depth (min_fifo_depth) and then output the result.

[0088] Similarly, processing circuit 605 receives the output of subtractor 603 and twice the minimum depth (min_fifo_depth), and uses this value to take the absolute value of the output of subtractor 603. For example, if the result of subtracting the value of auxiliary read pointer (pop_pt_r) from the value of synchronous write pointer (push_sync_b) is a positive integer, processing circuit 605 directly outputs the result. If the result of subtracting the value of auxiliary read pointer (pop_pt_r) from the value of synchronous write pointer (push_sync_b) is negative, processing circuit 605 takes the absolute value of the result and outputs it. For example, processing circuit 605 can subtract the difference between auxiliary read pointer (pop_pt_r) and synchronous write pointer (push_sync_b) from twice the minimum depth (min_fifo_depth) and then output the result.

[0089] Comparator 607 receives the value of minimum depth min_fifo_depth and compares it with the output of processing circuit 604 to generate a full index push_full. If the output of processing circuit 604 is equal to the value of minimum depth min_fifo_depth, the full index push_full is set to a predetermined value (e.g., push_full is set to 1). If the output of processing circuit 604 is not equal to the value of minimum depth min_fifo_depth, the full index push_full is not set to a predetermined value (e.g., push_full is set to 0).

[0090] Comparator 608 receives the value 0 and compares it with the output of processing circuit 605 to generate an empty index pop_empty. If the output of processing circuit 605 is equal to the value 0, the empty index pop_empty is set to a predetermined value (e.g., the empty index pop_empty is set to 1). If the output of processing circuit 605 is not equal to the value 0, the empty index pop_empty is not set to a predetermined value (e.g., the empty index pop_empty is set to 0).

[0091] Therefore, according to one embodiment of the present invention, when the absolute value of the difference between a value corresponding to the write pointer (e.g., the auxiliary write pointer push_pt_r) and a value corresponding to the read pointer (e.g., the synchronous read pointer pop_sync_b) is equal to the current depth, the asynchronous FIFO memory can set the full pointer push_full to a predetermined value, and when the difference between a value corresponding to the write pointer (e.g., the synchronous write pointer push_sync_b) and a value corresponding to the read pointer (e.g., the auxiliary read pointer pop_pt_r) is 0, the asynchronous FIFO memory can set the empty pointer pop_empty to a predetermined value.

[0092] In an embodiment of the present invention, Figure 6 The logic circuit shown is applicable to various current depth settings. That is, regardless of whether the current depth (which can be considered as the minimum depth of asynchronous FIFO memory, min_fifo_depth) is set to a power of 2, it can be used... Figure 6 The logic circuit shown generates the correct full pointer push_full and empty pointer pop_empty.

[0093] According to another embodiment of the present invention, when the current depth is set to a power of 2, the logic circuit for generating the full pointer push_full and the null pointer pop_empty can be further simplified by adding an extra flag bit to the read pointer pop_pt and the write pointer push_pt, which becomes an auxiliary read pointer pop_pt_r and an auxiliary write pointer push_pt_r.

[0094] Figure 8 This is a schematic diagram showing another part of the logic circuit inside the asynchronous FIFO memory according to an embodiment of the present invention, used to illustrate the operation of effectively determining the current empty / full state of the FIFO using auxiliary read pointers pop_pt_r, pop_pt_p and auxiliary write pointers push_pt_r, push_pt_p when the current depth is set to a power of 2. The binary code to Gray code circuit 815 converts the binary encoded auxiliary read pointers pop_pt_r and pop_pt_p into Gray code encoded auxiliary read pointers pop_gray_r and pop_gray_p, respectively, and converts the binary encoded auxiliary write pointers push_pt_r and push_pt_p into Gray code encoded auxiliary write pointers push_gray_r and push_gray_p. The synchronization circuit 801 is used to resample the Gray code-encoded auxiliary read pointer pop_gray_p at the frequency of the write pointer signal to generate a Gray code-encoded synchronous read pointer pop_gray_sync_b, and to resample the Gray code-encoded auxiliary write pointer push_gray_p at the frequency of the read pointer signal to generate a Gray code-encoded synchronous write pointer push_gray_sync_b.

[0095] Comparator 807 receives and compares the Gray code-encoded auxiliary write pointer push_gray_r and the Gray code-encoded synchronous read pointer pop_gray_sync_b. When the Gray code-encoded auxiliary write pointer push_gray_r and the Gray code-encoded synchronous read pointer pop_gray_sync_b are identical except for the most significant and second most significant bits, the asynchronous FIFO memory can set the full pointer push_full to a predetermined value (e.g., the full index push_full will be set to 1). If the Gray code-encoded auxiliary write pointer push_gray_r and the Gray code-encoded synchronous read pointer pop_gray_sync_b are not identical except for the most significant and second most significant bits, then the full index push_full will not be set to a predetermined value (e.g., the full index push_full will be set to 0).

[0096] Comparator 808 receives and compares the Gray code-encoded auxiliary read pointer `pop_gray_r` with the Gray code-encoded synchronous write pointer `push_gray_sync_b`. When all bits of the Gray code-encoded auxiliary read pointer `pop_gray_r` and the Gray code-encoded synchronous write pointer `push_gray_sync_b` are identical, the asynchronous FIFO memory can set the null pointer `pop_empty` to a predetermined value (e.g., the null index `pop_empty` will be set to 1). If not all bits of the Gray code-encoded auxiliary read pointer `pop_gray_r` and the Gray code-encoded synchronous write pointer `push_gray_sync_b` are identical, the null index `pop_empty` will not be set to a predetermined value (e.g., the null index `pop_empty` will be set to 0).

[0097] In addition to determining the current empty / full state of the FIFO as described above, in embodiments of the present invention, one or more FIFO frequency signals corresponding to one or more unconfigured entries based on the current depth may be disabled, thereby effectively reducing the power consumption of the asynchronous FIFO memory. Taking an asynchronous FIFO memory with a maximum depth of 8 as an example, assuming the current depth is set to 6, at least 7 independent Isolation Clock Gating (ICG) circuits can be used to control the FIFO frequency signals. One ICG circuit is used to disable the FIFO frequency signals corresponding to the two unconfigured entries, and the remaining 6 ICG circuits are used to control the FIFO frequency signals corresponding to the 6 configured entries.

[0098] Figure 7This is a schematic diagram of an isolated clock gating circuit according to an embodiment of the present invention. It is assumed that the isolated clock gating circuit (hereinafter referred to as the ICG circuit) 700 is the ICG circuit corresponding to the first FIFO input.

[0099] The ICG circuit 700 receives a frequency enable signal Clk_en and a FIFO frequency signal Clk_FIFO. It enables or disables the FIFO frequency signal Clk_FIFO based on the frequency enable signal Clk_en to generate a controlled FIFO frequency signal Clk_FIFO'. When the first piece of data is pushed to the transmission interface between the master device and the asynchronous FIFO memory, the valid input data signal in_valid is set to a predetermined value, and the write pointer push_pt points to the first FIFO entry. The asynchronous FIFO memory can generate the frequency enable signal Clk_en based on the write pointer push_pt and the valid input data signal in_valid. For example, by inputting the write pointer push_pt and the valid input data signal in_valid into an AND logic gate, the frequency enable signal Clk_en is generated and set to a predetermined value (e.g., Clk_en is set to 1). The frequency enable signal Clk_en is provided to the ICG circuit 700 to enable the FIFO frequency signal Clk_FIFO corresponding to the first FIFO entry. Therefore, the controlled FIFO frequency signal Clk_FIFO' is enabled, while the FIFO frequency signals corresponding to other FIFO entries are disabled. In response to the enabled FIFO frequency signal Clk_FIFO', the data payload_in is stored in the first FIFO entry pointed to by the write pointer push_pt. After the data is written to the first FIFO entry, the frequency enable signal Clk_en is no longer set to a predetermined value (e.g., the frequency enable signal Clk_en is set to 0), thus disabling the FIFO frequency signal Clk_FIFO corresponding to the first FIFO entry. Therefore, the controlled FIFO frequency signal Clk_FIFO' is not enabled.

[0100] Similarly, when the second data is pushed to the transmission interface between the master device and the asynchronous FIFO memory, since the write pointer push_pt points to the second FIFO entry, the ICG circuit corresponding to the second FIFO entry can turn on (enable) the FIFO frequency signal corresponding to the second FIFO entry. In response, the data payload_in will be stored in the second FIFO entry pointed to by the write pointer push_pt, while the FIFO frequency signals corresponding to other FIFO entries will be turned off. The remaining operations follow the same principle. Through the above independent isolated clock gating operation, the power consumption of the asynchronous FIFO memory can be effectively reduced.

[0101] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should fall within the scope of the present invention.

Claims

1. A control method for an asynchronous first-in-first-out (FIFO) memory, used to control the operation of an asynchronous FIFO memory, characterized in that, The asynchronous FIFO memory is coupled between a master device and a slave device to cache data written by the master device, and the method includes: The current depth of the asynchronous FIFO memory is determined based on at least one of a frequency ratio, a burst length, and a continuous transmission length, wherein the frequency ratio is a ratio of a frequency of a first frequency signal used by the master device to a frequency of a second frequency signal used by the slave device. Based on the current depth, one or more entries of the asynchronous FIFO memory are configured to be used, wherein the asynchronous FIFO memory comprises multiple entries, and the current depth is less than or equal to the total number of the multiple entries; and According to the current depth, multiple FIFO frequency signals are provided to the asynchronous FIFO memory, where one FIFO frequency signal corresponds to an entry, and one or more FIFO frequency signals corresponding to one or more entries that are not configured according to the current depth are not enabled.

2. The control method for asynchronous FIFO memory as described in claim 1, characterized in that, The greater the difference between the frequency of the first frequency signal and the frequency of the second frequency signal, the smaller the current depth.

3. The control method for asynchronous FIFO memory as described in claim 1, characterized in that, The longer the burst length or the longer the continuous transmission length, the greater the current depth.

4. The control method for asynchronous FIFO memory as described in claim 1, characterized in that, The control method further includes: In response to a write operation of the master device, a write pointer is updated, wherein the write pointer is represented by a plurality of characters; In response to a read operation from the slave device, a read pointer is updated, wherein the read pointer is represented by a plurality of characters; and A full index or an empty index is generated based on the write pointer and the read pointer. When the write pointer and the read pointer are identical except for the most significant bit, the full index is set to a first predetermined value. When all bits of the write pointer are the same as all bits of the read pointer, the null pointer is set to a second predetermined value.

5. The control method for asynchronous FIFO memory as described in claim 1, characterized in that, The control method further includes: A write pointer is updated in response to a write operation on the master device; In response to a read operation from the slave device, a read pointer is updated; and A full index is generated based on the current depth, the write pointer, and the read pointer. When the absolute value of the difference between a value corresponding to the write pointer and a value corresponding to the read pointer is equal to the current depth, the full index is set to a predetermined value.

6. A data transmission system, characterized in that, The data transmission system includes: A main device; and An asynchronous first-in-first-out (FIFO) memory is coupled between the master device and a slave device, and contains multiple entries for caching data written by the master device. The master device and at least one of the asynchronous FIFO memory determine a current depth of the asynchronous FIFO memory based on at least one of a frequency ratio, a burst length, and a continuous transmission length, wherein the current depth is less than or equal to the total number of the plurality of entries, and the frequency ratio is the ratio of a frequency of a first frequency signal used by the master device to a frequency of a second frequency signal used by the slave device. The asynchronous FIFO memory configures one or more entries used by the asynchronous FIFO memory according to the current depth, and controls multiple FIFO frequency signals according to the current depth, wherein one FIFO frequency signal corresponds to one entry, and one or more FIFO frequency signals corresponding to one or more entries that are not configured according to the current depth are not enabled.

7. The data transmission system as described in claim 6, characterized in that, The greater the difference between the frequency of the first frequency signal and the frequency of the second frequency signal, the smaller the current depth.

8. The data transmission system as described in claim 6, characterized in that, The longer the burst length or the longer the continuous transmission length, the greater the current depth.

9. The data transmission system as described in claim 6, characterized in that, The asynchronous FIFO memory updates a write pointer (represented by multiple characters) in response to a write operation of the master device, updates a read pointer (represented by multiple characters) in response to a read operation of the slave device, and generates a full index or a null index based on the write pointer and the read pointer. The full index is set to a first predetermined value when all bits of the write pointer and the read pointer are the same except for the most significant bit, and the null index is set to a second predetermined value when all bits of the write pointer and the read pointer are the same.

10. The data transmission system as described in claim 6, characterized in that, The asynchronous FIFO memory updates a write pointer (represented by multiple characters) in response to a write operation of the master device, updates a read pointer (represented by multiple characters) in response to a read operation of the slave device, and generates a full index based on the write pointer and the read pointer, wherein the full index is set to a predetermined value when the absolute value of the difference between a value corresponding to the write pointer and a value corresponding to the read pointer is equal to the current depth.

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