Bus receiver with electronic device

Abstract

The application provides a bus receiver, comprising: a voltage regulating module and a detection comparator module; the voltage regulating module comprises a voltage regulating unit and a voltage clamping unit; the detection comparator module comprises a bias current generating unit, a current mirror unit, a back gate voltage biasing unit, a level shifting unit, a comparator unit and an output unit; the voltage regulating unit is used for regulating down the first bus voltage and the second bus voltage to obtain the first bus voltage and the second bus voltage after down regulation; the voltage clamping unit is used for clamping the first bus voltage and the second bus voltage after down regulation to clamp the first bus voltage and the second bus voltage after down regulation to a preset range and output a first differential voltage signal; and the back gate voltage biasing unit is used for generating a back gate voltage and biasing the back gate voltage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor communication, and more particularly to a bus receiver and electronic device. Background Technology

[0002] The bus receiver is an integrated electrical isolation device used for bidirectional data communication on balanced, multi-point bus transmission lines, providing data output corresponding to the voltage differential provided on a two-conductor data bus.

[0003] The current bus receiver has the following defects: (1) When the input voltage exceeds the operating range of the bus receiver, it will damage the circuit; (2) It does not support the input range of positive and negative common-mode voltages and does not support a wide range of power supply voltages; (3) The comparator does not support negative input voltages. Summary of the Invention

[0004] This invention provides a bus receiver and electronic device to solve the problems of circuit damage caused by excessive input voltage, lack of support for positive and negative common-mode voltage input range, lack of support for wide range of power supply voltage, and comparator lack of support for negative input voltage.

[0005] According to a first aspect of the present invention, a bus receiver is provided for outputting different output signals based on differential voltages of the bus voltage, comprising: a voltage regulation module and a detection comparator module; the voltage regulation module includes a voltage regulation unit, a voltage clamping unit, and a filtering unit; the detection comparator module includes: a bias current generation unit, a current mirror unit, a back gate voltage bias unit, a level shifting unit, a comparator unit, and an output unit;

[0006] The first input terminal of the voltage regulation unit is connected to the first bus voltage terminal, and the second input terminal of the voltage regulation unit is connected to the second bus voltage terminal for receiving the first bus voltage and the second bus voltage. The output terminal of the voltage regulation unit is connected to the first terminal of the voltage clamping unit, and the second terminal of the voltage clamping unit is connected to the input terminal of the filtering unit. The first output terminal of the filtering unit is connected to the first terminal of the level shifting unit, and the second output terminal of the filtering unit is connected to the second terminal of the level shifting unit. The third terminal of the level shifting unit is connected to the first terminal of the back gate voltage biasing unit, and the second terminal of the back gate voltage biasing unit is connected to the first terminal of the bias current generating unit. The second terminal of the bias current generating unit is connected to the first terminal of the current mirror unit, and the second terminal of the current mirror unit is connected to the first terminal of the comparator unit and an output signal terminal. The third terminal of the back gate voltage biasing unit is connected to the second terminal of the comparator unit, and the third terminal of the comparator unit is connected to the first terminal of the output unit. The second terminal of the output unit is connected to the output signal terminal.

[0007] The voltage regulation unit is used to perform step-down regulation on the first bus voltage and the second bus voltage to obtain the step-down regulated first bus voltage and the second bus voltage;

[0008] The voltage clamping unit is used to clamp the first bus voltage and the second bus voltage after buck regulation, so as to clamp the first bus voltage and the second bus voltage after buck regulation to a preset range, and output a first differential voltage signal, wherein the first differential voltage signal represents the difference between the first bus voltage and the second bus voltage;

[0009] The filtering unit is used to filter the first bus voltage and the second bus voltage after the step-down regulation to obtain and output the second differential voltage signal.

[0010] The back gate voltage biasing unit is used to generate a back gate voltage and bias the back gate voltage.

[0011] The level shifting unit is used to receive the second differential voltage signal and perform level shifting on the second differential voltage signal to output a third differential voltage signal.

[0012] The comparator unit is used to convert the third differential voltage signal into a single-ended signal;

[0013] The output unit is used to amplify the single-ended signal and output an output signal based on the single-ended signal.

[0014] Optionally, the voltage clamping unit includes a first MOSFET, a second MOSFET, a first Zener diode, and a second Zener diode;

[0015] The first terminal of the first MOSFET is connected to the first terminal of the voltage regulation unit, the second terminal of the first MOSFET, and the first terminal of the filter unit. The first terminal of the second MOSFET is connected to the second terminal of the voltage regulation unit, the second terminal of the second MOSFET, and the second terminal of the filter unit. The third terminal of the first MOSFET is connected to the negative terminal of the first Zener diode. The positive terminal of the first Zener diode is connected to the positive terminal of the second Zener diode and ground. The negative terminal of the second Zener diode is connected to the third terminal of the second MOSFET.

[0016] Optionally, the voltage regulation unit includes a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0017] Wherein, the first end of the first resistor is connected to the first bus voltage terminal, the second end of the first resistor is connected to the first end of the third resistor and the first end of the first MOSFET, the second end of the third resistor is connected to the first end of the fourth resistor and ground, the second end of the fourth resistor is connected to the first end of the second resistor and the first end of the second MOSFET, and the second end of the second resistor is connected to the second bus voltage terminal.

[0018] The voltage regulation unit is configured such that the ratio between the value of the first resistor and the value of the third resistor is equal to the ratio between the value of the second resistor and the value of the fourth resistor, and the ratio between the value of the first resistor and the value of the third resistor is a proportional coefficient for the voltage reduction regulation of the first bus voltage and the second bus voltage.

[0019] Optionally, the filtering unit includes a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, and a third capacitor;

[0020] Wherein, the first end of the fifth resistor is connected to the first end of the first MOS transistor, the second end of the fifth resistor is connected to the first end of the first capacitor, the first end of the third capacitor and the first end of the level shifting unit, the second end of the first capacitor is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the first end of the sixth resistor, the second end of the third capacitor and the second end of the level shifting unit, and the second end of the sixth resistor is connected to the first end of the second MOS transistor.

[0021] Optionally, the level shifting unit includes: a third MOS transistor, a fourth MOS transistor, a seventh resistor, and an eighth resistor;

[0022] The first end of the third MOS transistor and the first end of the fourth MOS transistor are respectively connected to the first output end of the filter unit and the second output end of the filter unit. The second end of the third MOS transistor and the second end of the fourth MOS transistor are connected to the first end of the compensation unit. The third end of the third MOS transistor and the third end of the fourth MOS transistor are respectively connected to the first end of the seventh resistor and the eighth resistor. The second ends of the seventh resistor and the eighth resistor are grounded.

[0023] Optionally, the back gate voltage bias unit includes a back gate voltage generation unit and a bias unit. The back gate voltage generation unit includes a fifth MOS transistor, a sixth MOS transistor, a third MOS transistor, and a fourth MOS transistor. The bias unit includes a seventh MOS transistor and an eighth MOS transistor.

[0024] In this configuration, the first terminal of the fifth MOSFET is connected to the third terminal of the fourth MOSFET, the first terminal of the sixth MOSFET is connected to the third terminal of the third MOSFET, the fifth MOSFET is connected to the second terminal of the sixth MOSFET, the third terminals of the fifth MOSFET and the sixth MOSFET are connected to the comparator unit, and the first terminals of the fifth MOSFET and the sixth MOSFET are also connected to the first terminal of the seventh MOSFET to transmit the back gate voltage to the bias unit; the second terminal of the seventh MOSFET is connected to the first terminal of the seventh MOSFET, the third terminal of the seventh MOSFET is connected to the first and second terminals of the eighth MOSFET, and the third terminal of the eighth MOSFET is grounded.

[0025] Optionally, the comparator unit includes: a ninth MOS transistor, a tenth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor;

[0026] Wherein, the first end of the ninth MOS transistor and the first end of the tenth MOS transistor are respectively connected to the fifth MOS transistor and the sixth MOS transistor, the second end of the ninth MOS transistor is connected to the first end of the ninth MOS transistor and the second end of the tenth MOS transistor, and the third end of the ninth MOS transistor and the third end of the tenth MOS transistor are grounded.

[0027] The comparator unit is configured as follows:

[0028] When the differential voltage signal is above a preset threshold, a first single-ended signal is output;

[0029] When the differential voltage signal is less than the preset threshold, a second single-ended signal is output.

[0030] Optionally, the bus receiver further includes a clamping unit; the clamping unit includes a tenth MOS transistor and an eleventh MOS transistor;

[0031] Wherein, the first terminal of the tenth MOS transistor is connected to the output terminal of the comparator unit and the second terminal of the tenth MOS transistor, the third terminal of the tenth MOS transistor is connected to the first terminal of the eleventh MOS transistor, the first terminal of the eleventh MOS transistor is also connected to the second terminal of the eleventh MOS transistor, and the third terminal of the eleventh MOS transistor is grounded.

[0032] The clamping unit is configured to clamp the first single-ended signal.

[0033] Optionally, the output unit includes: a thirteenth MOS transistor; the first terminal of the thirteenth MOS transistor is connected to the first terminal of the eleventh MOS transistor, the second terminal of the thirteenth MOS transistor is connected to the third terminal of the twelfth MOS transistor, and the third terminal of the thirteenth MOS transistor is connected to the output signal terminal;

[0034] The output unit is configured as follows:

[0035] When the single-ended signal is the first single-ended signal, the first output signal is output;

[0036] When the single-ended signal is the second single-ended signal, the second output signal is output.

[0037] Optionally, the first output signal is characterized as a high level, and the second output signal is characterized as a low level.

[0038] Optionally, the bias current generating unit includes: a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, a transistor, and a ninth resistor;

[0039] Wherein, the first terminal of the fourteenth MOSFET is connected to the first terminal of the fifteenth MOSFET, the second terminal of the fourteenth MOSFET is connected to the second terminal and the third terminal of the fifteenth MOSFET, the third terminals of the fourteenth MOSFET and the fifteenth MOSFET are respectively connected to the first terminals of the sixteenth MOSFET and the seventeenth MOSFET, the first terminal of the sixteenth MOSFET is also connected to the second terminals of the sixteenth MOSFET and the seventeenth MOSFET, the third terminal of the sixteenth MOSFET is connected to the first terminal and the second terminal of the transistor, the third terminal of the transistor is grounded, the third terminal of the seventeenth MOSFET is connected to the first terminal of the ninth resistor, and the second terminal of the ninth resistor is grounded.

[0040] Optionally, the current mirror unit includes: the fourteenth MOS transistor, the fifteenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor, and the twenty-second MOS transistor;

[0041] The first terminals of the fourteenth and fifteenth MOSFETs are all connected to the first terminals of the eighteenth to twenty-second MOSFETs. The second terminals of the fourteenth and fifteenth MOSFETs are all connected to the second terminals of the eighteenth to twenty-second MOSFETs. The third terminal of the eighteenth MOSFET is connected to the first terminal of the seventh MOSFET. The third terminal of the nineteenth MOSFET is connected to the first terminal of the compensation unit. The third terminal of the twentieth MOSFET is connected to the second terminal of the compensation unit. The third terminal of the twenty-first MOSFET is connected to the comparator unit. The third terminal of the twenty-second MOSFET is connected to the output signal terminal.

[0042] Optionally, the bus receiver further includes a compensation unit, which includes: a 22nd MOS transistor, a 23rd MOS transistor, and a 10th resistor;

[0043] Wherein, the first end of the 23rd MOSFET is connected to the 22nd MOSFET, the second end of the 23rd MOSFET is connected to the output signal terminal, the third end of the 23rd MOSFET is connected to the first end of the 10th resistor and the 3rd MOSFET, and the second end of the 10th resistor is connected to the 4th MOSFET;

[0044] The compensation unit is configured to generate a compensation voltage, which is characterized as a fixed threshold voltage and a hysteresis voltage.

[0045] According to a second aspect of the invention, an electronic device is provided, comprising the first aspect and the optional bus receiver described herein.

[0046] The bus receiver and electronic device provided by this invention regulates and clamps the input bus voltage through a voltage adjustment unit and a voltage clamping unit, thereby controlling the range of the bus voltage and ensuring that the voltage is clamped to prevent damage when the input voltage exceeds the receiver's operating range. Furthermore, this invention generates a back-gate voltage through a back-gate voltage biasing unit, thus supporting a wider range of positive and negative common-mode voltage inputs and a wider range of VCC power supply voltages. Further, this invention uses a level shifting unit to boost the input bus voltage, enabling support for negative input voltages by converting negative input voltage levels to levels greater than ground, while also providing a certain amplification effect.

[0047] Furthermore, in a preferred embodiment, the present invention compensates for the process deviation and temperature characteristics of the resistor by using a fixed threshold voltage and hysteresis voltage generated by the compensation unit.

[0048] In other preferred embodiments, the present invention reduces transmission delay by adding a clamping unit in the comparator module, and facilitates the achievement of symmetry in transmission delay time when the output is high and low. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the structure of a bus receiver in one embodiment of the present invention. Figure 1 ;

[0051] Figure 2 This is a schematic diagram of the structure of a bus receiver in one embodiment of the present invention. Figure 2 ;

[0052] Figure 3 This is a schematic diagram of the detection comparator module in a bus receiver according to an embodiment of the present invention. Figure 1 ;

[0053] Figure 4 This is a schematic diagram of the detection comparator module in a bus receiver according to an embodiment of the present invention. Figure 2 ;

[0054] Figure 5 This is a schematic diagram of the operating waveform of the bus receiver in one embodiment of the present invention. Figure 1 ;

[0055] Figure 6 This is a schematic diagram of the operating waveform of the bus receiver in one embodiment of the present invention. Figure 2 .

[0056] Explanation of reference numerals in the attached figures:

[0057] 1-Voltage regulation module;

[0058] 101 - Voltage regulation unit;

[0059] R1 - First resistor;

[0060] R2 - Second resistor;

[0061] R3 - Third resistor;

[0062] R4 - Fourth resistor;

[0063] 102 - Voltage clamping unit;

[0064] M1 - First MOSFET;

[0065] M2 - Second MOSFET;

[0066] Z1 - First Zener tube;

[0067] Z2 - Second Zener tube;

[0068] 103 - Filtering unit;

[0069] R5 - Fifth resistor;

[0070] R6 - the sixth resistor;

[0071] C1 - First capacitor;

[0072] C2 - Second capacitor;

[0073] C3 - The third capacitor;

[0074] 2-Detection comparator module;

[0075] 201-Level shift unit;

[0076] M3 - Third MOSFET;

[0077] M4 - Fourth MOSFET;

[0078] R7 - Seventh resistor R7;

[0079] R8 - the eighth resistor;

[0080] 202 - Bias current generating unit;

[0081] M14 - Fourteenth MOSFET;

[0082] M15 - The fifteenth MOSFET;

[0083] M16 - The sixteenth MOSFET;

[0084] M17 - The seventeenth MOSFET;

[0085] Q1 - Transistor;

[0086] R9 - Ninth resistor;

[0087] 203 - Back gate voltage bias unit;

[0088] M5 - The fifth MOSFET;

[0089] M6 - The sixth MOSFET;

[0090] M7 - Seventh MOSFET;

[0091] M8 - The eighth MOSFET;

[0092] 204 - Comparator unit;

[0093] M9 - Ninth MOSFET;

[0094] M10 - The tenth MOSFET;

[0095] 205 - Output Unit;

[0096] M13 - The thirteenth MOSFET;

[0097] 206 - Current Mirror Unit;

[0098] M18 - The eighteenth MOSFET;

[0099] M20 - The twentieth MOSFET;

[0100] M21 - The twenty-first MOSFET;

[0101] M22 - The twenty-second MOSFET;

[0102] 207-Clamping Unit;

[0103] M11 - Eleventh MOSFET;

[0104] M12 - The twelfth MOSFET;

[0105] 208 - Compensation Unit;

[0106] M19 - The nineteenth MOSFET;

[0107] M23 - The 23rd MOSFET;

[0108] R10 - The tenth resistor;

[0109] INH - First bus voltage terminal INH;

[0110] INL - Second bus voltage terminal;

[0111] INH-INL - First differential voltage signal;

[0112] inh-int / inl-int - the second differential voltage signal. Detailed Implementation

[0113] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0114] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0115] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0116] Please refer to Figure 1 as well as Figure 2 This invention provides a bus receiver for outputting different output signals based on the differential voltage of the bus voltage, comprising: a voltage adjustment module 1 and a detection comparator module 2; the voltage adjustment module 1 includes a voltage adjustment unit 101, a voltage clamping unit 102, and a filtering unit 103; the detection comparator module 2 includes: a bias current generation unit 202, a current mirror unit 206, a back gate voltage bias unit 203, a level shifting unit 201, a comparator unit 204, and an output unit 205;

[0117] The first input terminal of the voltage adjustment unit 101 is connected to the first bus voltage terminal INH, and the second input terminal of the voltage adjustment unit 101 is connected to the second bus voltage terminal INL, for receiving the first bus voltage and the second bus voltage. The output terminal of the voltage adjustment unit 101 is connected to the first terminal of the voltage clamping unit 102, and the second terminal of the voltage clamping unit 102 is connected to the input terminal of the filtering unit 103. The first output terminal of the filtering unit 103 is connected to the first terminal of the level shifting unit 201, and the second output terminal of the filtering unit 103 is connected to the second terminal of the level shifting unit 201. The third terminal is connected to the first terminal of the back gate voltage bias unit 203. The second terminal of the back gate voltage bias unit 203 is connected to the first terminal of the bias current generating unit 202. The second terminal of the bias current generating unit 202 is connected to the first terminal of the current mirror unit 206. The second terminal of the current mirror unit 206 is connected to the first terminal of the comparator unit 204 and an output signal terminal. The third terminal of the back gate voltage bias unit 203 is connected to the second terminal of the comparator unit 204. The third terminal of the comparator unit 204 is connected to the first terminal of the output unit 205. The second terminal of the output unit 205 is connected to the output signal terminal.

[0118] The voltage regulation unit 101 is used to perform step-down regulation on the first bus voltage and the second bus voltage to obtain the step-down regulated first bus voltage and the second bus voltage;

[0119] The voltage clamping unit 102 is used to clamp the first bus voltage and the second bus voltage after buck adjustment, so as to clamp the first bus voltage and the second bus voltage after buck adjustment to a preset range, and output a first differential voltage signal INH-INL, wherein the first differential voltage signal INH-INL represents the difference between the first bus voltage and the second bus voltage.

[0120] The filtering unit 103 is used to filter the first bus voltage and the second bus voltage after the step-down regulation to obtain and output the second differential voltage signal inh-int / inl-int.

[0121] The back gate voltage biasing unit 203 is used to generate a back gate voltage and bias the back gate voltage.

[0122] The level shifting unit 201 is used to receive the second differential voltage signal inh-int / inl-int and perform level shifting on the second differential voltage signal inh-int / inl-int, and output the third differential voltage signal.

[0123] The comparator unit 204 is used to convert the third differential voltage signal into a single-ended signal.

[0124] The output unit 205 is used to amplify the single-ended signal and output an output signal based on the single-ended signal.

[0125] Regarding the working principle of the bus receiver, in a specific embodiment, the bus receiver is used to detect the differential voltage between the two bus voltages, namely INH-INL (the first differential voltage signal INH-INL). When INH-INL (the first differential voltage signal INH-INL) is above a preset threshold, the output is high level, and when INH-INL (the first differential voltage signal INH-INL) is below a certain threshold, the output is low level.

[0126] For details, please refer to Figure 5 as well as Figure 6 Differential voltage detection needs to support a wide common-mode voltage range, and the common-mode voltage VCM can be higher than the high power supply voltage VCC of the bus receiver (i.e., Figure 5 The waveform can be either lower than the receiver's power supply low voltage GND (i.e., the waveform of the receiver). Figure 6 (The waveform), at this time the receiver needs to adjust the bus voltage to the voltage range that the receiver can detect.

[0127] In the above scheme, the voltage adjustment unit 101 and the voltage clamping unit 102 adjust and clamp the input bus voltage to control the range of the bus voltage and ensure that the voltage is clamped to prevent damage when the input voltage exceeds the operating range of the receiver. In addition, the present invention generates a back gate voltage through the back gate voltage biasing unit 203, thereby supporting a wider positive and negative common-mode voltage input range and a wider VCC power supply voltage. Furthermore, the present invention uses the level shifting unit 201 to boost the level of the input bus voltage, enabling support for negative input voltages by converting the negative input voltage level to a level greater than ground voltage, while also providing a certain amplification effect.

[0128] For more information on voltage clamping unit 102, please refer to [link / reference needed]. Figure 1 In a preferred embodiment, the voltage clamping unit 102 includes a first MOS transistor M1, a second MOS transistor M2, a first Zener transistor Z1, and a second Zener transistor Z2.

[0129] The first terminal of the first MOSFET M1 is connected to the first terminal of the voltage regulation unit 101, the second terminal of the first MOSFET M1, and the first terminal of the filter unit 103. The first terminal of the second MOSFET M2 is connected to the second terminal of the voltage regulation unit 101, the second terminal of the second MOSFET M2, and the second terminal of the filter unit 103. The third terminal of the first MOSFET M1 is connected to the negative terminal of the first Zener diode Z1. The positive terminal of the first Zener diode Z1 is connected to the positive terminal of the second Zener diode Z2 and ground. The negative terminal of the second Zener diode Z2 is connected to the third terminal of the second MOSFET M2.

[0130] In the above scheme, in order to prevent damage to the internal circuit after the first bus voltage INH or the second bus voltage INL exceeds the normal operating range, the first MOSFET M1, the second MOSFET M2, the first Zener transistor Z1, and the second Zener transistor Z2 play the role of voltage clamping.

[0131] For more information on voltage regulation unit 101, please refer to [link / reference needed]. Figure 1 In a preferred embodiment, the voltage regulation unit 101 includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0132] Wherein, the first end of the first resistor R1 is connected to the first bus voltage terminal INH, the second end of the first resistor R1 is connected to the first end of the third resistor R3 and the first end of the first MOS transistor M1, the second end of the third resistor R3 is connected to the first end of the fourth resistor R4 and ground, the second end of the fourth resistor R4 is connected to the first end of the second resistor R2 and the first end of the second MOS transistor M2, and the second end of the second resistor R2 is connected to the second bus voltage terminal INL.

[0133] The voltage regulation unit 101 is configured such that the ratio between the value of the first resistor R1 and the value of the third resistor R3 is equal to the ratio between the value of the second resistor R2 and the value of the fourth resistor R4, and the ratio between the value of the first resistor R1 and the value of the third resistor R3 is a proportional coefficient for the voltage reduction regulation of the first bus voltage and the second bus voltage.

[0134] In a specific embodiment, the common-mode voltage amplitude is reduced, and the differential-mode voltage is also reduced accordingly. By reducing the voltage of the first bus voltage and the second bus voltage, the first differential voltage is adjusted to a voltage range that the bus receiver can detect.

[0135] For information on filter unit 103, please refer to [link / reference needed]. Figure 1In a preferred embodiment, the filter unit 103 includes a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0136] Wherein, the first end of the fifth resistor R5 is connected to the first end of the first MOS transistor M1, the second end of the fifth resistor R5 is connected to the first end of the first capacitor C1, the first end of the third capacitor C3 and the first end of the level shifting unit 201, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is connected to the first end of the sixth resistor R6, the second end of the third capacitor C3 and the second end of the level shifting unit 201, and the second end of the sixth resistor R6 is connected to the first end of the second MOS transistor M2.

[0137] In the above scheme, the fifth resistor R5, the sixth resistor R6, the first capacitor C1, the second capacitor C2, and the third capacitor C3 filter the input bus voltage signal, thereby reducing common-mode noise interference and ensuring the safety of circuit operation.

[0138] Specifically, once the first bus voltage and the second bus voltage are adjusted to a range acceptable to the bus receiver, the comparator module 2 needs to determine whether the output differential voltage is higher or lower than the preset threshold. The differential voltage and common-mode voltage input to the comparator module 2 have both been attenuated by N+1 times, where N is greater than 0, N is a positive integer, and N is the step-down ratio.

[0139] For information on level shift unit 201, please refer to [link / reference needed]. Figure 3 In a preferred embodiment, the level shifting unit 201 includes: a third MOS transistor M3, a fourth MOS transistor M4, a seventh resistor R7, and an eighth resistor R8;

[0140] The first terminal of the third MOS transistor M3 and the first terminal of the fourth MOS transistor M4 are respectively connected to the first output terminal and the second output terminal of the filter unit 103. The second terminal of the third MOS transistor M3 and the second terminal of the fourth MOS transistor M4 are connected to the first terminal of the compensation unit 208. The third terminal of the third MOS transistor M3 and the third terminal of the fourth MOS transistor M4 are respectively connected to the first terminal of the seventh resistor R7 and the eighth resistor R8. The second terminals of the seventh resistor R7 and the eighth resistor R8 are grounded.

[0141] In a specific embodiment, the seventh resistor R7 and the eighth resistor R8 are resistive loads, requiring a small voltage margin to allow the bus receiver to support a lower power supply voltage VCC. In addition, due to the level shifting unit 201's level boosting of the differential voltage signal, that is, when the second differential voltage signal inh-int / inl-int (inh-int and inl-int) is also lower than the ground voltage, the level shifting unit 201 boosts the differential voltage signal, making the second differential voltage signal inh-int / inl-int (inh-int and inl-int) higher than the ground voltage.

[0142] For more information on the back gate voltage bias unit 203, please refer to [link / reference needed]. Figure 4 In a preferred embodiment, the back gate voltage bias unit 203 includes a back gate voltage generation unit and a bias unit. The back gate voltage generation unit includes a fifth MOS transistor M5, a sixth MOS transistor M6, a third MOS transistor M3, and a fourth MOS transistor M4. The bias unit includes a seventh MOS transistor M7 and an eighth MOS transistor M8.

[0143] Specifically, the first terminal of the fifth MOSFET M5 is connected to the third terminal of the fourth MOSFET M4, the first terminal of the sixth MOSFET M6 is connected to the third terminal of the third MOSFET M3, the fifth MOSFET M5 is connected to the second terminal of the sixth MOSFET M6, the third terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are connected to the comparator unit 204, and the first terminals of the fifth MOSFET M5 and the sixth MOSFET M6 are also connected to the first terminal of the seventh MOSFET M7 to transmit the back gate voltage to the bias unit; the second terminal of the seventh MOSFET M7 is connected to the first terminal of the seventh MOSFET M7, the third terminal of the seventh MOSFET M7 is connected to the first and second terminals of the eighth MOSFET M8, and the third terminal of the eighth MOSFET M8 is grounded.

[0144] In a specific embodiment, the seventh MOS transistor M7 and the eighth MOS transistor M8 generate a bias voltage to bias the back gate voltage generated by the back gate voltage generation unit. Specifically, since the voltage range of the power supply voltage VCC that needs to be supported is relatively wide, and inh-int / inl-int (the second differential voltage signal inh-int / inl-int) may also be lower than the ground voltage, the back gate voltage is adaptively biased so that the threshold voltages of the seventh MOS transistor M7, the eighth MOS transistor M8, the third MOS transistor M3, and the fourth MOS transistor M4 can change in the same direction, thereby avoiding the impact of process and temperature changes on the performance of the bus receiver.

[0145] For more information on comparator unit 204, please refer to [link / reference]. Figure 3 In a preferred embodiment, the comparator unit 204 includes: a ninth MOS transistor M9, a tenth MOS transistor M10, a fifth MOS transistor M5, and a sixth MOS transistor M6;

[0146] Wherein, the first end of the ninth MOS transistor M9 and the first end of the tenth MOS transistor M10 are respectively connected to the fifth MOS transistor M5 and the sixth MOS transistor M6, the second end of the ninth MOS transistor M9 is connected to the first end of the ninth MOS transistor M9 and the second end of the tenth MOS transistor M10, and the third end of the ninth MOS transistor M9 and the third end of the tenth MOS transistor M10 are grounded.

[0147] The comparator unit 204 is configured to:

[0148] When the differential voltage signal is above a preset threshold, a first single-ended signal is output;

[0149] When the differential voltage signal is less than the preset threshold, a second single-ended signal is output.

[0150] For more information on clamping unit 207, please refer to [link / reference]. Figure 3 In a preferred embodiment, the bus receiver further includes a clamping unit 207; the clamping unit 207 includes an eleventh MOS transistor M11 and a twelfth MOS transistor M12;

[0151] Wherein, the first end of the eleventh MOS transistor M11 is connected to the output end of the comparator unit 204 and the second end of the eleventh MOS transistor M11, the third end of the eleventh MOS transistor M11 is connected to the first end of the twelfth MOS transistor M12, the first end of the twelfth MOS transistor M12 is also connected to the second end of the twelfth MOS transistor M12, and the third end of the twelfth MOS transistor M12 is grounded.

[0152] The clamping unit 207 is configured to clamp the first single-ended signal.

[0153] For information on output unit 205, please refer to [link / reference needed]. Figure 3 In a preferred embodiment, the output unit 205 includes: a thirteenth MOS transistor M13; the first end of the thirteenth MOS transistor M13 is connected to the first end of the eleventh MOS transistor M11, the second end of the thirteenth MOS transistor M13 is connected to the third end of the twelfth MOS transistor M12, and the third end of the thirteenth MOS transistor M13 is connected to the output signal terminal;

[0154] The output unit 205 is configured as follows:

[0155] When the single-ended signal is the first single-ended signal, the first output signal is output;

[0156] When the single-ended signal is the second single-ended signal, the second output signal is output.

[0157] In a specific embodiment, the first output signal is characterized as a high level, and the second output signal is characterized as a low level.

[0158] In a specific embodiment, the comparator unit 204 converts the differential signal into a single-ended signal, and then further amplifies the single-ended signal through the thirteenth MOS transistor M13.

[0159] In the above scheme, in order to reduce transmission delay, the outbb signal (i.e., single-ended signal) only needs to be near the threshold voltage of the thirteenth MOSFET M13. However, when the output signal changes from high to low, if the voltage of the outbb signal (i.e., single-ended signal) exceeds the preset threshold when the output is high, it will take a relatively longer time to drop below the threshold of the thirteenth MOSFET M13, thereby increasing unnecessary transmission delay. The present invention clamps the outbb signal (i.e., single-ended signal) through the clamping unit 207 to limit the amplitude of the outbb signal (i.e., single-ended signal) when the output signal is high, so that when the output signal changes to low, a smaller transmission delay can be achieved, thereby making the transmission delay of high output and low output more symmetrical.

[0160] In the above scheme, the present invention reduces transmission delay by adding a clamping unit 207 to the comparator module, and is beneficial to achieving symmetry in transmission delay time when the output is high and low.

[0161] For information on the bias current generation unit, please refer to [link / reference]. Figure 4 In a preferred embodiment, the bias current generating unit includes: a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET M16, a seventeenth MOSFET M17, a transistor Q1, and a ninth resistor R9;

[0162] Wherein, the first end of the fourteenth MOSFET is connected to the first end of the fifteenth MOSFET, the second end of the fourteenth MOSFET is connected to the second end and the third end of the fifteenth MOSFET, the third ends of the fourteenth MOSFET and the fifteenth MOSFET are respectively connected to the first ends of the sixteenth MOSFET M16 and the seventeenth MOSFET M17, the first end of the sixteenth MOSFET M16 is also connected to the second ends of the sixteenth MOSFET M16 and the seventeenth MOSFET M17, the third end of the sixteenth MOSFET M16 is connected to the first end and the second end of the transistor Q1, the third end of the transistor Q1 is grounded, the third end of the seventeenth MOSFET M17 is connected to the first end of the ninth resistor R9, and the second end of the ninth resistor R9 is grounded.

[0163] For information on current mirror unit 206, please refer to [link / reference needed]. Figure 3 In a preferred embodiment, the current mirror unit 206 includes: the fourteenth MOS transistor M14, the fifteenth MOS transistor M15, the eighteenth MOS transistor M18, the twentieth MOS transistor M20, the twenty-first MOS transistor M21, and the twenty-second MOS transistor M22;

[0164] The first and second ends of the fourteenth MOSFET M14 and the fifteenth MOSFET M15 are connected to the first and second ends of the eighteenth MOSFET M18, the twentieth MOSFET M20, the twentieth MOSFET M21, and the twenty-second MOSFET M22. The third end of the eighteenth MOSFET M18 is connected to the first end of the seventh MOSFET M7. The third end of the twentieth MOSFET M20 is connected to the compensation unit 208. The third end of the twentieth MOSFET M21 is connected to the comparator unit 204. The third end of the twenty-second MOSFET M22 is connected to the output signal terminal.

[0165] For information regarding compensation unit 208, please refer to [link / reference needed]. Figure 4 In a preferred embodiment, the bus receiver further includes a compensation unit 208, which includes the nineteenth MOS transistor M19, the twenty-third MOS transistor M23, and the tenth resistor R10.

[0166] Wherein, the first end of the 23rd MOSFET M23 is connected to the 19th MOSFET M19, the second end of the 23rd MOSFET M23 is connected to the output signal terminal, the third end of the 23rd MOSFET M23 is connected to the first end of the 10th resistor R10 and the third MOSFET M3, and the second end of the 10th resistor R10 is connected to the fourth MOSFET M4.

[0167] The compensation unit 208 is configured to generate a compensation voltage, which is characterized as a fixed threshold voltage and a hysteresis voltage.

[0168] In a specific embodiment, for different bus receivers, the input differential voltage signal that determines whether it is high or low is an arbitrary value (i.e., not necessarily 0). At this time, it is necessary to adjust this threshold through the tenth resistor R10. Specifically, after the output changes from high to low or from low to high, the hysteresis of the input threshold voltage is introduced to ensure that the output does not oscillate near the threshold.

[0169] Furthermore, when the output signal out is low, the nineteenth MOSFET M19 and the twenty-third MOSFET M23 will add an additional current to the third MOSFET M3 terminal, thereby increasing the voltage required for the subsequent high-level output of the output signal out. The bias current is the Vbe voltage of transistor Q1 divided by the resistance value. Using the same type of resistors, the ninth resistor R9 and the tenth resistor R10, can offset the influence of the resistance value caused by different process angles and temperatures.

[0170] In the above scheme, the present invention compensates for the process deviation and temperature characteristics of the resistor by using the fixed threshold voltage and hysteresis voltage generated by the compensation unit 208.

[0171] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bus receiver for outputting a different output signal in accordance with a differential voltage of a bus voltage, characterized by, include: Voltage regulation module and detection comparator module; The voltage regulation module includes a voltage regulation unit, a voltage clamping unit, and a filtering unit; The detection comparator module includes: a bias current generation unit, a current mirror unit, a back gate voltage bias unit, a level shifting unit, a comparator unit, and an output unit; The first input terminal of the voltage regulation unit is connected to the first bus voltage terminal, and the second input terminal of the voltage regulation unit is connected to the second bus voltage terminal for receiving the first bus voltage and the second bus voltage. The output terminal of the voltage regulation unit is connected to the first terminal of the voltage clamping unit, and the second terminal of the voltage clamping unit is connected to the input terminal of the filtering unit. The first output terminal of the filtering unit is connected to the first terminal of the level shifting unit, and the second output terminal of the filtering unit is connected to the second terminal of the level shifting unit. The third terminal of the level shifting unit is connected to the first terminal of the back gate voltage biasing unit, and the second terminal of the back gate voltage biasing unit is connected to the first terminal of the bias current generating unit. The second terminal of the bias current generating unit is connected to the first terminal of the current mirror unit, and the second terminal of the current mirror unit is connected to the first terminal of the comparator unit and an output signal terminal. The third terminal of the back gate voltage biasing unit is connected to the second terminal of the comparator unit, and the third terminal of the comparator unit is connected to the first terminal of the output unit. The second terminal of the output unit is connected to the output signal terminal. The voltage regulation unit is used to perform step-down regulation on the first bus voltage and the second bus voltage to obtain the step-down regulated first bus voltage and the second bus voltage; The voltage clamping unit is used to clamp the first bus voltage and the second bus voltage after buck regulation, so as to clamp the first bus voltage and the second bus voltage after buck regulation to a preset range, and output a first differential voltage signal, wherein the first differential voltage signal represents the difference between the first bus voltage and the second bus voltage; The filtering unit is used to filter the first bus voltage and the second bus voltage after the step-down regulation to obtain and output the second differential voltage signal. The back gate voltage biasing unit is used to generate a back gate voltage and bias the back gate voltage. The level shifting unit is used to receive the second differential voltage signal and perform level shifting on the second differential voltage signal to output a third differential voltage signal. The comparator unit is used to convert the third differential voltage signal into a single-ended signal; The output unit is used to amplify the single-ended signal and output an output signal based on the single-ended signal.

2. The bus receiver of claim 1, wherein, The voltage clamping unit includes a first MOSFET, a second MOSFET, a first Zener diode, and a second Zener diode; The first terminal of the first MOSFET is connected to the first terminal of the voltage regulation unit, the second terminal of the first MOSFET, and the first terminal of the filter unit. The first terminal of the second MOSFET is connected to the second terminal of the voltage regulation unit, the second terminal of the second MOSFET, and the second terminal of the filter unit. The third terminal of the first MOSFET is connected to the negative terminal of the first Zener diode. The positive terminal of the first Zener diode is connected to the positive terminal of the second Zener diode and ground. The negative terminal of the second Zener diode is connected to the third terminal of the second MOSFET.

3. The bus receiver of claim 2, wherein, The voltage regulation unit includes a first resistor, a second resistor, a third resistor, and a fourth resistor; Wherein, the first end of the first resistor is connected to the first bus voltage terminal, the second end of the first resistor is connected to the first end of the third resistor and the first end of the first MOSFET, the second end of the third resistor is connected to the first end of the fourth resistor and ground, the second end of the fourth resistor is connected to the first end of the second resistor and the first end of the second MOSFET, and the second end of the second resistor is connected to the second bus voltage terminal. The voltage regulation unit is configured such that the ratio between the value of the first resistor and the value of the third resistor is equal to the ratio between the value of the second resistor and the value of the fourth resistor, and the ratio between the value of the first resistor and the value of the third resistor is a proportional coefficient for the voltage reduction regulation of the first bus voltage and the second bus voltage.

4. The bus receiver according to claim 3, characterized in that, The filtering unit includes a fifth resistor, a sixth resistor, a first capacitor, a second capacitor, and a third capacitor; Wherein, the first end of the fifth resistor is connected to the first end of the first MOS transistor, the second end of the fifth resistor is connected to the first end of the first capacitor, the first end of the third capacitor and the first end of the level shifting unit, the second end of the first capacitor is connected to the first end of the second capacitor, the second end of the second capacitor is connected to the first end of the sixth resistor, the second end of the third capacitor and the second end of the level shifting unit, and the second end of the sixth resistor is connected to the first end of the second MOS transistor.

5. The bus receiver according to claim 4, characterized in that, The level shifting unit includes: a third MOS transistor, a fourth MOS transistor, a seventh resistor, and an eighth resistor; The first end of the third MOS transistor and the first end of the fourth MOS transistor are respectively connected to the first output end and the second output end of the filter unit. The second end of the third MOS transistor and the second end of the fourth MOS transistor are connected to the first end of the compensation unit. The third end of the third MOS transistor and the third end of the fourth MOS transistor are respectively connected to the first end of the seventh resistor and the eighth resistor. The second ends of the seventh resistor and the eighth resistor are grounded.

6. The bus receiver according to claim 5, characterized in that, The back gate voltage bias unit includes a back gate voltage generation unit and a bias unit. The back gate voltage generation unit includes a fifth MOS transistor, a sixth MOS transistor, a third MOS transistor, and a fourth MOS transistor. The bias unit includes a seventh MOS transistor and an eighth MOS transistor. In this configuration, the first terminal of the fifth MOSFET is connected to the third terminal of the fourth MOSFET, the first terminal of the sixth MOSFET is connected to the third terminal of the third MOSFET, the fifth MOSFET is connected to the second terminal of the sixth MOSFET, the third terminals of the fifth MOSFET and the sixth MOSFET are connected to the comparator unit, and the first terminals of the fifth MOSFET and the sixth MOSFET are also connected to the first terminal of the seventh MOSFET to transmit the back gate voltage to the bias unit; the second terminal of the seventh MOSFET is connected to the first terminal of the seventh MOSFET, the third terminal of the seventh MOSFET is connected to the first and second terminals of the eighth MOSFET, and the third terminal of the eighth MOSFET is grounded.

7. The bus receiver according to claim 6, characterized in that, The comparator unit includes: a ninth MOS transistor, a tenth MOS transistor, the fifth MOS transistor, and a sixth MOS transistor; Wherein, the first end of the ninth MOS transistor and the first end of the tenth MOS transistor are respectively connected to the fifth MOS transistor and the sixth MOS transistor, the second end of the ninth MOS transistor is connected to the first end of the ninth MOS transistor and the second end of the tenth MOS transistor, and the third end of the ninth MOS transistor and the third end of the tenth MOS transistor are grounded. The comparator unit is configured as follows: When the differential voltage signal is above a preset threshold, a first single-ended signal is output; When the differential voltage signal is less than the preset threshold, a second single-ended signal is output.

8. The bus receiver according to claim 7, characterized in that, It also includes a clamping unit; the clamping unit includes an eleventh MOS transistor and a twelfth MOS transistor; Wherein, the first terminal of the eleventh MOS transistor is connected to the output terminal of the comparator unit and the second terminal of the eleventh MOS transistor, the third terminal of the eleventh MOS transistor is connected to the first terminal of the twelfth MOS transistor, the first terminal of the twelfth MOS transistor is also connected to the second terminal of the twelfth MOS transistor, and the third terminal of the twelfth MOS transistor is grounded. The clamping unit is configured to clamp the first single-ended signal.

9. The bus receiver according to claim 8, characterized in that, The output unit includes: a thirteenth MOS transistor; the first terminal of the thirteenth MOS transistor is connected to the first terminal of the eleventh MOS transistor, the second terminal of the thirteenth MOS transistor is connected to the third terminal of the twelfth MOS transistor, and the third terminal of the thirteenth MOS transistor is connected to the output signal terminal; The output unit is configured as follows: When the single-ended signal is the first single-ended signal, the first output signal is output; When the single-ended signal is the second single-ended signal, the second output signal is output.

10. The bus receiver according to claim 9, characterized in that, The first output signal is characterized as a high level, and the second output signal is characterized as a low level.

11. The bus receiver according to claim 10, characterized in that, The bias current generating unit includes: a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, a transistor, and a ninth resistor; Wherein, the first terminal of the fourteenth MOSFET is connected to the first terminal of the fifteenth MOSFET, the second terminal of the fourteenth MOSFET is connected to the second terminal and the third terminal of the fifteenth MOSFET, the third terminals of the fourteenth MOSFET and the fifteenth MOSFET are respectively connected to the first terminals of the sixteenth MOSFET and the seventeenth MOSFET, the first terminal of the sixteenth MOSFET is also connected to the second terminals of the sixteenth MOSFET and the seventeenth MOSFET, the third terminal of the sixteenth MOSFET is connected to the first terminal and the second terminal of the transistor, the third terminal of the transistor is grounded, the third terminal of the seventeenth MOSFET is connected to the first terminal of the ninth resistor, and the second terminal of the ninth resistor is grounded.

12. The bus receiver according to claim 11, characterized in that, The current mirror unit includes: the fourteenth MOSFET, the fifteenth MOSFET, the eighteenth MOSFET, the twentieth MOSFET, the twenty-first MOSFET, and the twenty-second MOSFET; The first and second ends of the fourteenth and fifteenth MOSFETs are connected to the first and second ends of the eighteenth, twentieth, eleventh, and twentieth MOSFETs, respectively. The third end of the eighteenth MOSFET is connected to the first end of the seventh MOSFET. The third end of the twentieth MOSFET is connected to the compensation unit. The third end of the twentieth MOSFET is connected to the comparator unit. The third end of the twentieth MOSFET is connected to the output signal terminal.

13. The bus receiver according to claim 12, characterized in that, It also includes a compensation unit, which includes: a nineteenth MOS transistor, a twenty-third MOS transistor, and a tenth resistor; Wherein, the first end of the 23rd MOSFET is connected to the 19th MOSFET, the second end of the 23rd MOSFET is connected to the output signal terminal, the third end of the 23rd MOSFET is connected to the first end of the 10th resistor and the 3rd MOSFET, and the second end of the 10th resistor is connected to the 4th MOSFET; The compensation unit is configured to generate a compensation voltage, which is characterized as a fixed threshold voltage and a hysteresis voltage.

14. An electronic device comprising a bus receiver as described in any one of claims 1-13.

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