Computer system and memory management method based on crystal stack architecture

Abstract

A computer system based on a crystal stack architecture can replace static memory with low-cost volatile memory to achieve cache function in high-speed operation. The computer system includes at least a first memory crystal layer and a logic circuit layer stacked into a wafer stack. The first memory crystal layer includes at least a first memory and a second memory with different performance characteristics. The logic circuit layer includes at least a logic circuit connected to the first memory and the second memory to execute a logic expression. The logic circuit is an embedded programmable logic gate array. The logic circuit includes at least an operation unit and a performance manager. The operation unit includes a plurality of operation gates for executing the logic expression. The performance manager is connected to the plurality of operation gates and can connect input terminals or output terminals of the plurality of operation gates to the first memory or the second memory according to performance requirements of the plurality of operation gates.

Description

Technical Field

[0001] This application relates to a calculator system with a chip stacking architecture, and more particularly to a calculator architecture with dynamically configurable cache performance. Background Technology

[0002] Parallel computing utilizes a different computer hardware architecture than traditional single-processor architectures. Its applications are wide-ranging, including artificial intelligence, machine learning, and blockchain. These applications require exponentially increasing computational demands. Computer devices developed for specific applications often face extremely high memory throughput requirements or massive storage capacity requirements. Memory, based on its purpose, can be broadly categorized into two types: storage and computation. Storage memory is suitable for storing data with low-frequency changes. Computational memory is suitable for storing data that changes frequently during high-speed computations. In traditional processor architectures, static memory (SRAM) is typically used as a cache to facilitate computation. While SRAM offers significantly higher performance than volatile memory (VRAM), it is also relatively expensive. As computational demands increase, cache capacity requirements also rise, increasing product cost. Furthermore, when implementing various application-specific logical operations using application-specific chips, the logical expressions involved often need flexible adjustments or change with version updates. Therefore, the performance and capacity requirements for cache vary constantly. In traditional computer architectures, SRAM is typically a fixed hardware configuration. If the configuration is less than the demand, performance will be affected. If the configuration is greater than the demand, costs will be wasted. In view of this, a flexible and scalable memory management architecture needs to be developed. Summary of the Invention

[0003] This application proposes a calculator system based on a crystal stack architecture, which can replace static memory with low-cost volatile memory to achieve caching functionality in high-speed computation. The calculator system includes at least a first memory crystal layer and logic circuit layers stacked on a wafer. The first memory crystal layer includes at least a first memory and a second memory. The first performance characteristics of the first memory differ from the second performance characteristics of the second memory.

[0004] The logic circuit layer contains at least logic circuits. The logic circuits connect the first memory and the second memory, and use the first memory and the second memory to execute logical expressions. The logic circuits are embedded programmable gate arrays.

[0005] The logic circuit includes at least an arithmetic unit and a performance manager. The arithmetic unit includes multiple arithmetic gates for executing the logical expression. The performance manager connects to the multiple arithmetic gates and can connect the input or output terminals of the multiple arithmetic gates to the first memory or the second memory respectively, according to the performance requirements of the multiple arithmetic gates.

[0006] In a further embodiment, when an arithmetic gate cannot find data in the first memory, the performance manager connects the arithmetic gate to the second memory to access the data.

[0007] In a further embodiment, the calculator system can be a multi-layer memory stack architecture. For example, it may consist of a second memory crystal layer, with the first memory crystal layer and the logic circuit layer combined to form the wafer stack. A third memory may be implemented in the second memory crystal layer, and a third performance characteristic of the third memory crystal layer differs from the first or second performance characteristic. The logic circuit accesses the third memory in the same manner as described above.

[0008] In a further embodiment, a plurality of connection pads are included between the logic circuit layer and the first memory crystal layer for transmitting signals. The logic circuit may further include a first memory controller and a second memory controller, corresponding to the first memory and the second memory, respectively. Specifically, the first memory controller is connected to the performance manager and coupled to the first memory through the plurality of connection pads to control the first memory. Similarly, the second memory controller is connected to the performance manager and coupled to the second memory through the plurality of connection pads to control the second memory.

[0009] In a further embodiment, the first performance characteristic and the second performance characteristic refer to memory latency. In the architecture of this application, the first memory and the second memory each contain one or more memory arrays, and the memory latency can be configured via instructions through a memory controller. For example, the first memory controller and the second memory controller respectively use instructions to change the dimensional configuration of the plurality of memory arrays in the first memory and the second memory to adjust the first performance characteristic and the second performance characteristic.

[0010] Another embodiment of this application proposes a memory management method, based on the above-described calculator system embodiment, to maximize the efficiency of a repeatedly executed logical expression. The execution of the logical expression includes at least the following steps: searching for a first input parameter in first memory and substituting it into the logical expression to generate an output value. During the execution of the logical expression, the performance controller performs the following steps of the memory management method: When the logical expression requires reading the first input parameter, it searches for it in first memory. When the first input parameter is not found in first memory, it searches for it in second memory. When the first input parameter is found in second memory, it is first moved from second memory to first memory, and then read from first memory to cause the logical expression to generate the output value. Finally, the output value is stored in first memory. The memory latency of the first memory is lower than that of the second memory.

[0011] In a further embodiment, the performance controller can also calculate the access rate of each block in the first memory. When the remaining space in the first memory is less than a minimum threshold, the performance controller can use commands to move the data of the block with the lowest access rate in the first memory to the second memory.

[0012] Furthermore, the lookup process iterates from faster memory to slower memory. For example, if the first input parameter cannot be found in the second memory, the performance controller can also look for the first input parameter in a third memory. Similarly, after the first input parameter is found in the second memory, it is moved from the second memory to the first memory before being used by the logical expression. The memory latency of the third memory is higher than that of the second memory.

[0013] In summary, the calculator system and memory management method proposed in this application leverage the advantages of a crystal stack architecture to create a calculator architecture suitable for massive memory access. Volatile memory can be optimized by a performance manager to replace traditional static memory, thereby reducing costs. The logic circuitry employs an eFPGA architecture suitable for parallel computing, giving this calculator a significant performance advantage in the artificial intelligence and blockchain markets. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 This is a three-dimensional wafer product 100 with a chip stacking architecture according to an embodiment of this application.

[0016] Figure 2 This is a calculator system 200 according to an embodiment of this application.

[0017] Figure 3 The three-dimensional wafer product 300 is made using a chip stacking architecture according to another embodiment of this application.

[0018] Figure 4 This is the calculator system 400 in this application embodiment.

[0019] Figure 5 This is the calculator system 500 according to an embodiment of this application.

[0020] Figure 6 This is a flowchart of a memory management method according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] This application proposes a calculator system based on a crystal stacking architecture, which can replace static memory with low-cost volatile memory to achieve cache functionality in high-speed operations.

[0023] Figure 1 This is an embodiment of the 3D wafer product 100 of this application. The 3D wafer product 100 is composed of at least one memory crystal layer 110, a logic circuit layer 120, and a substrate 130 stacked together. The substrate 130 provides basic support and additional wiring space. Multiple connection pads 102 or 104 are configured between each layer to provide signal channels. The 3D wafer product 100 of this embodiment is a semi-finished product of a computer system 200, which, after dicing, can produce multiple independently operating computer systems 200. Figure 1 As shown, each calculator system 200 may include a plurality of memory devices 112 and a plurality of logic circuits 122, possessing the same three-dimensional wafer structure. In other words, the memory devices 112 and logic circuits 122 included in each calculator system 200 are pre-laid in the memory crystal layer 110 and the logic circuit layer 120, and then fabricated as a three-dimensional structure in the form of chip stacking. In the three-dimensional structure, the circuit wires between the chipsets do not need to occupy extra area, and thousands of connection pads 102 and 104 can be used directly as the signal transmission path, so that the data transmission performance problem is effectively solved, thereby realizing the calculator system 200 of this application.

[0024] In the embodiments of this application, the logic circuit 122 is implemented using Embedded Field Programmable Gate Array (eFPGA) technology. As the name suggests, it implements a programmable gate array in an embedded system. Compared to traditional Application Specific Integrated Circuit (ASIC) technology, eFPGA offers advantages such as extremely high hardware parallel processing capabilities, deep pipelines, and high-width buses. These advantages are particularly suitable for applications in fields such as artificial intelligence, technology learning, deep learning, and blockchain. While the operating frequency of a traditional eFPGA may not be comparable to ASIC technology, introducing caches between the logic circuits 122 can increase the operating speed of the eFPGA by 1.5 to 2 times. Therefore, the embodiments of this application utilize the advantages of a chip stacking architecture, enabling the logic circuit 122 to easily access the memory device 112 through a large number of wires.

[0025] Figure 2 This is a calculator system 200 according to an embodiment of this application. Figure 1 The 3D wafer product 100 shown, after completing the chip stacking process, can be further processed by wafer dicing to form multiple computer systems 200. The memory layer 210 is from... Figure 1 The portion cut out from the memory crystal layer 110 can accommodate various types of memory, such as first memory 211, second memory 212, and third memory 213. The logic circuit 220 is derived from... Figure 1 The portion cut out from the logic circuit layer 120 is stacked with the memory layer 210, and includes various circuit modules, such as a first memory controller 221, a second memory controller 222, a third memory controller 223, a performance manager 225, and an arithmetic unit 510. Each memory controller is connected to the first memory 211, the second memory 212, and the third memory 213 in the memory layer 210, and is responsible for transmitting access commands and data, as well as controlling memory performance parameters. The substrate 230 is from... Figure 1 The portion cut out from the substrate 130. Signals are transmitted between the stacked memory layer 210 and logic circuit 220 via multiple connection pads 102. The logic circuit 220 is also fixed to the substrate 230 via multiple connection pads 104. The substrate 230 provides basic support for the entire computer system 200 and also provides additional wiring space. Signals between the memory controller and the multiple memory devices are transmitted via the connection pads 102.

[0026] In summary, the calculator system 200 embodiments of this application include at least a memory layer 210 and logic circuitry 220 stacked on a wafer. The memory layer 210 contains various types of memory, each with different performance characteristics. For example, a performance characteristic could be memory latency. According to traditional memory architectures, the first memory 211 and the second memory 212 can be understood as a combination of one or more memory arrays, each array consisting of multiple memory cells arranged in a matrix, with each memory cell responsible for storing one bit of data. Memory latency is the frequency required to retrieve or write data from these memory cells. Many factors affect memory latency, primarily transistor characteristics and capacitance effects. For example, when driving a memory array, the more memory cells in each row, the longer the latency.

[0027] This application embodiment configures memory with different latency characteristics in memory layer 210, enabling the calculator system 200 to optimize computation with minimal cost. For example, in the memory array of the first memory 211, each row is configured with a smaller number of memory units, reducing latency. Thus, the first memory 211 is suitable for storing data with a high update frequency, such as data being calculated in the computation unit 510. In contrast, each row of the memory array of the second memory 212 can be configured with a larger number of memory units, doubling the capacity. Although the latency of the second memory 212 is higher than that of the first memory 211, it is suitable for storing data with a low change frequency or large amounts. Furthermore, the calculator system 200 of this application can be configured with more types of memory according to the needs of actual applications, such as a third memory 213 that is slower but larger than the second memory 212, so that data with different performance requirements can be mapped to the most appropriate storage space.

[0028] In a further embodiment, the calculator system 200 may employ memory with dimension configuration capabilities. The dimensions of rows and columns in the memory array can be reconfigured through specific instructions and circuitry. When the number of memory cells in each row is changed, the capacitance effect can be altered, changing the memory latency characteristics. The dimension configuration can be set via instructions through the memory controller. For example, the first memory controller 221 and the second memory controller 222 can respectively change the dimension configuration of the memory arrays in the first memory controller 221 and the second memory controller 222 via instructions to adjust the corresponding performance characteristics, i.e., memory latency.

[0029] In conventional dynamic random access memory (DRAM), the memory latency is approximately 25 to 65 cycles. Through the configuration method of this embodiment, the memory latency of the first memory controller 221 can be set to 1 to 3 cycles, the memory latency of the second memory controller 222 to 3 to 12 cycles, and the memory latency of the third memory controller 223 to 12 to 25 cycles. With the first memory controller 221 configured for low latency, it is particularly suitable to replace conventional static random access memory (SRAM) and be provided to the arithmetic unit 510 as a cache or buffer used during computation.

[0030] Figure 1 After the logic circuit 122 is cut out from the logic circuit layer 120, it becomes Figure 2 The logic circuit 220 is an embedded programmable gate array (eFPGA), which includes a first memory controller 221, a second memory controller 222, a third memory controller 223, a performance manager 225, and one or more computing units 510. The first memory controller 221, the second memory controller 222, and the third memory controller 223 are correspondingly connected to and manage the first memory 211, the second memory 212, and the third memory 213. Multiple computing units 510 can be cascaded into a parallel computing architecture to execute specific applications. For example, the Convolutional Neural Network (CNN) algorithm, commonly used in machine learning, is an array-based iterative computation suitable for parallel operations. Details regarding the CNN algorithm belong to the existing field of artificial intelligence and are therefore not described in detail in this embodiment. The computing unit 510 can programmatically convert any mathematical operation, including the mathematical formulas used in the CNN algorithm, into a hardware structure composed of multiple adders and multipliers. Combined with the first memory 211, the second memory 212, and the third memory 213 as computational aids, performance optimization can be achieved.

[0031] The performance manager 225 is a control unit proposed in this application for memory management optimization. The multiple arithmetic units 510 may include various arithmetic gates, such as adders, multipliers, dividers, multiplexers, and various logic gates. The input or output value of each arithmetic gate may be stored in the memory in the memory layer 210; therefore, the performance manager 225 can dynamically configure its connection to the corresponding memory according to the data access requirements of each arithmetic gate. On the other hand, the first memory controller 221, the second memory controller 222, and the third memory controller 223 are connected to the performance manager 225 and, driven by the performance manager 225, control the corresponding first memory 211, second memory 212, and third memory 213 through the multiple connection pads 102. For detailed design of the memory controllers, please refer to the JEDEC memory standard protocol; further details are omitted here.

[0032] Figure 3 This is a three-dimensional wafer product 300 fabricated using a chip stacking architecture according to another embodiment of this application. (And...) Figure 1 Similarly, the 3D wafer product 300 consists of at least one memory crystal layer 110, a logic circuit layer 120, and a substrate 130 stacked together. In addition, the 3D wafer product 300 may also include a memory crystal layer 140 additionally stacked on top of the memory crystal layer 110. Multiple memory devices 142 may be disposed in the memory crystal layer 140. In other words, the number of chip stacking layers is not limited to three. The memory crystal layer 140 and the memory crystal layer 110 are connected by multiple connection pads 101 to transmit signals. After the 3D wafer product 300 is stacked, it can be further longitudinally diced to produce a calculator system 400.

[0033] Figure 4 It is based on Figure 3 The resulting calculator system 400 includes a memory layer 210, logic circuitry 220, a substrate 230, and a memory layer 240. The memory layer 210 is... Figure 3 The part cut out from the memory crystal layer 110, logic circuit 220 is Figure 3 The part cut out from logic circuit layer 120, substrate 230 is Figure 3 The portion cut out from memory crystal layer 140. Memory layer 240 is... Figure 3 The portion cut out from the memory crystal layer 140 refers to one or more of the multiple memory devices 142. Memory devices with different performance characteristics can be arranged in different layers. For example, a first memory 211 and a second memory 212 can be configured in memory layer 210. A third memory 213 can be configured in memory layer 240. A first memory controller 221 and a second memory controller 222 can control the first memory 211 and the second memory 212 respectively through connection pads 102. A third memory controller 223 can control the third memory 213 through connection pads 102 and 101. In order for the third memory controller 223 to access the third memory 213 in memory layer 240 across memory layer 210, space can be reserved in memory layer 210 to form a channel 214 for direct connection between connection pads 101 and 102. Since the third memory 213 is located in the memory layer 240, which is farther away from the logic circuit 220, it is more suitable as a large-capacity memory compared to the first memory 211 and the second memory 212 for storing static data with a low update frequency. In this embodiment, the arithmetic unit 510 accesses the third memory 213 in the same way as described above. The performance manager 225 connects the plurality of arithmetic gates to the appropriate memory according to the performance requirements of each arithmetic gate in the arithmetic unit 510.

[0034] Figure 5 This application describes a calculator system 500 according to an embodiment of the present application, illustrating one operating mode of the performance manager 225 and the arithmetic unit 510. For simplicity, Figure 5 The diagram only shows the relationship between the performance manager 225, the arithmetic unit 510, and various memory modules. The performance manager 225 itself can be a programmable microprocessor with calculation, judgment, and memory mapping functions. The arithmetic unit 510's memory access requests and access data are judged by the performance manager 225 and transferred to the most suitable set of memory modules. For example, the arithmetic unit 510 contains multiple arithmetic gates, such as adder 507 and multiplier 509, which can execute various logical expressions required by the application program through circuit combinations. Adder 507 reads data from input 501, performs addition, and outputs the value to multiplier 509. Multiplier 509 reads data from input 503, adds it to the output of adder 507, and stores the result back into memory through output 505. For the arithmetic unit 510, memory access is handled through the performance manager 225. The performance manager 225 determines how to forward access requests to the first memory 211, the second memory 212, and the third memory 213. In other words, the performance manager 225 can monitor the memory access requests of the multiple arithmetic gates, dynamically calculate the performance of each arithmetic gate, and connect the input or output terminals of the multiple arithmetic gates to the corresponding first memory 211, second memory 212, or third memory 213.

[0035] Figure 5 Although two arithmetic gates are displayed, it is understandable that the number of arithmetic gates in arithmetic unit 510 is not limited to this in practical applications. Performance Manager 225 can also further provide analysis and judgment functions to optimize the memory mapping method for arithmetic gates. One approach is to group multiple arithmetic gates together to simplify management, depending on the situation. For example, there may be six arithmetic gates in arithmetic unit 510. Performance Manager 225 can analyze the original arithmetic logic and find that it actually involves five arithmetic gates performing the calculation a thousand times, and then adding the result of the sixth arithmetic gate. In this case, Performance Manager 225 can group the first five arithmetic gates together and configure memory according to the performance requirements of the entire group.

[0036] In this embodiment, the performance manager 225 is described as "connecting" the input or output of an arithmetic gate to the corresponding memory. It is important to note that while physical electronic circuits inherently have coupling relationships, the "connection" described in this performance manager 225 embodiment represents a logical mapping, transfer, or switching—that is, multiplexing of data access. Multiplexing and switching techniques for electronic data can be implemented using known logic circuits and will not be explained in detail here. Figure 5The circuit connections illustrated can also be implemented in physical design using a memory mapping table. A memory mapping table is a storage management method that maps logical page frames to physical addresses. In this embodiment, different types of memory can be assigned different physical addresses. Therefore, the circuit connections shown in performance manager 225 can be implemented simply by manipulating the memory mapping table.

[0037] In addition, due to the low latency of the first memory 211 in this example, the performance manager 225 can also use the first memory 211 as a built-in cache or buffer. Any access to memory by an arithmetic gate can preferentially use the first memory 211. Only when the data is not found in the first memory 211 will the second memory 212 or the third memory 213 be used. In other words, when an arithmetic gate cannot find the data in the first memory controller 221, the performance manager 225 can connect the arithmetic gate to the second memory controller 222 to access the data.

[0038] The performance manager of this application can maximize its utility based on the aforementioned calculator system embodiments, but is not limited to the operation mode of the aforementioned embodiments. For example, the performance manager 225 can also implement the function of controlling the cache. Traditional calculator systems use expensive static memory as the first level (L1) and second level (L2) cache. This embodiment can use less expensive volatile memory, namely the first memory and the second memory, as the first level and the second level cache. Each arithmetic gate in the arithmetic unit 510, whether it is an adder, multiplier, divider, multiplexer, or various logic gates, can also be designed to operate in accordance with the memory access protocol, which can be summarized as: requiring the reading of one or more input parameters, performing operations, and requiring the writing of output data.

[0039] Figure 6This is a flowchart of a memory management method according to another embodiment of this application. First, in step 601, the arithmetic gate sends a read request to the performance manager 225 to read a first input parameter. In step 603, the arithmetic gate obtains the first input parameter output by the performance manager 225. In step 605, the arithmetic gate uses the first input parameter to perform its corresponding logical function to generate output data in step 607. In step 609, the arithmetic gate sends a write request to the performance manager, requesting the performance manager to store the output data in memory. In step 610, the arithmetic gate may receive an access permission signal from the performance manager, and then transmits the output data to the performance manager for subsequent storage operations. The arithmetic gate itself does not need to know which memory storage location the data will be sent to; it only needs to send a predetermined request or receive a response according to the memory access protocol to complete the memory access. The storage of physical data is arranged by the performance manager. Typically, the arithmetic unit 510 is designed to run repeatedly. Therefore, after completing step 610, the operation gate can repeatedly start from step 601.

[0040] On the other hand, the performance manager 225 can handle various memory access requests from the arithmetic gate, maximizing memory data access performance. In the calculator system of this embodiment, the first memory has the lowest latency among all memories, i.e., the fastest speed. Therefore, the performance manager will prioritize performing operations in the first memory. In step 611, when the performance manager 225 receives a read request from the arithmetic gate, it will prioritize searching for the first input parameter in the first memory. In step 613, there are different processing methods depending on the search result. If the first input parameter is not found in the first memory, step 615 is performed, and the first input parameter is found in the slower second memory and moved to the first memory. If the first input parameter is found in step 613, step 617 is executed directly. Similarly, after step 615 is completed, step 617 is also skipped. In step 617, the first input parameter is extracted from the first memory and transmitted to the arithmetic gate, so that the read request is satisfied.

[0041] When the performance manager 225 receives a write request from the arithmetic gate, requesting that output data be stored in memory, the performance manager 225 proceeds to step 619. In principle, the first memory is the preferred storage space for any new data. Therefore, in step 619, the performance manager checks whether the remaining space in the first memory is sufficient. If the space is sufficient, it directly runs step 623, receiving the output data transmitted from the arithmetic gate and storing it in the first memory. Conversely, if the remaining space in the first memory is insufficient, space must be freed up first. At this time, the performance manager executes step 621. In step 621, the performance manager moves the data in the least accessed block in the first memory to the slower second memory to free up space. In other words, the performance manager has cache management capabilities and can execute a Least Recently Used (LRU) algorithm to calculate the usage rate of each block in the first memory. After a long period of operation, only the most frequently used data will gradually remain in the first memory, keeping the calculator system running in an optimized state. After step 621 is completed, the performance manager can execute step 623 to satisfy the data write requirements of the operational gate.

[0042] It is understood that the memory access requirements of the components in the arithmetic unit 510 can comply with the JEDEC memory management protocol. Therefore, how the arithmetic unit 510 generates the signal format for memory access requirements for the arithmetic gate is not described in this embodiment. It is worth mentioning that in step 615, the process of searching for the first input parameter in the second memory may not be found. In this case, the search process can be extended to continue searching in the third memory, which is slower than the second memory, and so on. On the other hand, although this embodiment only describes the first input parameter, it is understood that an arithmetic gate may read multiple input parameters simultaneously for calculation, and the output data may also be multiple values. This embodiment does not limit the various forms that may arise in the physical design, and the implementation method of the performance manager providing optimized memory access functions for the arithmetic gate is universally applicable.

[0043] In summary, the memory management method of this application, based on the aforementioned calculator system embodiment, can maximize efficiency for a repeatedly executed logical expression. The execution of the logical expression includes at least the following steps: searching for a first input parameter in first memory and substituting it into the logical expression to generate an output value. During the execution of the logical expression, the performance controller performs the memory management method as follows: When the logical expression requires reading the first input parameter, it searches for it in first memory. When the first input parameter is not found in first memory, it searches for it in second memory. When the first input parameter is found in second memory, it is first moved from second memory to first memory, and then read from first memory to cause the logical expression to generate the output value. Finally, the output value is stored in first memory. The memory latency of the first memory is lower than that of the second memory.

[0044] In a further embodiment, the performance controller can also calculate the access rate of each block in the first memory. When the remaining space in the first memory is less than a minimum threshold, the performance controller can use commands to move the data of the block with the lowest access rate in the first memory to the second memory.

[0045] Furthermore, the lookup process iterates from faster memory to slower memory. For example, if the first input parameter cannot be found in the second memory, the performance controller can also look for the first input parameter in a third memory. Similarly, after the first input parameter is found in the second memory, it is moved from the second memory to the first memory before being used by the logical expression. The memory latency of the third memory is higher than that of the second memory.

[0046] In summary, the calculator system and memory management method proposed in this application leverage the advantages of a crystal stack architecture to create a calculator architecture suitable for massive memory access. Volatile memory can be optimized by a performance manager to replace traditional static memory, thereby reducing costs. The logic circuitry employs an eFPGA architecture suitable for parallel computing, giving this calculator a significant performance advantage in the artificial intelligence and blockchain markets.

[0047] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A calculator system, characterized in that, Include: A first memory crystal layer includes at least a first memory and a second memory, wherein a first performance characteristic of the first memory is different from a second performance characteristic of the second memory, and the first memory and the second memory are low-cost volatile memories, with the low-cost volatile memories replacing static memory; The second memory crystal layer includes a third memory, which is the volatile memory. A third performance characteristic of the third memory is different from the first performance characteristic or the second performance characteristic, and is used to store static data with a low update frequency. as well as A logic circuit layer, together with the second memory crystal layer, and the first memory crystal layer, are stacked on a wafer and contain logic circuits; wherein: The logic circuit connects the first memory and the second memory, and uses the first memory and the second memory to execute logical expressions; The logic circuit includes: The arithmetic unit includes multiple arithmetic gates for executing the logical expression; and A performance manager, connected to the plurality of arithmetic gates, is used to connect the input or output terminals of the plurality of arithmetic gates to the first memory or the second memory respectively according to the performance requirements of the plurality of arithmetic gates; When the arithmetic gate cannot find data in the first memory, the performance manager connects the arithmetic gate to the second memory to access the data. The third memory is located in the second memory crystal layer, which is far away from the logic circuit.

2. The calculator system as described in claim 1, characterized in that, The logic circuit is an embedded programmable gate array.

3. The calculator system as described in claim 1, characterized in that, It also includes multiple connection pads connecting the logic circuit layer and the first memory crystal layer for transmitting signals; wherein the logic circuit further includes: A first memory controller is connected to the performance manager and coupled to the first memory through the plurality of connection pads, for controlling the first memory; as well as A second memory controller is connected to the performance manager and coupled to the second memory through the plurality of connection pads for controlling the second memory.

4. The calculator system as described in claim 3, characterized in that: The first performance characteristic and the second performance characteristic are memory latency; The first memory and the second memory each contain one or more memory arrays; as well as The first memory controller and the second memory controller respectively change the dimensional configuration of the plurality of memory arrays in the first memory and the second memory by means of instructions, so as to adjust the first performance feature and the second performance feature.

5. A memory management method applied to the calculator system as described in claim 1, wherein the calculator system repeatedly executes a logical expression based on a first input parameter to generate an output value; characterized in that, The memory management method includes: Find the first input parameter from the first memory; If the first input parameter cannot be found in the first memory, the first input parameter is searched for in the second memory. When the first input parameter is found in the second memory, the first input parameter is moved from the second memory to the first memory. The first input parameter is read from the first memory and provided to the calculator system to execute a logical expression to generate the output value; The output value is stored in the first memory; wherein the memory latency of the first memory is lower than that of the second memory, and the first memory and the second memory are volatile memories.

6. The memory management method as described in claim 5, characterized in that, Also includes: Calculate the access rate of each block in the first memory; When the remaining space in the first memory is less than a minimum value, the data of the block with the lowest access rate will be moved to the second memory.

7. The memory management method as described in claim 5, characterized in that, Also includes: If the first input parameter cannot be found in the second memory, the first input parameter is searched for in a third memory. as well as When the first input parameter is found in the second memory, the first input parameter is moved from the second memory to the first memory; wherein: The memory latency of the third memory is higher than that of the second memory, and the third memory is the volatile memory.

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