A multi-octave power amplifier design method

Abstract

The application provides a multi-octave power amplifier design method, which introduces a nonlinear factor gamma after considering input nonlinear effect, greatly expands the second harmonic impedance space, and even approaches the open circuit point in part of the second harmonic impedance space, effectively relieving the design difficulty of the matching network. The embodiment shows that the power amplifier designed by the method can work in multi-octave, while maintaining the advantages of high efficiency, high gain and high output power.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a design method for a multi-octave power amplifier. Background Technology

[0002] Currently, an increasing number of mobile communication technologies are emerging. These technologies often encompass different frequency bands; for example, 4G includes bands such as 1830–1860MHz and 2110–2310MHz, while 5G includes bands such as 2515–2675MHz and 3400–3600MHz. Designing a separate power amplifier for each frequency band would undoubtedly significantly increase the system's cost and complexity. Researching multi-octave power amplifiers that can cover multiple frequency bands will help reduce system cost and size. Summary of the Invention

[0003] For multi-octave power amplifiers, the fundamental frequency and second harmonic impedance spaces overlap. For example, the operating frequency band of a multi-octave power amplifier can be represented as f0~t·f0, where f0 is the starting frequency of the operating frequency band, and t>2 is a real number. The operating frequency band is divided into m sub-bands according to octaves. The i-th sub-band is i·f0~(i+1)·f0, and its second harmonic is 2i·f0~2(i+1)·f0, which overlaps with the fundamental frequencies of the 2i-th sub-band 2i·f0~(2i+1)·f0 and the (2i+1)-th sub-band (2i+1)·f0~(2i+2)·f0. This overlap leads to bandwidth limitations in existing power amplifier operating modes. This invention provides a novel power amplifier operating mode. The design method based on this operating mode effectively expands the load impedance space, enabling the power amplifier to operate in multiple octaves while maintaining high efficiency.

[0004] Figure 1 This is the equivalent circuit of a power amplifier that takes into account input nonlinearity. At the gate of the transistor, there exists a gate-source capacitance C. gs The size of this capacitor is mainly affected by the gate-source voltage. Gate-source capacitance C gs This will introduce input nonlinearity, which will affect the gate input voltage and further affect the drain current. Figure 1 In the middle, the gate-source voltage V gs Represented as

[0005]

[0006] Among them, V gso V1 and V2 represent the gate bias voltage, fundamental voltage, and second harmonic voltage, respectively, α is the conduction angle, and θ is the angular frequency. Furthermore, the normalized gate-source voltage... Represented as

[0007]

[0008] The nonlinear factor γ = V2 / V1 is used to characterize the gate-source capacitance C. gs The input nonlinearity effect. Since V2 and V1 are out of phase, γ < 0. When γ = 0, it means that the input nonlinearity effect is ignored. Let Determine the cutoff angle β as

[0009]

[0010] Drain current I ds Represented as

[0011]

[0012] Among them, I r3 This is called drain current I. ds The compensation coefficient for the third harmonic component is expressed as follows:

[0013]

[0014] For drain current I ds Perform Fourier series expansion to determine the DC component I of the drain current. DC The real part of the fundamental component I 1r With imaginary part I 1i The real part I of the second harmonic component 2r With imaginary part I 2i The real part I of the third harmonic component 3r With imaginary part I 3i as follows:

[0015]

[0016]

[0017] I 1i =0 (6c)

[0018]

[0019] I 2i =0 (6c)

[0020] I 3r =0 (6d)

[0021] I 3i =0 (6e)

[0022] Drain voltage V ds Represented as

[0023]

[0024] The above expression uses the drain bias voltage V DD Normalization is performed. Here, δ represents the reactance factor, and ξ represents the resistivity factor. For the drain voltage V... ds Performing a Fourier series expansion yields the DC component V. DC The real part V of the fundamental component 1r With the imaginary part V 1i The real part V of the second harmonic component 2r With the imaginary part V 2i The real part V of the third harmonic component 3r With the imaginary part V 3i They are respectively

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032] Harmonic impedance Z n It can be calculated using the following formula.

[0033]

[0034] Among them, I m It is the maximum drain current, V DD This is the drain bias voltage. V nr With V ni Let I represent the real and imaginary parts of the nth harmonic component of the drain voltage, respectively. nr with I ni Let Z1 and Z2 represent the real and imaginary parts of the nth harmonic component of the drain current, respectively. Finally, the fundamental impedance Z1, second harmonic impedance Z2, and third harmonic impedance Z3 are expressed as follows:

[0035]

[0036]

[0037] Z3=∞(10c)

[0038] Among them, R opt =2V DD / I mThis indicates the optimal load impedance for a Class B power amplifier.

[0039] The drain efficiency DE is calculated by the following formula.

[0040]

[0041] Output power P out It can be represented as

[0042]

[0043] Figure 2 The relationship between drain efficiency DE and the nonlinearity factor γ and resistivity factor ξ is shown. Both the nonlinearity factor γ and the resistivity factor ξ have a significant impact on drain efficiency DE. The larger the absolute values ​​of the nonlinearity factor γ and the resistivity factor ξ, the smaller the drain efficiency DE. Figure 3 The output power P is displayed. out The relationship between the nonlinear factor γ and the resistive factor ξ. The larger the resistive factor ξ, the higher the output power P. out The smaller the value, the less the nonlinear factor γ affects the output power P. out The impact is relatively small.

[0044] When the nonlinearity factor γ = 0, the input nonlinearity effect is not considered. In this case, if the drain efficiency DE is to be greater than 60%, the resistivity factor ξ is taken as 0 ≤ ξ ≤ 0.7, and the optimal load impedance space is as follows: Figure 4 As shown in the figure. Z1 region represents the fundamental impedance space, and Z2 region represents the second harmonic impedance space. When considering input nonlinearity, taking -0.35≤γ≤0 and 0≤ξ≤0.5, the optimal load impedance space is as follows: Figure 5 As shown, by introducing a nonlinear factor γ to account for input nonlinearity, the second harmonic impedance space can be greatly expanded, with some parts of the second harmonic impedance space even approaching the open circuit point. Therefore, this effectively alleviates the design difficulty of the matching network.

[0045] Based on the above principle analysis, the multi-octave power amplifier design method of the present invention is as follows:

[0046] Step 1: Given the operating frequency band f0~t·f0 and drain efficiency DE of the multi-octave power amplifier to be designed.

[0047] Step 2: Based on the relationship between drain efficiency DE and input nonlinearity factor γ and resistivity factor ξ, determine the range of values ​​for nonlinearity factor γ and resistivity factor ξ.

[0048] Step 3: Determine the optimal load impedance space based on the range of values ​​for the nonlinear factor γ and the resistive factor ξ.

[0049] Step 4: Determine the output matching network topology; during the optimization of structural parameters, the fundamental impedance in the f0~2·f0 frequency band should be located in the Z1 region of the optimal load impedance space; for the 2·f0~t·f0 frequency band, it is itself the fundamental wave, and at the same time, it is also the second harmonic of f0~(t / 2)·f0, so the corresponding impedance should be located in the overlapping region of Z1 and Z2; for the t·f0~2t·f0 frequency band, it is the second harmonic of (t / 2)·f0~t·f0, so the corresponding impedance should be located in the Z2 region.

[0050] Step 5: Use the designed output matching network as the load of the transistor for source pulling, and determine the source fundamental frequency and second harmonic impedance; ensure that the corresponding nonlinear factor γ value is within the range of γ values ​​determined in Step 2.

[0051] Step 6: Design the input matching network based on the source fundamental frequency and the second harmonic impedance.

[0052] The beneficial effect of the multi-octave power amplifier design method described in this invention is that it achieves multi-octave operation while maintaining high efficiency. Attached Figure Description

[0053] Figure 1 : A schematic diagram of the equivalent circuit of a power amplifier considering input nonlinear effects;

[0054] Figure 2 Schematic diagram showing the relationship between drain efficiency DE and nonlinearity factor γ and resistivity factor ξ;

[0055] Figure 3 Output power P out A schematic diagram showing the relationship between the nonlinear factor γ and the resistive factor ξ;

[0056] Figure 4 : Schematic diagram of the optimal load impedance space when input nonlinearity is not considered, i.e., γ = 0 and 0 ≤ ξ ≤ 0.7;

[0057] Figure 5 : Schematic diagram of the optimal load impedance space when considering input nonlinear effects, i.e., -0.35≤γ≤0 and 0≤ξ≤0.5;

[0058] Figure 6 : Schematic diagram of the embodiment structure;

[0059] Figure 7 : Schematic diagram of simulation and test results of the embodiment. Detailed Implementation

[0060] To demonstrate the inventiveness and novelty of this invention, the implementation and effects of the verification technical solution are illustrated below with the aid of embodiments. The analysis will be conducted in conjunction with the accompanying drawings and specific embodiments, but the implementation of this invention is not limited thereto.

[0061] Without loss of generality, this embodiment uses a commonly used microstrip substrate with a relative permittivity of 3.66 and a substrate thickness of 0.508 mm.

[0062] The structure of the embodiment is as follows Figure 6 As shown, the key feature is that: the input terminal (Source), the first capacitor (C1), the first microstrip line segment (M1), the second microstrip line segment (M2), the third microstrip line segment (M3), the fourth microstrip line segment (M4), the fifth microstrip line segment (M5), and the sixth microstrip line segment (M6) are connected sequentially; the other end of the sixth microstrip line segment (M6) is simultaneously connected to one end of the seventh microstrip line segment (M7) and one end of the eighth microstrip line segment (M8); the other end of the seventh microstrip line segment (M7) is connected to the second capacitor (C1). 2) One end of the second capacitor (C2) is grounded; the other end of the eighth microstrip section (M8) is connected to the gate of the field-effect transistor (FET); the source of the field-effect transistor (FET) is grounded, and the drain is connected to one end of the ninth microstrip section (M9); the other end of the ninth microstrip section (M9) is connected to one end of the tenth microstrip section (M10), and the other end of the tenth microstrip section (M10) is simultaneously connected to one end of the eleventh microstrip section (M11) and one end of the fourteenth microstrip section (M14); the eleventh The other end of microstrip line segment (M11) is connected to one end of the twelfth microstrip line segment (M12), and the other end of the twelfth microstrip line segment (M12) is connected to one end of the thirteenth microstrip line segment (M13); the other end of the fourteenth microstrip line segment (M14) is simultaneously connected to one end of the fifteenth microstrip line segment (M15) and one end of the sixteenth microstrip line segment (M16); the other end of the fifteenth microstrip line segment (M15) is connected to one end of the third capacitor (C3), and the other end of the third capacitor (C3) is grounded; the sixteenth microstrip line segment... The other end of section (M16) is connected to one end of the seventeenth microstrip section (M17); the other ends of the thirteenth microstrip section (M13) and the seventeenth microstrip section (M17) are simultaneously connected to one end of the eighteenth microstrip section (M18); the other end of the eighteenth microstrip section (M18) is connected to one end of the nineteenth microstrip section (M19); the other end of the nineteenth microstrip section (M19) is connected to one end of the fourth capacitor (C4); and the other end of the fourth capacitor (C4) is connected to the output terminal (Load).

[0063] In this embodiment, a GaN HEMT power device CG2H40010F is selected as the field-effect transistor (FET). Following step 1 of the design method, the target operating frequency band is 0.4–4.3 GHz (i.e., t = 10.75), and the drain efficiency DE is not less than 60%. According to step 2, using… Figure 2 The range of the input nonlinearity factor γ is determined by the drain efficiency DE to be -0.35 ≤ γ ≤ 0, and the range of the resistive factor ξ is 0 ≤ ξ ≤ 0.5. Based on step 3, the optimal load impedance space is determined from the ranges of γ and ξ. Figure 5 As shown in Table 1. According to step 4, adjust and optimize the structural parameters of the output matching network to ensure that the fundamental impedance in the f0 to 2·f0 frequency band is located in the Z1 region of the optimal load impedance space; for the 2·f0 to t·f0 frequency band, it is itself the fundamental wave, and at the same time, it is also the second harmonic of f0 to (t / 2)·f0, so the corresponding impedance should be located in the overlapping region of Z1 and Z2; for the t·f0 to 2t·f0 frequency band, it is the second harmonic of (t / 2)·f0 to t·f0, so the corresponding impedance should be located in the Z2 region. According to step 5, use the designed output matching network as the source pull of the transistor load to determine the source-end fundamental impedance and second harmonic impedance values, as shown in Table 1; the simulation results show that the simulated value of γ varies between -0.14 and -0.26, which is within the expected range of -0.35≤γ≤0. Step 6: Design the input matching network based on the determined source-end fundamental and second harmonic impedances.

[0064] Table 1. Source-end fundamental impedance and second harmonic impedance values ​​at some typical frequencies.

[0065] Fundamental impedance (Ω) 20.0+j22.0 25.4-j1.0 22.6-j10.0 19.8-j6.2 14.0-j4.5 Second harmonic impedance (Ω) 14.9-j0.9 20.2-j2.2 15.0-j9.7 10.1+j25 14.6+j23 γ -0.260 -0.232 -0.168 -0.183 -0.207

[0066] Finally, the structural parameters of the embodiment were determined as follows: the width of the first microstrip line segment (M1) is 1.1 mm and the length is 4.8 mm; the width of the second microstrip line segment (M2) is 2.1 mm and the length is 5.0 mm; the width of the third microstrip line segment (M3) is 0.7 mm and the length is 4.9 mm; the width of the fourth microstrip line segment (M4) is 4.7 mm and the length is 4.8 mm; the width of the fifth microstrip line segment (M5) is 0.9 mm and the length is 4.6 mm; The sixth microstrip section (M6) has a width of 6.4 mm and a length of 4.5 mm; the seventh microstrip section (M7) has a width of 1.1 mm and a length of 4.8 mm; the eighth microstrip section (M8) has a width of 2.0 mm and a length of 2.5 mm; the ninth microstrip section (M9) has a width of 1.9 mm and a length of 2.5 mm; the tenth microstrip section (M10) has a width of 4.9 mm and a length of 10.4 mm; and the eleventh microstrip section (M11) has a width of 1 mm and a length of 1 mm. The 12th microstrip section (M12) has a width of 3.6mm and a length of 7.7mm; the 13th microstrip section (M13) has a width of 1.8mm and a length of 18.1mm; the 14th microstrip section (M14) has a width of 1.0mm and a length of 7.7mm; the 15th microstrip section (M15) has a width of 1.1mm and a length of 11.3mm; the 16th microstrip section (M16) has a width of 2.3mm and a length of 7.7mm. The width of the 17th microstrip line segment (M17) is 5.7 mm; the width of the 17th microstrip line segment (M17) is 1.0 mm and the length is 16.0 mm; the width of the 18th microstrip line segment (M18) is 2.2 mm and the length is 17.6 mm; the width of the 19th microstrip line segment (M19) is 1.4 mm and the length is 14.6 mm; the first capacitor (C1) is 7.4 pF, the second capacitor (C2) is 10 pF, the third capacitor (C3) is 10 pF, and the fourth capacitor (C4) is 7.4 pF.

[0067] Test results are as follows Figure 7 As shown, the results agree well with the simulation results. Within the operating frequency band of 0.4–4.3 GHz, the drain efficiency DE of the embodiment is 49.7–62.8%, and the output power P... out The impedance ranges from 37.4 to 42.92 dBm, and the gain ranges from 8.9 to 12.1 dB.

[0068] The embodiments listed above fully illustrate that the multi-octave power amplifier design method of the present invention introduces a nonlinear factor γ after considering the input nonlinearity effect. The power amplifier designed in this way can operate in multiple octaves while maintaining the advantages of high efficiency, high gain, and high output power, demonstrating significant technological progress. Those skilled in the art will recognize that the embodiments described herein are for the purpose of helping the reader understand the principles of the invention and should be understood as not limiting the scope of protection of the invention to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the essence of the invention, and these modifications and combinations are still within the scope of protection of the present invention.

Claims

1. A design method for a multi-octave power amplifier, characterized in that: Step 1: Given the operating frequency band f0~t·f0 and drain efficiency DE of the multi-octave power amplifier to be designed; Step 2: Determine the value range of nonlinear factor γ and resistive factor ξ based on the relationship between drain efficiency DE and input nonlinear factor γ and resistive factor ξ; Step 3: Determine the optimal load impedance space based on the value range of nonlinear factor γ and resistive factor ξ; Step 4: Determine the output matching network topology; During the optimization of structural parameters, it should be ensured that the fundamental impedance in the f0~2·f0 frequency band is located within the fundamental impedance Z1 region in the optimal load impedance space; For the 2·f0~t·f0 frequency band, it is itself the fundamental frequency and also serves as the second harmonic of f0~(t / 2)·f0, therefore the corresponding impedance should be located in the overlapping region of the fundamental impedance Z1 and the second harmonic impedance Z2; For the t·f0~2t·f0 frequency band, it is (t / 2)·f0~ The second harmonic of t·f0, therefore the corresponding impedance should be located within the second harmonic impedance Z2 region; Step 5, use the designed output matching network as the load of the transistor for source pulling, and determine the source fundamental and second harmonic impedance; ensure that the corresponding nonlinear factor γ value is within the range of γ values ​​determined in Step 2; Step 6, design the input matching network according to the source fundamental and second harmonic impedance.

2. In the multi-octave power amplifier design method according to claim 1, the drain efficiency DE is expressed as: in, DC component The real part of the fundamental component DC component of drain current The real part of the fundamental component Drain current I ds Third harmonic component compensation coefficient α is the conduction angle, β is the cutoff angle, γ is the nonlinearity factor, and ξ is the resistive factor; output power P out Represented as 。 3. In the multi-octave power amplifier design method according to claim 1, the fundamental impedance Z1 is expressed as: in, ξ is the resistivity factor, δ represents the reactance factor, and R opt I represents the optimal load impedance of a Class B power amplifier. 1r Indicates drain current I ds The real part of the fundamental component; the second harmonic impedance Z2 is expressed as Among them, I 2r Indicates drain current I ds The real part of the second harmonic component.

4. The multi-octave power amplifier design method according to claim 1, characterized in that: The input terminal (Source), the first capacitor (C1), the first microstrip line segment (M1), the second microstrip line segment (M2), the third microstrip line segment (M3), the fourth microstrip line segment (M4), the fifth microstrip line segment (M5), and the sixth microstrip line segment (M6) are connected sequentially; the other end of the sixth microstrip line segment (M6) is simultaneously connected to one end of the seventh microstrip line segment (M7) and one end of the eighth microstrip line segment (M8); the other end of the seventh microstrip line segment (M7) is connected to one end of the second capacitor (C2), and the... The other end of capacitor C2 is grounded; the other end of the eighth microstrip section (M8) is connected to the gate of the field-effect transistor (FET); the source of the FET is grounded, and its drain is connected to one end of the ninth microstrip section (M9); the other end of the ninth microstrip section (M9) is connected to one end of the tenth microstrip section (M10), and the other end of the tenth microstrip section (M10) is simultaneously connected to one end of the eleventh microstrip section (M11) and one end of the fourteenth microstrip section (M14); the eleventh microstrip section... The other end of (M11) is connected to one end of the twelfth microstrip section (M12), and the other end of the twelfth microstrip section (M12) is connected to one end of the thirteenth microstrip section (M13); the other end of the fourteenth microstrip section (M14) is simultaneously connected to one end of the fifteenth microstrip section (M15) and one end of the sixteenth microstrip section (M16); the other end of the fifteenth microstrip section (M15) is connected to one end of the third capacitor (C3), and the other end of the third capacitor (C3) is grounded; the sixteenth microstrip section (M11)... The other end of M16 is connected to one end of the seventeenth microstrip section (M17); the other ends of the thirteenth microstrip section (M13) and the seventeenth microstrip section (M17) are simultaneously connected to one end of the eighteenth microstrip section (M18); the other end of the eighteenth microstrip section (M18) is connected to one end of the nineteenth microstrip section (M19); the other end of the nineteenth microstrip section (M19) is connected to one end of the fourth capacitor (C4); and the other end of the fourth capacitor (C4) is connected to the output terminal (Load).

5. The multi-octave power amplifier design method according to claim 1, wherein the operating frequency band is 0.4~4.3GHz, and the drain efficiency DE is not less than 60%; a commonly used microstrip substrate is selected, with a relative permittivity of 3.66 and a substrate thickness of 0.508mm; a GaN HEMT power device CG2H40010F is selected as the field-effect transistor (FET); a set of structural parameters are as follows: the width of the first microstrip line segment (M1) is 1.1mm, and the length is 4.8mm; the width of the second microstrip line segment (M2) is 2.1mm, and the length is 5.0mm; the width of the third microstrip line segment (M3) is 0.7mm, and the length is 4.9mm; the width of the fourth microstrip line segment (M4) is 4.7mm, and the length is 4.8mm; and the width of the fifth microstrip line segment (M5) is 0.9mm, and the length is 4.6mm. m; the sixth microstrip section (M6) has a width of 6.4 mm and a length of 4.5 mm; the seventh microstrip section (M7) has a width of 1.1 mm and a length of 4.8 mm; the eighth microstrip section (M8) has a width of 2.0 mm and a length of 2.5 mm; the ninth microstrip section (M9) has a width of 1.9 mm and a length of 2.5 mm; the tenth microstrip section (M10) has a width of 4.9 mm and a length of 10.4 mm; the eleventh microstrip section (M11) has a width of 1.8 mm and a length of 7.7 mm; the tenth The second microstrip section (M12) has a width of 3.6 mm and a length of 3.6 mm; the thirteenth microstrip section (M13) has a width of 1.8 mm and a length of 18.1 mm; the fourteenth microstrip section (M14) has a width of 1.0 mm and a length of 7.7 mm; the fifteenth microstrip section (M15) has a width of 1.1 mm and a length of 11.3 mm; the sixteenth microstrip section (M16) has a width of 2.3 mm and a length of 5.7 mm; and the seventeenth microstrip section (M17) has a width of 1.0 mm and a length of 16 mm. The width of the eighteenth microstrip line segment (M18) is 2.2 mm and the length is 17.6 mm; the width of the nineteenth microstrip line segment (M19) is 1.4 mm and the length is 14.6 mm; the first capacitor (C1) is 7.4 pF, the second capacitor (C2) is 10 pF, the third capacitor (C3) is 10 pF, and the fourth capacitor (C4) is 7.4 pF; the test results show that within the operating frequency band of 0.4~4.3 GHz, the drain efficiency DE test results are 49.7~62.8%, and the output power P out The impedance ranges from 37.4 to 42.92 dBm, and the gain ranges from 8.9 to 12.1 dB.

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