Simulation method and device of semiconductor structure, readable storage medium and terminal

Abstract

A semiconductor structure simulation method, apparatus, readable storage medium, and terminal are disclosed. The method includes: performing a first-level simulation of the semiconductor structure using baseline process conditions to determine a baseline device compact model for each type of sub-device; for each electrical characteristic parameter, determining electrical characteristic simulation parameters for each type of sub-device under multiple batch conditions, and substituting them into the corresponding baseline device compact model of the sub-device to obtain a batch device compact model for each type of sub-device under each batch condition; for each batch condition, performing a second-level simulation using the batch device compact models of each type of sub-device to determine the simulation values ​​of preset device core parameters of the semiconductor structure; for each device core parameter, determining each fitting coefficient in the fitting model of the device core parameter; and determining the target values ​​of the electrical characteristic parameters of each type of sub-device. This invention can improve the controllability and accuracy of the fitting results.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method and apparatus for simulating semiconductor structures, a readable storage medium, and a terminal. Background Technology

[0002] With the continuous development of digital integrated circuits, memory has become an important component of digital systems. Static Random Access Memory (SRAM) has the characteristic of storing data as long as it is powered, without the need for constant refreshing, and is gaining increasing attention due to its advantages of low power consumption and high speed.

[0003] As memory sizes continue to shrink, SRAM device improvements face greater challenges. Considering the time-consuming and costly nature of semiconductor device processes, simulation tools can be used to perform performance simulations on SRAM, and then the optimal window for device characteristic parameters can be determined in reverse, providing a target for subsequent process and device condition optimization.

[0004] However, in existing technologies, SRAM simulation methods are time-consuming, have low simulation efficiency, and the controllability of fitting results is poor. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a simulation method and apparatus for semiconductor structures, a readable storage medium, and a terminal, which can improve the controllability and accuracy of the fitting results.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a simulation method for a semiconductor structure, wherein the semiconductor structure comprises one or more types of sub-devices; the method includes: performing a first-level simulation of the semiconductor structure using baseline process conditions to determine a baseline device compact model for each type of sub-device, wherein the baseline device compact model includes analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under the baseline process conditions; for each electrical characteristic parameter, determining electrical characteristic simulation parameters for each type of sub-device under multiple batch conditions, and substituting them into the corresponding baseline device compact model of the sub-device to obtain a batch device compact model for each type of sub-device under each batch condition; for each batch condition, performing a second-level simulation using the batch device compact models of each type of sub-device to determine the simulation values ​​of preset device core parameters of the semiconductor structure; for each device core parameter, using the electrical characteristic simulation parameters of each type of sub-device as elements, determining each fitting coefficient in the fitting model of the device core parameter based on the simulation values ​​of the device core parameter; and determining the target values ​​of the electrical characteristic parameters of each type of sub-device based on the target values ​​of the device core parameters and the fitting model.

[0007] Optionally, the method further includes: adjusting the baseline process conditions using the target values ​​of the electrical characteristic parameters of the various sub-devices as the adjustment target.

[0008] Optionally, the semiconductor structure is SRAM; wherein the SRAM includes sub-devices selected from one or more of the following: pull-down diode (PD) sub-device, pull-up diode (PU) sub-device, and transfer diode (PG) sub-device.

[0009] Optionally, the electrical characteristic parameters are selected from one or more of the following: voltage parameter Vt, current parameter Id, and leakage current parameter Ioff.

[0010] Optionally, the device core parameters are selected from one or more of the following: static noise margin SNM, write noise margin WNM, read current Iread, and standby leakage current Istandby.

[0011] Optionally, the first-level simulation of the semiconductor structure using benchmark process conditions to obtain a benchmark device compact model for each type of sub-device includes: using a preset semiconductor process simulation and device simulation TCAD technology, inputting the benchmark process conditions to obtain parameter values ​​of electrical characteristic parameters for each type of sub-device; and using a preset device compact model extraction technology to extract device compact models for each type of sub-device under the benchmark process conditions based on the parameter values ​​of the electrical characteristic parameters, as the benchmark device compact model.

[0012] Optionally, the step of using batch compact models of various sub-devices to perform a second-level simulation to determine the simulation values ​​of the preset device core parameters of the semiconductor structure includes: using preset circuit simulation technology, inputting batch compact models of various sub-devices, and determining the simulation values ​​of the preset device core parameters of the semiconductor structure after simulation.

[0013] Optionally, the sub-devices corresponding to each batch condition are the same, and the electrical characteristic simulation parameters of each sub-device are obtained by adding or subtracting a preset ratio based on the electrical characteristic parameters in the compact model of the reference device; wherein, the preset ratios of addition or subtraction are not exactly the same under different batch conditions.

[0014] Optionally, the step of substituting the corresponding sub-device's reference device compact model to obtain the batch device compact model for each type of sub-device under each batch condition includes: replacing the electrical characteristic parameters in the reference device compact model with the electrical characteristic simulation parameters under that batch condition under each batch condition; and adjusting the analytical expression in the reference device compact model using Design of Experiments (DOE) technology.

[0015] Optionally, for each device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, the fitting coefficients in the fitting model of the device core parameter are determined based on the simulation values ​​of the device core parameter. This includes: under multiple batch conditions, substituting the electrical characteristic simulation parameters of various sub-devices and the simulation values ​​of the device core parameter into the following multivariate fitting polynomial formula, and determining the fitting coefficients:

[0016]

[0017] Where y represents the multivariate fitting function of the core parameters of the device, x1 to x3 represent the electrical characteristic simulation parameters of the first to third type sub-devices, and a ijk The coefficients are used to represent the fitting coefficients, M represents the order of the polynomial, and i, j, k, and M are all integers.

[0018] Optionally, the number of the multivariate fitting polynomial formulas is at least equal to the number of the fitting coefficients; wherein each multivariate fitting polynomial formula is determined based on a single batch condition.

[0019] Optionally, based on the target values ​​of the device core parameters and the fitting model, the target values ​​of the electrical characteristic parameters of the various sub-devices are determined, including: substituting the test values ​​of multiple sets of electrical characteristic parameters into the fitting model to obtain the corresponding test values ​​of multiple sets of device core parameters; using interpolation to determine the mapping relationship between multiple electrical characteristic parameters and the device core parameters; and based on the mapping relationship, determining a set of electrical characteristic parameter values ​​mapped to the target values ​​of the device core parameters as the target values ​​of the electrical characteristic parameters.

[0020] To address the aforementioned technical problems, embodiments of the present invention provide a simulation apparatus for a semiconductor structure, wherein the semiconductor structure comprises one or more types of sub-devices; the apparatus includes: a first simulation module, configured to perform a first-level simulation of the semiconductor structure using reference process conditions to determine a reference device compact model for each type of sub-device, the reference device compact model including analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under reference process conditions; and a batching module, configured to determine, for each electrical characteristic parameter, electrical characteristic simulation parameters of each type of sub-device under multiple batching conditions, and substitute them into the reference device compact model of the corresponding sub-device to obtain... The system comprises: a compact model of each type of sub-device under each batching condition; a second simulation module, used for performing a second-level simulation using the compact model of each type of sub-device for each batching condition to determine the simulation values ​​of the preset device core parameters of the semiconductor structure; a fitting coefficient determination module, used for determining the fitting coefficients in the fitting model of each device core parameter based on the simulation values ​​of the electrical characteristics of each type of sub-device, using the simulation parameters of the electrical characteristics of each type of sub-device as elements; and a target value determination module, used for determining the target values ​​of the electrical characteristic parameters of each type of sub-device based on the target values ​​of the device core parameters and the fitting model.

[0021] To address the aforementioned technical problems, embodiments of the present invention provide a readable storage medium storing a computer program thereon, wherein the computer program, when run by a processor, executes the steps of the above-described semiconductor structure simulation method.

[0022] To address the aforementioned technical problems, this invention provides a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the steps of the above-described semiconductor structure simulation method.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In this embodiment of the invention, a compact model of the reference device can be determined based on only a small number of reference process conditions, without the need for repeated adjustments to process parameters. Then, in batch experiments, the electrical characteristic parameters of various sub-devices are adjusted to obtain electrical characteristic simulation parameters under different batch conditions. After a second-level simulation, the fitting coefficients and the parameter relationships between the device core parameters and individual sub-devices are determined. Compared to adjusting process parameters from the source each time, this effectively reduces simulation time and improves simulation efficiency. Furthermore, since the batch experiments are designed for electrical characteristic parameters, the electrical characteristic simulation parameters have characteristics such as good uniformity of parameter value intervals. Compared to electrical characteristic simulation parameters obtained by adjusting process parameters, which are prone to problems such as extreme values ​​and uneven parameter value intervals, the solution of this embodiment of the invention can effectively improve the controllability and accuracy of the fitting results.

[0025] Furthermore, by using the target values ​​of the electrical characteristic parameters of the various sub-devices as the adjustment target, the baseline process conditions are adjusted. This allows for adjustment of the baseline process conditions after simulation. Compared to the prior art, which designs multiple process conditions to be simulated and then selects process conditions two steps backward based on the device core parameters, resulting in lower reference value, the solution of this embodiment of the invention allows for adjustment of process conditions by simply going back one step based on the target values ​​of the electrical characteristic parameters of the various sub-devices. This provides stronger reference value and helps improve accuracy. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating a semiconductor structure simulation method in the prior art;

[0027] Figure 2 This is a flowchart of a simulation method for a semiconductor structure according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram showing the correspondence between the core parameters of a device and the electrical characteristic parameters of a single type of sub-device in an embodiment of the present invention;

[0029] Figure 4 This is a schematic diagram of the electrical characteristic parameter range of a single type of sub-device corresponding to a device core parameter in an embodiment of the present invention;

[0030] Figure 5 This is a flowchart illustrating a simulation method for another semiconductor structure in an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of a semiconductor structure simulation device according to an embodiment of the present invention. Detailed Implementation

[0032] As mentioned earlier, in the prior art, it is necessary to design multiple sets of process parameters for each SRAM sub-device. For example, process parameters for multiple sub-devices such as pull-down (PD) sub-device, pull-up (PU) sub-device, and transfer (PG) sub-device are designed, such as active area feature size (AACD), gate feature size (GTCD), ion implantation process parameters, etc. Then, for various process conditions, the first-level simulation of a single sub-device is performed to obtain a compact model of the single sub-device.

[0033] In order to perform circuit simulation, it is necessary to first establish a compact model of the sub-device through the first-level simulation (also known as sub-device level simulation). That is, for the various sub-devices supported by the circuit simulation program, there must be a corresponding mathematical model to describe them in the simulation program, so that they can be expressed by computer-executable calculation formulas.

[0034] The device compact model contains analytical expressions for one or more sets of electrical characteristic simulation parameters of the corresponding sub-devices. Specifically, the device compact model can be regarded as transforming the actual sub-device characteristics, including the electrical characteristic parameters of the sub-devices (such as voltage parameters, current parameters, etc.) and their variation with operating voltage and sub-device size, into analytical expressions.

[0035] It should be noted that these analytical expressions can also serve as input for subsequent circuit simulations. Based on the compact device models of each sub-device, a second-level simulation (also known as structural-level simulation) can be performed on the entire semiconductor structure to obtain SRAM core (cell) parameters. Then, multiple sets of SRAM core parameters are fitted, and the fitting results are used to indicate the parameter relationship between the SRAM core parameters and individual sub-devices. Furthermore, the structural-level simulation can also be implemented in conjunction with the circuit structure to which the semiconductor structure belongs.

[0036] Reference Figure 1 , Figure 1 This is a flowchart illustrating a simulation method for a semiconductor structure in the prior art.

[0037] like Figure 1 As shown, each group of experiments corresponds to different process conditions. The experiments are independent of each other. Each group of experiments requires steps such as process simulation of a single sub-device, electrical performance simulation of a single sub-device, extraction of a compact model of a single sub-device, and performance simulation of SRAM core (cell).

[0038] Research has revealed that in existing technologies, when determining the compact model of a single sub-device based on first-level simulation, it is always necessary to rely on the adjusted process parameters for simulation. The resulting electrical performance simulation parameter values ​​necessitate repeated design of process parameters and execution of both single-sub-device process simulation and single-sub-device electrical performance simulation.

[0039] It is particularly important to note that the process simulation and electrical performance simulation of individual sub-devices account for a significant portion of the overall simulation time. Furthermore, the more process parameters there are, the longer the total time required for these two steps becomes. In existing technologies, these two steps are required for every single process condition, resulting in a substantial increase in simulation time.

[0040] The study also found that because the process parameters were adjusted from the source each time, the controllability of the electrical characteristics simulation parameters of each sub-device obtained after simulation was poor. For example, extreme values ​​and uneven parameter value intervals were likely to occur. Based on this, the fitting results also had the problem of poor controllability.

[0041] In this embodiment of the invention, a compact model of the reference device can be determined based on only a small number of reference process conditions, without the need for repeated adjustments to process parameters. Then, in batch experiments, the electrical characteristic parameters of various sub-devices are adjusted to obtain electrical characteristic simulation parameters under different batch conditions. After a second-level simulation, the fitting coefficients and the parameter relationships between the device core parameters and individual sub-devices are determined. Compared to adjusting process parameters from the source each time, this effectively reduces simulation time and improves simulation efficiency. Furthermore, since the batch experiments are designed for electrical characteristic parameters, the electrical characteristic simulation parameters have characteristics such as good uniformity of parameter value intervals. Compared to electrical characteristic simulation parameters obtained by adjusting process parameters, which are prone to problems such as extreme values ​​and uneven parameter value intervals, the solution of this embodiment of the invention can effectively improve the controllability and accuracy of the fitting results.

[0042] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Reference Figure 2 , Figure 2 This is a flowchart of a semiconductor structure simulation method according to an embodiment of the present invention. The semiconductor structure simulation method may include steps S21 to S25:

[0044] Step S21: Perform a first-level simulation on the semiconductor structure using reference process conditions to determine the reference device compact model for each type of sub-device. The reference device compact model includes analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under reference process conditions.

[0045] Step S22: For each electrical characteristic parameter, determine the electrical characteristic simulation parameters of various sub-devices under multiple batch conditions, and substitute them into the corresponding sub-device's reference device compact model to obtain the batch device compact model of each type of sub-device under each batch condition.

[0046] Step S23: For each batching condition, a second-level simulation is performed using a batching device compact model of various sub-devices to determine the simulation values ​​of the preset device core parameters of the semiconductor structure;

[0047] Step S24: For each device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, determine each fitting coefficient in the fitting model of the device core parameter based on the simulation value of the device core parameter;

[0048] Step S25: Based on the target values ​​of the device core parameters and the fitting model, determine the target values ​​of the electrical characteristic parameters of the various sub-devices.

[0049] In the specific implementation of step S21, the semiconductor structure can be the semiconductor device to be simulated, and the semiconductor structure can include one or more types of sub-devices.

[0050] Specifically, the sub-devices of the semiconductor structure can be pre-classified, with each category containing one or more sub-devices. Sub-devices of the same category have similar electrical characteristic parameters (e.g., the mean square error is less than a preset threshold) and can be simulated together.

[0051] Furthermore, the semiconductor structure is SRAM; wherein the SRAM includes sub-devices selected from one or more of the following: pull-down diode (PD) sub-device, pull-up diode (PU) sub-device, and transfer diode (PG) sub-device.

[0052] Specifically, taking SRAM as an example of a semiconductor structure, SRAM has a symmetrical circuit structure and contains three types of sub-devices, with two of each type. Sub-devices of the same type have similar electrical characteristic parameters and can be classified into the same category.

[0053] It should be noted that if multiple sub-devices in the semiconductor structure to be simulated appear to be of the same category but actually have significantly different electrical characteristic parameters, then such sub-devices can be classified into different categories.

[0054] Furthermore, for SRAM, the electrical characteristic parameters can be selected from one or more of the following: voltage parameter Vt, current parameter Id, and leakage current parameter Ioff.

[0055] There can be a many-to-many correspondence between the sub-device categories and their electrical characteristic parameters.

[0056] Taking the electrical characteristic parameter Vt as an example, the electrical characteristic simulation parameter Vt of various SRAM sub-devices can be selected from one or more of the following: Vtpd, Vtpu, Vtpg.

[0057] Wherein, Vtpd is used to represent the voltage parameter Vt of the pull-down transistor (PD), Vtpu is used to represent the voltage parameter Vt of the pull-up transistor (PU), and Vtpg is used to represent the voltage parameter Vt of the pass gate transistor (PG).

[0058] Similarly, the electrical characteristic simulation parameter Id of various SRAM sub-devices can be selected from one or more of the following: Idpd, Idpu, Idpg.

[0059] Wherein, Idpd represents the current parameter Id of PD, Idpu represents the current parameter Id of PU, and Idpg represents the current parameter Id of transmission tube PG.

[0060] The simulation parameter Ioff for the electrical characteristics of various SRAM sub-devices can be selected from one or more of the following: Ioffpd, Ioffpu, Ioffpg.

[0061] Wherein, Ioffpd represents the leakage current parameter Ioff of PD, Ioffpu represents the leakage current parameter Ioff of PU, and Ioffpg represents the leakage current parameter Ioff of transmission transistor PG.

[0062] The device compact model contains analytical expressions for one or more sets of electrical characteristic simulation parameters of the corresponding sub-devices. Specifically, the device compact model can be regarded as transforming the actual sub-device characteristics, including the electrical characteristic parameters of the sub-devices (such as voltage parameters, current parameters, etc.) and their variation with operating voltage and sub-device size, into analytical expressions.

[0063] Furthermore, the step of performing a first-level simulation of the semiconductor structure using benchmark process conditions to obtain a benchmark device compact model for each type of sub-device may include: using preset semiconductor process simulation and device simulation (Technology Computer Aided Design, TCAD) technology, inputting the benchmark process conditions to obtain parameter values ​​of electrical characteristic parameters for each type of sub-device; using preset device compact model extraction technology, extracting device compact models for each type of sub-device under the benchmark process conditions based on the parameter values ​​of the electrical characteristic parameters, and using these as the benchmark device compact models.

[0064] In this embodiment of the invention, by using classes as the basic unit to determine the electrical characteristic parameters of each class of sub-devices, sub-devices with similar electrical characteristic parameter results can be merged, and a compact model of a single device can be extracted, effectively reducing the amount of computation.

[0065] Furthermore, after determining the baseline process conditions, the preset device compact model extraction technique can be implemented using the Mystic module in the Sentaurus device simulation tool.

[0066] Understandably, other conventional tools can also be used to extract compact models of devices.

[0067] In this embodiment of the invention, a compact model of a reference device can be determined based on only a small number of reference process conditions, effectively reducing the amount of simulation.

[0068] Without limitation, a device compact model can be determined based on only a set of sub-devices under a single baseline process condition.

[0069] In the specific implementation of step S22, for each electrical characteristic parameter, the electrical characteristic simulation parameters of various sub-devices under multiple batch conditions are determined, and they are substituted into the corresponding sub-device's reference device compact model to obtain the batch device compact model of each type of sub-device under each batch condition.

[0070] Furthermore, the sub-devices corresponding to each batch condition are consistent, and the electrical characteristic simulation parameters of each sub-device are obtained by adding or subtracting a preset ratio based on the electrical characteristic parameters in the compact model of the reference device; wherein, the preset ratios of addition or subtraction are not exactly the same under different batch conditions.

[0071] In a non-limiting specific embodiment, the electrical characteristic parameters in the compact model of the reference device are Vtpd, Vtpu, and Vtpg. A first batching condition can be set to satisfy one or more of the following: Vtpd+20mV, Vtpu+20mV, and Vtpg+20mV, and a second batching condition can be set to satisfy one or more of the following: Vtpd-20mV, Vtpu-20mV, and Vtpg-20mV.

[0072] Furthermore, the step of substituting the corresponding sub-devices into the benchmark compact model to obtain the batch compact model of each type of sub-device under each batch condition may include: replacing the electrical characteristic parameters in the benchmark compact model with the electrical characteristic simulation parameters under each batch condition; and adjusting the analytical expression in the benchmark compact model using Design of Experiments (DOE) technology.

[0073] Specifically, one can start from the analytical expression of the compact model of the reference device and directly adjust the parameters such as Vt and Id of the device. After adjustment, a compact model corresponding to different parameters can be obtained.

[0074] In a non-limiting specific embodiment, when adjusting Vt of a single device, the adjustment of Vt can be achieved directly using VTH0+ / -deltaVt based on the following analytical expression of Vt:

[0075]

[0076] Where VTH0 represents the threshold voltage of the long trench device under zero substrate bias, Φ s γ is used to represent the semiconductor surface potential, and V is used to represent the substrate bias coefficient. bs Used to indicate substrate bias voltage.

[0077] As can be seen from the above, the VTH0 parameter can always be used as a direct means to adjust Vt. The time required to adjust the electrical characteristic parameters and obtain the adjusted compact model of the device is much less than the time required to extract the compact model of the device.

[0078] Furthermore, to implement the DOE technology, the analytical expressions in the compact model of the reference device can be adjusted using the TTSPro tool, and a batch compact model of the device can be obtained based on the replaced electrical characteristic simulation parameters.

[0079] Understandably, other conventional tools can also be used to obtain a compact model of the batched devices based on the replaced electrical characteristic simulation parameters.

[0080] In this embodiment of the invention, a compact model of batched devices is obtained based on the electrical characteristic simulation parameters under different batch conditions. Compared with the prior art, which adjusts the process parameters from the source to obtain a compact model of a single sub-device under different process conditions, the steps are simplified and the simulation time of the first-level simulation is significantly reduced.

[0081] In the specific implementation of step S23, for each batching condition, a second-level simulation is performed using a batching device compact model of various sub-devices to determine the simulation values ​​of the preset device core parameters of the semiconductor structure.

[0082] Furthermore, the step of performing a second-level simulation using batch compact models of various sub-devices to determine the simulation values ​​of the preset device core parameters of the semiconductor structure may include: using preset circuit simulation technology, inputting batch compact models of various sub-devices, and determining the simulation values ​​of the preset device core parameters of the semiconductor structure after simulation.

[0083] Taking SRAM as an example, the device core parameters are selected from one or more of the following: Static Noise Margin (SNM), Write Noise Margin (WNM), Read Current Iread, and Standby Leakage Current Istandby.

[0084] In practice, at least a portion of the multiple device core parameters of the semiconductor structure can be selected, based on the simulation values ​​of the device core parameters determined by the batch device compact model.

[0085] Furthermore, the preset circuit simulation technology can be implemented using the Hspice tool, which can perform a second-level simulation after inputting a batch of compact device models to determine the simulation values ​​of device core parameters.

[0086] Understandably, other conventional circuit simulation tools can also be used to obtain simulation values ​​of device core parameters based on the compact model of batched devices.

[0087] Combined with reference Figure 3 and Figure 4 , Figure 3 This is a schematic diagram illustrating the correspondence between the core parameters of a device and the electrical characteristic parameters of a single type of sub-device in an embodiment of the present invention. Figure 4 This is a schematic diagram showing the range of electrical characteristic parameters of a single type of sub-device corresponding to the core parameters of a device in an embodiment of the present invention.

[0088] Specifically, Figure 3 This illustrates the correspondence between SRAM core parameters SNM and WNM and various batching conditions for Vt of a single sub-device. Figure 4 The range of Vt for a single sub-device corresponding to the SRAM core parameters SNM and WNM is shown.

[0089] It should be pointed out that, in Figure 3 and Figure 4 The specific applications shown are derived using P-type PU sub-devices, N-type PG sub-devices, and N-type PD sub-devices; however, the embodiments of this application do not limit the types of sub-devices.

[0090] Depend on Figure 3 It can be seen that SNM is mainly determined by the Vt values ​​of PU and PG sub-devices, and is independent of the Vt value of PD sub-devices, while WNM is mainly determined by the Vt value of PG, and is independent of the Vt values ​​of PU and PD.

[0091] Depend on Figure 4It can be seen that if the target values ​​of SNM (148mV~160mV) and WNM (255mV~268MV) need to be met simultaneously, then the Vt deviation values ​​(Delta Vt values) of the three devices PU, PD, and PG can be in the ranges of -20mV~+20mV, 0mV~+20mV, and 0mV~20mV, respectively.

[0092] In the specific implementation of step S24, for each device core parameter, the electrical characteristic simulation parameters of various sub-devices are used as elements, and the fitting coefficients in the fitting model of the device core parameter are determined according to the simulation value of the device core parameter.

[0093] Furthermore, for each device core parameter, the step of determining the fitting coefficients in the fitting model of the device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, may include: under multiple batch conditions, substituting the electrical characteristic simulation parameters of various sub-devices and the simulation values ​​of the device core parameter into the following multivariate fitting polynomial formula, and determining the fitting coefficients:

[0094]

[0095] Where y represents the multivariate fitting function of the core parameters of the device, x1 to x3 represent the electrical characteristic simulation parameters of the first to third type sub-devices, and a ijk The coefficients are used to represent the fitting coefficients, M is used to represent the order of the polynomial, and i, j, k, and M are all integers. The y in different multivariate fitting polynomial formulas adopts the simulation value of the device core parameters under the corresponding batch conditions.

[0096] In a non-limiting specific embodiment, taking a polynomial order M=1 as an example, with the possible values ​​of i being 0 or 1, j being 0 or 1, and k being 0 or 1, the above multivariate fitting polynomial formula can be transformed into:

[0097] y=a0+a1x1+a2x2+a3x3+a4x1x2+a5x1x3+a6x2x3+a7x1x2x3

[0098] Where y represents the ternary fitting function of the core parameters of the device, x1 to x3 represent the electrical characteristic simulation parameters of the first to third type sub-devices, and a0 to a7 represent the fitting coefficients.

[0099] Furthermore, the number of the multivariate fitting polynomial formulas is at least equal to the number of the fitting coefficients; wherein each multivariate fitting polynomial formula is determined based on a single batch condition.

[0100] Based on the specific embodiment of polynomial order M=1 described above, with 8 fitting coefficients, 8 multivariate fitting polynomial formulas are used. By substituting the electrical characteristic simulation parameters under each batch condition and the simulation values ​​of the device core parameters under the corresponding batch conditions into the different multivariate fitting polynomial formulas, the 8 fitting coefficients can be determined.

[0101] Furthermore, nine or more multivariate fitting polynomial formulas can be used to determine eight fitting coefficients in multiple rounds, and then the mean value of each fitting coefficient can be calculated to improve the accuracy of the fitting coefficient determination.

[0102] In the specific implementation of step S25, the target values ​​of the electrical characteristic parameters of the various sub-devices are determined based on the target values ​​of the device core parameters and the fitting model.

[0103] Furthermore, the step of determining the target values ​​of the electrical characteristic parameters of the various sub-devices based on the target values ​​of the device core parameters and the fitting model may include: substituting the test values ​​of multiple sets of electrical characteristic parameters into the fitting model to obtain the corresponding test values ​​of multiple sets of device core parameters; using interpolation to determine the mapping relationship between multiple electrical characteristic parameters and the device core parameters; and based on the mapping relationship, determining a set of electrical characteristic parameter values ​​mapped to the target values ​​of the device core parameters as the target values ​​of the electrical characteristic parameters.

[0104] In this embodiment of the invention, by presetting multiple sets of test values ​​for electrical characteristic parameters and obtaining the test values ​​of the corresponding device core parameters for each set, a discrete mapping relationship between the device core parameters and the set of electrical characteristic parameter values ​​can be obtained. Then, by using an interpolation method, a set of electrical characteristic parameter values ​​mapped to the target value of the device core parameters can be deduced from the discrete mapping relationship, thereby realizing the reverse deduction from the target value of the device core parameters to the target value of the set of electrical characteristic parameters.

[0105] In this embodiment of the invention, a compact model of the reference device can be determined based on only a small number of reference process conditions, without the need for repeated adjustments to process parameters. Then, in batch experiments, the electrical characteristic parameters of various sub-devices are adjusted to obtain electrical characteristic simulation parameters under different batch conditions. After a second-level simulation, the fitting coefficients and the parameter relationships between the device core parameters and individual sub-devices are determined. Compared to adjusting process parameters from the source each time, this effectively reduces simulation time and improves simulation efficiency. Furthermore, since the batch experiments are designed for electrical characteristic parameters, the electrical characteristic simulation parameters have characteristics such as good uniformity of parameter value intervals. Compared to electrical characteristic simulation parameters obtained by adjusting process parameters, which are prone to problems such as extreme values ​​and uneven parameter value intervals, the solution of this embodiment of the invention can effectively improve the controllability and accuracy of the fitting results.

[0106] Reference Figure 5 , Figure 5 This is a flowchart illustrating another semiconductor structure simulation method in an embodiment of the present invention.

[0107] like Figure 5 As shown, only a small number of reference process conditions are needed to determine the compact model of the reference device, even in Figure 5 The schematic diagram shown only requires simulation of the process of a single sub-device and the electrical characteristics of a single sub-device under a single reference process condition, and then the compact model of the single reference device is determined.

[0108] Then, the electrical characteristics simulation of individual sub-devices under multiple batch conditions is provided. As mentioned earlier, each batch condition can be determined by adding / subtracting preset ratios.

[0109] Then, individual device parameters are adjusted on the device compact model under the baseline conditions to obtain the device compact models of individual sub-devices under each batch condition. As mentioned earlier, the time required to adjust the electrical characteristic parameters and obtain the adjusted device compact model is much less than the time required to extract the device compact model.

[0110] Finally, SRAM core performance simulation is performed, and data analysis is conducted based on the simulation results to determine the target values ​​of the electrical characteristic parameters of the sub-devices.

[0111] In a non-restrictive specific application process, for Figure 1 and Figure 5 The simulation times of the shown methods were compared:

[0112] Existing technology simulation time = (n+1)×(Tprocess+Tdevice+Tmodel+Tcell)

[0113] Simulation time for this invention = (Tprocess + Tdevice + Tmodel + Tcell) + n × (Tretarget + Tcell)

[0114] Where n is the number of batch experiments (also known as the number of DOE conditions), Tprocess is used to represent the process simulation time, Tdevice is used to represent the electrical characteristic simulation time, Tmodel is used to represent the compact model extraction time, Tcell is used to represent the SRAM core performance simulation time, and Tretarget is used to represent the time to adjust from the baseline device compact model to the batch device compact model.

[0115] For example, using a 28nm 6TSRAM with n=100, and Tprocess, Tdevice, Tmodel, Tcell, and Tretarget being 5hrs, 1hrs, 4hrs, 0.2hrs, and 0.2hrs respectively, the simulation times required by the prior art and the present invention are 1030.2hrs and 50.2hrs respectively, which is reduced to 5% of the original time.

[0116] Furthermore, the method may also include: adjusting the baseline process conditions using the target values ​​of the electrical characteristic parameters of the various sub-devices as the adjustment target.

[0117] In this embodiment of the invention, the target values ​​of the electrical characteristic parameters of the various sub-devices are used as the adjustment targets to adjust the baseline process conditions. This allows for adjustment of the baseline process conditions after simulation. Compared to the prior art, which designs multiple process conditions to be simulated and then selects process conditions by working backward two steps based on the device core parameters, resulting in lower reference value, the solution of this embodiment of the invention allows for adjustment of process conditions by working backward one step based on the target values ​​of the electrical characteristic parameters of the various sub-devices. This provides stronger reference value and helps improve accuracy.

[0118] Reference Figure 6 , Figure 6 This is a schematic diagram of a semiconductor structure simulation device according to an embodiment of the present invention. The semiconductor structure simulation device may include:

[0119] The first simulation module 61 is used to perform a first-level simulation of the semiconductor structure using reference process conditions to determine a reference device compact model for each type of sub-device. The reference device compact model includes analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under reference process conditions.

[0120] Batch module 62 is used to determine the electrical characteristic simulation parameters of various sub-devices under multiple batch conditions for each electrical characteristic parameter, and substitute them into the corresponding sub-device's reference device compact model to obtain the batch device compact model of each type of sub-device under each batch condition.

[0121] The second simulation module 63 is used to perform a second-level simulation using a batch compact model of various sub-devices for each batch condition, so as to determine the simulation values ​​of the preset device core parameters of the semiconductor structure.

[0122] The fitting coefficient determination module 64 is used to determine each fitting coefficient in the fitting model of the device core parameter for each device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, based on the simulation value of the device core parameter.

[0123] The target value determination module 65 is used to determine the target values ​​of the electrical characteristic parameters of the various sub-devices based on the target values ​​of the device core parameters and the fitting model.

[0124] For the principles, specific implementation, and beneficial effects of the simulation device for this semiconductor structure, please refer to the relevant description of the simulation method for semiconductor structures mentioned above; it will not be repeated here.

[0125] This invention also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, performs the steps of the above-described method. The readable storage medium may be a computer-readable storage medium, such as non-volatile or non-transitory memory, and may also include optical discs, hard disk drives, solid-state drives, etc.

[0126] This invention also provides a terminal, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it performs the steps of the above-described method. The terminal includes, but is not limited to, terminal devices such as servers, mobile phones, computers, and tablet computers.

[0127] Specifically, in this embodiment of the invention, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0128] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0129] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0130] In the embodiments of this application, "multiple" refers to two or more.

[0131] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0132] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for simulating semiconductor structures, characterized in that, The semiconductor structure includes one or more types of sub-devices; The method includes: The semiconductor structure is simulated at the first level using reference process conditions to determine the reference device compact model for each type of sub-device. The reference device compact model contains analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under reference process conditions. For each electrical characteristic parameter, determine the electrical characteristic simulation parameters of various sub-devices under multiple batch conditions, and substitute them into the corresponding sub-device's benchmark compact model to obtain the batch compact model of each type of sub-device under each batch condition. For each batching condition, a second-level simulation is performed using a batching device compact model of various sub-devices to determine the simulation values ​​of the preset device core parameters of the semiconductor structure. For each device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, the fitting coefficients in the fitting model of the device core parameter are determined based on the simulation values ​​of the device core parameter. Based on the target values ​​of the device core parameters and the fitting model, the target values ​​of the electrical characteristic parameters of the various sub-devices are determined; Among them, the sub-devices corresponding to each batch condition are the same, and the electrical characteristic simulation parameters of each sub-device are obtained by adding or subtracting a preset ratio based on the electrical characteristic parameters in the compact model of the reference device. The preset proportions for increasing or decreasing are not exactly the same under different batch conditions.

2. The method according to claim 1, characterized in that, The method further includes: The baseline process conditions are adjusted based on the target values ​​of the electrical characteristic parameters of the various sub-devices.

3. The method according to claim 1, characterized in that, The semiconductor structure is SRAM; The SRAM includes sub-devices selected from one or more of the following: Pull-down diode (PD) sub-device, pull-up diode (PU) sub-device, and transmission diode (PG) sub-device.

4. The method according to claim 3, characterized in that, The electrical characteristic parameters are selected from one or more of the following: Voltage parameter Vt, current parameter Id, and leakage current parameter Ioff.

5. The method according to claim 3 or 4, characterized in that, The device core parameters are selected from one or more of the following: Static noise margin SNM, write noise margin WNM, read current Iread, and standby leakage current Istandby.

6. The method according to claim 1, characterized in that, The first-level simulation of the semiconductor structure using baseline process conditions to obtain a baseline compact model of each type of sub-device includes: Using preset semiconductor process simulation and device simulation TCAD technology, the baseline process conditions are input to obtain the parameter values ​​of the electrical characteristic parameters of each type of sub-device; Using a preset device compact model extraction technique, device compact models of various sub-devices under the reference process conditions are extracted based on the parameter values ​​of the electrical characteristic parameters, and used as the reference device compact model.

7. The method according to claim 1 or 6, characterized in that, The second-level simulation, which uses batch compact models of various sub-devices to determine the simulation values ​​of preset device core parameters of the semiconductor structure, includes: Using a pre-defined circuit simulation technique, batch compact models of various sub-devices are input to determine the simulation values ​​of the preset device core parameters of the semiconductor structure after simulation.

8. The method according to claim 1, characterized in that, The step of substituting the corresponding sub-devices into the baseline device compact model to obtain the batch device compact model for each type of sub-device under each batch condition includes: Under each batch condition, the electrical characteristic parameters in the compact model of the reference device are replaced with the electrical characteristic simulation parameters under that batch condition; The analytical expressions in the compact model of the reference device were adjusted using the design of experiments (DOE) technique.

9. The method according to claim 1, characterized in that, For each device core parameter, using the electrical characteristic simulation parameters of various sub-devices as elements, the fitting coefficients in the fitting model of the device core parameter are determined based on the simulation values ​​of the device core parameter, including: Under multiple batch conditions, the simulated electrical characteristic parameters of various sub-devices and the simulated values ​​of device core parameters are substituted into the following multivariate fitting polynomial formula, and the fitting coefficients are determined: ； Where y represents the multivariate fitting function of the core parameters of the device, x1 to x3 represent the electrical characteristic simulation parameters of the first to third type sub-devices, and a ijk The coefficients are used to represent the fitting coefficients, M represents the order of the polynomial, and i, j, k, and M are all integers. In different multivariate fitting polynomial formulas, y uses the simulated values ​​of the device core parameters under the corresponding batch conditions.

10. The method according to claim 9, characterized in that, The number of the multivariate fitting polynomial formulas is at least equal to the number of the fitting coefficients; Each multivariate fitting polynomial formula is determined based on a single batch condition.

11. The method according to claim 1, characterized in that, Based on the target values ​​of the device core parameters and the fitting model, the target values ​​of the electrical characteristic parameters of the various sub-devices are determined, including: Substitute the test values ​​of multiple sets of electrical characteristic parameters into the fitting model to obtain the test values ​​of the corresponding multiple sets of device core parameters; The mapping relationship between multiple electrical characteristic parameters and the core parameters of the device is determined by interpolation. Based on the mapping relationship, a set of electrical characteristic parameter values ​​that are mapped to the target values ​​of the device core parameters are determined as the target values ​​of the electrical characteristic parameters.

12. A semiconductor structure simulation device, characterized in that, The semiconductor structure includes one or more types of sub-devices; The device includes: The first simulation module is used to perform a first-level simulation of the semiconductor structure using reference process conditions to determine a reference device compact model for each type of sub-device. The reference device compact model includes analytical expressions for one or more electrical characteristic parameters of the corresponding sub-device under reference process conditions. The batching module is used to determine the electrical characteristic simulation parameters of various sub-devices under multiple batching conditions for each electrical characteristic parameter, and substitute them into the corresponding sub-device's baseline compact model to obtain the batching compact model of each type of sub-device under each batching condition. The second simulation module is used to perform a second-level simulation using a batch compact model of various sub-devices for each batching condition, so as to determine the simulation values ​​of the preset device core parameters of the semiconductor structure. The fitting coefficient determination module is used to determine the fitting coefficients in the fitting model of each device core parameter based on the simulation values ​​of the electrical characteristics of various sub-devices, for each device core parameter. The target value determination module is used to determine the target values ​​of the electrical characteristic parameters of the various sub-devices based on the target values ​​of the device core parameters and the fitting model. Among them, the sub-devices corresponding to each batch condition are the same, and the electrical characteristic simulation parameters of each sub-device are obtained by adding or subtracting a preset ratio based on the electrical characteristic parameters in the compact model of the reference device. The preset proportions for increasing or decreasing are not exactly the same under different batch conditions.

13. A readable storage medium having a computer program stored thereon, characterized in that, The computer program, when run by a processor, performs the steps of the simulation method for the semiconductor structure according to any one of claims 1 to 11.

14. A terminal comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the simulation method for the semiconductor structure according to any one of claims 1 to 11.

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