Layout design method and device of silicon-based infrared detector array chip and medium

Abstract

The application discloses a layout design method and device of a silicon-based infrared detector array chip and a medium, and the method comprises the following steps: creating a first layout file, calling a standard Schottky layout, and flattening the standard Schottky layout; according to a preset layout design rule, the sizes of a P-type active region, an infrared absorption region, an N-type active region, an N well and a protection ring of the Schottky are respectively adjusted, and DRC verification is performed; the size adjustment of the P-type active region, the N-type active region, the N well and the protection ring is the minimum size in the rule; based on the preset layout design rule, an infrared antenna structure directly above the infrared absorption region is designed by using an M1 metal layer; the P-type active region, the N-type active region and the protection ring are connected by using a contact hole, and the contact hole is respectively connected to the M1 metal layer; in the M1 metal layer, all N electrodes are connected with the protection ring to form P poles and N poles. The application can make a chip with a larger size in the same layout area, and reduces the process production cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout design technology, and in particular to a layout design method, apparatus and medium for a silicon-based infrared detector array chip. Background Technology

[0002] The layout of an integrated circuit (IC) is the process by which IC designers transform their designed and simulated optimized circuits into a series of geometric combinations. These geometric combinations are composed of different layers of geometry, with each layer corresponding to a specific layout layer, and each layer corresponding to a different process step. Layout design is the process of converting circuit components and their interconnections into a layout form, typically accomplished using specialized design tools. It encompasses all physical properties of the device, including IC size and layer topology definitions. It not only relates to the functionality of the IC but also plays a decisive role in its performance and cost.

[0003] In recent years, with the development of infrared imaging technology, the materials of infrared detectors have evolved from indium antimonide to mercury cadmium telluride, and then to type-2 superlattices. Imaging scales have increased from 320×265 to 640×512, and then to 1280×1024, while pixel pitch has decreased from 30µm to 15µm, and then to 10µm. The types, specifications, and sizes of infrared detectors are constantly evolving and iterating. Therefore, developing silicon-based infrared detector array chips that are well-compatible with standard silicon-based CMOS processes can provide standard process assurance for large-area arrays and large-scale development. Furthermore, under the same process conditions, how to reduce pixel area while protecting equivalent infrared absorption, and achieve miniaturized layout design of infrared detector chips, thereby improving the integration density of infrared detector chips and reducing chip manufacturing costs, has become an important research direction in the practical development and application of silicon-based infrared detector chip integrated circuits. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a layout design method, apparatus and medium for silicon-based infrared detector array chips.

[0005] Therefore, the technical solution of the present invention is:

[0006] According to a first aspect of the present invention, a layout design method for a silicon-based infrared detector array chip is provided. The method includes: creating a first layout file, calling a standard Schottky layout, and flattening the standard Schottky layout; adjusting the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky array according to a preset layout design rule, and performing DRC verification; wherein the size of the infrared absorption region is adjusted to the maximum size in the preset layout design rule, and is used to absorb infrared light waves to generate photoelectrons; the dimensions of the P-type active region, N-type active region, N-well, and guard ring are adjusted to the minimum size in the rule; based on the preset layout design rule, designing an infrared antenna structure directly above the infrared absorption region using an M1 metal layer; connecting the P-type active region, N-type active region, and guard ring using contact holes, and respectively connecting them to the M1 metal layer; and connecting all N electrodes to the guard ring in the M1 metal layer to form P and N electrodes.

[0007] According to a second aspect of the present invention, a layout design apparatus for a silicon-based infrared detector array chip is provided. The apparatus includes a processor configured to: create a first layout file, call a standard Schottky layout, and flatten the standard Schottky layout; adjust the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky array according to a preset layout design rule, and perform DRC verification; wherein the size of the infrared absorption region is adjusted to the maximum size in the preset layout design rule, and is used to absorb infrared light waves to generate photoelectrons; the dimensions of the P-type active region, N-type active region, N-well, and guard ring are adjusted to the minimum size in the rule; based on the preset layout design rule, design an infrared antenna structure directly above the infrared absorption region using an M1 metal layer; connect the P-type active region, N-type active region, and guard ring using contact holes, and respectively connect them to the M1 metal layer; in the M1 metal layer, connect all N electrodes to the guard ring to form P and N electrodes.

[0008] According to a third aspect of the present invention, a non-transitory computer-readable storage medium is provided that stores instructions which, when executed by a processor, perform a layout design method for a silicon-based infrared detector array chip as described in any embodiment of the present invention.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0010] Traditional design methods, which use existing standard components from the process library for arraying, are often limited by PDK rules, resulting in design dimensions that do not meet requirements and making it impossible to design a layout that meets design requirements. This invention flattens the Schottky MOS transistors in the standard cell layout, modifies the layout design of the standard cell library area, and combines it with the standard cell layout design. While maintaining the device structure and circuit design, this greatly increases the design flexibility of the layout and avoids the constraints of some layout design rules. Secondly, the M1 metal layer in traditional design methods cannot be structured; the design method of this invention can make the M1 layer into a metal antenna to manipulate and control the incident light field. Finally, overlapping the top, bottom, left, and right guard rings enables miniaturization of the infrared detector array design. This results in a smaller area than the original design layout, allowing for the fabrication of larger chips within the same layout area, reducing manufacturing costs, and demonstrating engineering practicality and scientific merit. Furthermore, the layout design method that modifies the standard cell library area, due to improvements at mature process nodes, ensures chip yield and has a significant time advantage over traditional processes. Attached Figure Description

[0011] In drawings that are not necessarily drawn to scale, the same reference numerals may describe similar parts in different views. The same reference numerals with or without letter suffixes may indicate different instances of similar parts. The drawings generally illustrate various embodiments by way of example rather than limitation and, together with the description and claims, serve to explain embodiments of the invention. Where appropriate, the same reference numerals are used in all drawings to refer to the same or similar parts. Such embodiments are illustrative and not intended to be exhaustive or exclusive embodiments of the apparatus or method.

[0012] Figure 1 This is a flowchart of a layout design method for a silicon-based infrared detector array chip according to an embodiment of the present invention, including steps S1-S5.

[0013] Figure 2 This is a flowchart of a layout design method for a silicon-based infrared detector array chip according to an embodiment of the present invention, including step S6.

[0014] Figure 3 This is a flowchart of a layout design method for a silicon-based infrared detector array chip according to an embodiment of the present invention, including step S7.

[0015] Figure 4 This is a flowchart of a layout design method for a silicon-based infrared detector array chip according to an embodiment of the present invention, including steps S8-S10.

[0016] Figure 5This is a standard minimum area Schottky MOS transistor layout according to an embodiment of the present invention.

[0017] Figure 6 This is a modified minimum area Schottky MOS transistor layout according to an embodiment of the present invention.

[0018] Figure 7 This is a schematic diagram showing the positions of the N-doped region, the P-doped region, and the DIFF region according to an embodiment of the present invention.

[0019] Figure 8 This is a schematic diagram showing the positions of the N-doped region and the DIFF region (or the P-doped region and the DIFF region) according to an embodiment of the present invention.

[0020] Figure 9 This is a schematic diagram showing the positions of the two DIFF regions according to an embodiment of the present invention.

[0021] Figure 10 This is a schematic diagram showing the positions of the N-well region and the DIFF region according to an embodiment of the present invention.

[0022] Figure 11 This is a schematic diagram showing the distance between the contact hole and the DIFF area according to an embodiment of the present invention.

[0023] Figure 12 This is a schematic diagram illustrating the minimum width of the DIFF area according to an embodiment of the present invention.

[0024] Figure 13 This is a schematic diagram showing the minimum width of the N-doped and P-doped regions according to an embodiment of the present invention.

[0025] Figure 14 This is a structural diagram of the SBDDMY and DIFF layers of a silicon-based Schottky junction according to an embodiment of the present invention.

[0026] Figure 15 This is a structural diagram of the N-doped region of a silicon-based Schottky junction according to an embodiment of the present invention.

[0027] Figure 16 This is a schematic diagram of the N-region DIFF layer and the P-region PIMP layer (left) according to an embodiment of the present invention; and the P-region DIFF layer and the PIMP layer (right).

[0028] Figure 17 This diagram shows the minimum and maximum dimensions of the DIFF layer in the P-doped region according to an embodiment of the present invention.

[0029] Figure 18 This is a diagram showing the relationship between the layers of the Guard ring doped region according to an embodiment of the present invention.

[0030] Figure 19This is a diagram showing the spacing relationship between the SBDDMY layer and the Guard ring area DIFF layer according to an embodiment of the present invention.

[0031] Figure 20 This is a schematic diagram showing the relationship between the two PIMP layers in the Guard ring region according to an embodiment of the present invention.

[0032] Figure 21 This is a schematic diagram showing the gap relationship between two adjacent NWELL layers according to an embodiment of the present invention.

[0033] Figure 22 This diagram illustrates the case where the guard ring regions of two adjacent devices are combined and shared according to an embodiment of the present invention.

[0034] Figure 23 This is a layout of a non-overlapping Schottky MOS transistor array according to an embodiment of the present invention.

[0035] Figure 24 This is a layout of a Guardring-overlapping Schottky MOS transistor array according to an embodiment of the present invention.

[0036] Figure 25 This is a chip cell layout including an optimized Schottky MOS transistor array according to an embodiment of the present invention.

[0037] Figure 26 This is a chip array layout including an optimized Schottky MOS transistor array according to an embodiment of the present invention.

[0038] Figure 27 The IV curve of the chip designed according to the design method of the present invention. Detailed Implementation

[0039] The following examples are merely illustrative of the invention, and the scope of the invention is not limited to the embodiments described. Therefore, any non-essential modifications and adjustments made by those skilled in the art based on the above description to other embodiments are still within the scope of protection of this invention.

[0040] The invention will now be further described with reference to the accompanying drawings.

[0041] This invention provides a layout design method for a silicon-based infrared detector array chip, such as... Figure 1 As shown, it includes the following steps:

[0042] S1: Create the first layout file, call the factory-standardized Schottky layout, and flatten the standard Schottky layout.

[0043] like Figure 5The image shows the layout of a standard minimum area Schottky MOSFET. Figure 6 The image shows the modified minimum area Schottky MOSFET layout.

[0044] S2: According to the preset layout design rules, adjust the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky diode, and perform DRC verification. Specifically, the infrared absorption region must be adjusted to the maximum size specified in the rules to absorb infrared light waves and generate photoelectrons; other regions are adjusted to the minimum size specified in the rules.

[0045] In some embodiments, the preset layout design rules include the following rules:

[0046] 1) such as Figure 7 As shown, the N-doped and P-doped regions need to extend the DIFF region (active region) by at least 0.18 micrometers.

[0047] 2) such as Figure 8 As shown, the N-doped region and the DIFF region (or the P-doped region and the DIFF region) are at least 0.26 micrometers apart.

[0048] 3) such as Figure 9 As shown, according to rules 1) and 2), the two DIFF regions must be at least 0.18 + 0.26 = 0.44 micrometers apart.

[0049] 4) such as Figure 10 As shown, the N-well region needs to extend the DIFF region by at least 0.43 micrometers.

[0050] 5) such as Figure 11 As shown, the minimum size of the CONT contact hole is 0.22 × 0.22 micrometers, and the minimum extension distance from the DIFF area is 0.1 micrometers.

[0051] 6) such as Figure 12 As shown, the minimum width of the DIFF region is 0.22 micrometers.

[0052] 7) such as Figure 13 As shown, the minimum width of the N-doped and P-doped regions is 0.44 micrometers.

[0053] 8) For example Figure 14 As shown, the N well and the SBDDMY layer (red box) must completely overlap to ensure the integrity of the Schottky junction; the SBDDMY layer and the DIFF layer must maintain a spacing of 0.8 μm, and the area within the SBDDMY layer is the design and research range for the Schottky junction.

[0054] 9) For example Figure 15As shown, in the N-doped region, the width of the DIFF active region is 0.42 μm; the minimum size of the CONT contact hole is 0.22 μm × 0.22 μm, and the minimum extension distance between it and the DIFF region is 0.1 μm.

[0055] 10) such as Figure 16 and 17 As shown, in the P-doped region, the PIMP layer and DIFF layer (or NIMP layer and DIFF layer) must be at least 0.26 μm apart, and the boundary distance between the active region DIFF layer and PIMP layer must be equal to 0.22 μm. The width of the active region DIFF layer is a minimum of 2 μm and a maximum of 4 μm. The length of the DIFF layer is a minimum of 4 μm and a maximum of 16 μm.

[0056] 11) such as Figure 18 and 19 As shown, in the guard ring doped region, the narrowest width of the PIMP layer (purple frame) is 0.44 μm, and the minimum spacing between the PIMP and DIFF layers is 0.02 μm; the guard ring region must be continuous. The minimum spacing between the DIFF layer and the SBDDMY layer within the guard ring doped region is 0.43 μm. The outermost ring of the guard ring region must be marked with an RFDUMMY layer, and the minimum distance between this marking layer and the PIMP layer is 0.02 μm. The minimum spacing between the SBDDMY layer (or NWELL layer) and the DIFF layer in the guard ring region is 0.43 μm.

[0057] 12) such as Figure 20 and 21 As shown, each detector needs to use a guard ring as a protective ring. The gap between the PIMP layers of the guard ring of two adjacent unit devices is greater than or equal to 0.44um, and the gap between different NWELLs (white boxes) must be no less than 1.4um.

[0058] 13) such as Figure 22 As shown, in order to minimize the non-infrared sensitive area of ​​the detection unit device, this study merges and shares the guard ring areas of two adjacent devices within a limited pixel size, so that the metal micro / nano structure has enough area to achieve photoelectric coupling and conversion with light.

[0059] DRC (Geometric Design Rule Check) performs a geometric space check on an IC layout to ensure that the circuitry can be implemented using a specific manufacturing process. DRC requires two inputs: a completed layout (usually in GDS format) and a design rule file, typically provided by the manufacturer. The verification process is as follows:

[0060] 1. Prepare the map GDS file

[0061] 2. Open the Calibre DRC interface, and select the rule file and the path to run DRC in the Calibre DRC window;

[0062] 3. Enter the GDS name and the TOP CELL name in the Calibre DRC window;

[0063] 4. Click "Rus DRC" to run DRC. Verify the DRC code using the PDK.

[0064] 5. If there are designs in the layout that do not conform to the rules, the DRC results will display the specific details of the violations. Double-clicking the result will highlight the violating area directly in the layout. The output will contain an information file with DRC errors based on the verification results.

[0065] 6. Modify the layout according to the information prompts, save the GDS file, and perform DRC verification again until there are no error messages.

[0066] 7. DRC verification complete.

[0067] Making full use of this tool can greatly benefit layout design work, reduce the workload of layout design staff, significantly shorten the design cycle, and obtain accurate and stable results.

[0068] DRC verification content typically includes:

[0069] (1) Checking and automatically optimizing metal density.

[0070] (2) In the layout, the minimum gap between components and elements, line width, via distance, via size and other content related to the manufacturing process.

[0071] (3) Routing constraints, such as total length, width, wiring, etc.

[0072] (4) Rules for specific layers and specific networks, such as difference pair rules.

[0073] S3: Based on the preset layout design rules, design the infrared antenna structure directly above the infrared absorption area using the M1 metal layer.

[0074] S4: Connect to the P-type active area, N-type active area and guard ring through the contact hole, and conduct them to the M1 metal layer respectively.

[0075] S5: In the M1 metal layer, connect all the N electrodes to the guard ring to form the P and N electrodes.

[0076] In some embodiments, such as Figure 2 As shown, step S6 can be added after step S5:

[0077] S6: The P-type active region, infrared absorption region, and N-type active region are set as a photoelectric detection combination; the combination is called multiple times and arranged in a horizontal array in the same N-well and guard ring to realize the horizontal arraying of the infrared detection unit.

[0078] In some embodiments, such as Figure 3 As shown, step S7 is included after step S5 or S6:

[0079] S7: Create a second layout file and call the first layout file to combine them into an array device. The array period is designed to be the difference between the overall size of the first layout file and the size of the guard ring, so that the guard rings on the top, bottom, left and right are overlapped, realizing the miniaturization design when the infrared detector group is arrayed.

[0080] like Figure 23 The diagram shows the layout of a non-overlapping Schottky MOS transistor array with guardring, as shown below. Figure 24 The image shows the layout of a Guardring-overlapping Schottky MOS transistor array.

[0081] In some embodiments, such as Figure 4 As shown, steps S8-10 are included after step S7:

[0082] S8: In the M1 metal layer, the N poles of the first layout unit devices in the second layout file are connected to form a common N electrode; in the M2-M4 metal layers, the common N electrode and the P electrode of each pixel are connected to the outer ring of the infrared detector array by using the layout design of metal vias and conductors in each layer.

[0083] S9: Windowing is applied to the common N-electrode and P-electrode array to facilitate interconnection between the silicon-based infrared detector array chip and the readout circuit.

[0084] S10: Draw polysilicon below the outer electrode ring and perform DRC verification.

[0085] In some embodiments, the infrared antenna structure includes a grating antenna, a rectangular antenna, a log-periodic antenna, a planar helical antenna, a fractal antenna, etc.

[0086] In some embodiments, the contact hole must simultaneously form electrical contact with the infrared absorption region and the P-type active region.

[0087] In some embodiments, the infrared absorption region is an infrared-sensitive silicide material such as cobalt silicide, platinum silicide, or nickel silicide.

[0088] In some embodiments, 1 to 16 of the photodetector assemblies can be invoked when they are laterally arrayed in the same N-well and guard ring.

[0089] In some embodiments, the infrared antenna structure must not be obstructed during layout design.

[0090] The following embodiments of the present invention will be combined with specific examples to further illustrate the feasibility and progressiveness of the method.

[0091] An infrared detection sensing unit is designed, utilizing the Schottky junction at the metal-silicon interface on a silicon-based substrate to achieve efficient interlayer electron transition excitation, thereby completing a highly efficient photoelectric conversion process. To maximize the infrared sensitive area at the metal-silicon interface, research was conducted on the layout design method of silicon-based infrared detection chips. Through the layout design method of this invention, the utilization of the infrared sensitive area is maximized as much as possible.

[0092] A 300,000-pixel array of infrared absorption sensors was designed using the 0.18RF process in silicon-based semiconductor technology. Flip-chip interconnection between the sensing chip and the existing readout circuit chip was then achieved through windowing. The array design, based on the regularity of the sensing unit devices, required a one-to-one correspondence between the pixel sizes of the infrared sensitive area and the readout circuit area.

[0093] This invention combines a silicon-based infrared detection array device design method. The readout circuit area has a unit size of 15µm x 15µm, requiring the arraying of 3 x 1 Schottky junctions to form an infrared sensing unit. However, in the 0.18RF process, the standard Schottky MOS transistor DIFF region has a minimum length of 2µm and a maximum of 4µm, and a minimum width of 4µm and a maximum of 16µm. This does not allow for the formation of a 15µm x 15µm array unit. Using the design method of this invention, the DIFF region area is modified to accommodate a 15 x 15µm unit. The modified unit unit is then used, and the guard ring areas of adjacent devices are merged and shared to reduce the overall area of ​​the array device, achieving the required size design. This completes the design of a large-array infrared sensor. Figure 25 and Figure 26 As shown.

[0094] The chip designed using the above method was subjected to curve testing, such as... Figure 27 As shown, it exhibits excellent performance.

[0095] This invention also provides a layout design apparatus for a silicon-based infrared detector array chip, the apparatus including a processor configured to:

[0096] Create the first layout file, call the standard Schottky layout, and flatten the standard Schottky layout;

[0097] According to the preset layout design rules, the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky diode are adjusted respectively, and DRC verification is performed. Among them, the size of the infrared absorption region is adjusted to the maximum size in the preset layout design rules, and is used to absorb infrared light waves to generate photoelectrons; the dimensions of the P-type active region, N-type active region, N-well, and guard ring are adjusted to the minimum size in the rules.

[0098] Based on the preset layout design rules, the infrared antenna structure directly above the infrared absorption region is designed using the M1 metal layer.

[0099] The contact holes are used to connect to the P-type active area, N-type active area and guard ring, and respectively conduct them to the M1 metal layer;

[0100] In the M1 metal layer, all the N electrodes are connected to the guard ring to form the P and N electrodes.

[0101] In some embodiments, the processor is further configured to set the P-type active region, the infrared absorption region, and the N-type active region as a photodetector combination; and to call the photodetector combination multiple times and arrange it in a lateral array within the same N-well and guard ring to achieve the lateral arraying of the infrared detection unit.

[0102] In some embodiments, the processor is further configured to create a second layout file and call the first layout file to combine them into an array device, wherein the array period is designed to be the difference between the overall size of the first layout file and the size of the guard ring, so that the guard rings on the top, bottom, left and right overlap.

[0103] In some embodiments, the processor is further configured to:

[0104] In the M1 metal layer, the N-pole of the first layout unit device in the second layout file is connected to form a common N-electrode; in the M2, M3 and M4 metal layers, the common N-electrode and the P-electrode of each pixel are connected to the outer ring of the infrared detector array by using the layout design of metal vias and the conductors of each layer.

[0105] Windowing is applied to the common N-electrode and P-electrode array to enable interconnection between the silicon-based infrared detector array chip and the readout circuit.

[0106] Polycrystalline silicon was plotted below the outer electrode ring and DRC verification was performed.

[0107] In some embodiments, the infrared antenna structure includes one or a combination of a grating antenna, a rectangular antenna, a log-periodic antenna, a planar helical antenna, and a fractal antenna.

[0108] In some embodiments, the processor is further configured such that the contact hole simultaneously forms electrical contact with both the infrared absorption region and the P-type active region.

[0109] In some embodiments, the infrared absorption region is a region formed by an infrared-sensitive silicide material, which includes one or a combination of cobalt silicide, platinum silicide, and nickel silicide.

[0110] In some embodiments, the processor is further configured as the M2 metal layer, the M3 metal layer, and the M4 metal layer and vias, so as not to obstruct the infrared antenna structure during layout design.

[0111] It should be noted that the layout design device for the silicon-based infrared detector array chip provided in this embodiment belongs to the same technical concept as the prior layout design method for silicon-based infrared detector array chips, and can achieve the same beneficial effects, which will not be elaborated here.

[0112] This invention also provides a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, perform the layout design method for a silicon-based infrared detector array chip as described in any of the above embodiments.

[0113] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A layout design method for a silicon-based infrared detector array chip, characterized in that, The method includes: Create the first layout file, call the standard Schottky layout, and flatten the standard Schottky layout; According to the preset layout design rules, the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky diode are adjusted respectively, and DRC verification is performed. Among them, the size of the infrared absorption region is adjusted to the maximum size in the preset layout design rules, and is used to absorb infrared light waves to generate photoelectrons; the dimensions of the P-type active region, N-type active region, N-well, and guard ring are adjusted to the minimum size in the rules. Based on the preset layout design rules, the infrared antenna structure directly above the infrared absorption region is designed using the M1 metal layer. The contact holes are used to connect to the P-type active area, N-type active area and guard ring, and respectively conduct them to the M1 metal layer; In the M1 metal layer, all the N electrodes are connected to the guard ring to form the P and N electrodes; After connecting all the N electrodes to the guard ring in the M1 metal layer to form the P and N electrodes, the method further includes: Create a second layout file and call the first layout file to combine them into an array device. The array period is designed to be the difference between the overall size of the first layout file and the size of the guard ring, so that the guard rings on the top, bottom, left and right overlap. In the process of creating a second layout file and combining the first layout file into an array device, wherein the array period is designed to be the difference between the overall size of the first layout file and the size of the guard ring, so that the guard rings on the top, bottom, left, and right are overlapped, the method further includes: In the M1 metal layer, the N-pole of the first layout unit device in the second layout file is connected to form a common N-electrode; in the M2, M3 and M4 metal layers, the common N-electrode and the P-electrode of each pixel are connected to the outer ring of the infrared detector array by using the layout design of metal vias and the conductors of each layer. Windowing is applied to the common N-electrode and P-electrode arrays to enable interconnection between the silicon-based infrared detector array chip and the readout circuit. Polycrystalline silicon was drawn below the outer electrode ring and DRC verification was performed.

2. The layout design method for a silicon-based infrared detector array chip according to claim 1, characterized in that, After connecting all the N electrodes to the guard ring in the M1 metal layer to form the P and N electrodes, the method further includes: The P-type active region, infrared absorption region, and N-type active region are configured as a photoelectric detection combination; the photoelectric detection combination is called multiple times and arranged in a horizontal array within the same N-well and guard ring to achieve the horizontal arraying of the infrared detection unit.

3. The layout design method for a silicon-based infrared detector array chip according to claim 1, characterized in that, The infrared antenna structure includes one or a combination of grating antenna, rectangular antenna, log-periodic antenna, planar spiral antenna, and fractal antenna.

4. The layout design method for a silicon-based infrared detector array chip according to claim 1, characterized in that, The contact hole simultaneously forms electrical contact with both the infrared absorption region and the P-type active region.

5. The layout design method for a silicon-based infrared detector array chip according to claim 1, characterized in that, The infrared absorption region is a region formed by an infrared-sensitive silicide material, which includes one or a combination of cobalt silicide, platinum silicide, and nickel silicide.

6. The layout design method for a silicon-based infrared detector array chip according to claim 1, characterized in that, The M2, M3, and M4 metal layers and the vias do not obstruct the infrared antenna structure during layout design.

7. A layout design apparatus for a silicon-based infrared detector array chip, used in the method according to any one of claims 1 to 6, characterized in that, The device includes a processor, the processor being configured to: Create the first layout file, call the standard Schottky layout, and flatten the standard Schottky layout; According to the preset layout design rules, the dimensions of the P-type active region, infrared absorption region, N-type active region, N-well, and guard ring of the Schottky diode are adjusted respectively, and DRC verification is performed. Among them, the size of the infrared absorption region is adjusted to the maximum size in the preset layout design rules, and is used to absorb infrared light waves to generate photoelectrons; the dimensions of the P-type active region, N-type active region, N-well, and guard ring are adjusted to the minimum size in the rules. Based on the preset layout design rules, the infrared antenna structure directly above the infrared absorption region is designed using the M1 metal layer. The contact holes are used to connect to the P-type active area, N-type active area and guard ring, and respectively conduct them to the M1 metal layer; In the M1 metal layer, all the N electrodes are connected to the guard ring to form the P and N electrodes.

8. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, perform the method according to any one of claims 1 to 6.

Images