Flash memory and method of operating the same

Abstract

The application discloses a flash memory, all the memory cells of which are separated gate floating gate devices, the first and second source-drain regions of the memory cells in the array structure are connected to corresponding bit lines, each bit line is shared by two columns of adjacent memory cells, and the shared connection structure comprises that the second source-drain regions of the memory cells in the same row in the current column and the next column are all connected to a first bit line; the first source-drain regions of the memory cells in the same row in the current column and the previous column are all connected to a second bit line; and the first source-drain regions of the memory cells in the same row in the next column and the second column behind the next column are connected together and connected to a third bit line. The selected memory bit is the memory bit of the selected memory cell in the current column close to the second source-drain region, when a programming operation is performed on the selected memory bit, a bit line programming voltage is set on the first bit line, a programming current is set on the second bit line, and a first voltage smaller than the bit line programming voltage is set on the third bit line. The application further discloses an operation method of the flash memory. The application can reduce or eliminate programming interference.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, and in particular to a flash memory. This invention also relates to a method for operating the flash memory. Background Technology

[0002] like Figure 1 The diagram shown is a schematic diagram of the circuit structure of a conventional flash memory storage cell 101; as shown... Figure 2 The diagram shown is a cross-sectional view of a conventional flash memory storage cell 101; as shown... Figure 3 The diagram shown is an array structure diagram of an existing flash memory; the existing flash memory includes multiple storage cells 101, the multiple storage cells 101 form an array cell 301, and the multiple array cells 301 are arranged to form an array structure of the flash memory.

[0003] Each of the aforementioned storage cells 101 employs a discrete-gate floating-gate device.

[0004] like Figure 2 As shown, the split-gate floating gate device includes: a symmetrical first source / drain region 205b and a second source / drain region 206, a plurality of split first gate structures with floating gates 104 located between the first source / drain region 205b and the second source / drain region 205a, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gates 104.

[0005] The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two, which are represented by the markings 102a and 102b respectively.

[0006] The separated gate floating gate device is an N-type device, and both the first source / drain region 205b and the second source / drain region 205a are composed of N+ regions.

[0007] The P-type doped channel region is located between the first source / drain region 205b and the second source / drain region 205a and is covered by each of the first gate structure and the second gate structure 103. The first source / drain region 205b and the second source / drain region 205a are both formed on the P-type semiconductor substrate 201 and are self-aligned with the outer surfaces of the corresponding two first gate structures. The channel regions are formed by the P-type semiconductor substrate 201 between the first source / drain region 205b and the second source / drain region 205a or by further doping on the P-type semiconductor substrate 201.

[0008] The second source / drain region 205a of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BLa.

[0009] The first source-drain region 205b of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BLb.

[0010] Each of the first gate structures is formed by stacking the tunneling dielectric layer 202, the floating gate 104, the control gate dielectric layer 203, and the control gate 105.

[0011] Each of the second gate structures 103 is formed by stacking a word line gate dielectric layer 204 and a word line gate 106.

[0012] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WL. Figure 1 In the memory cell 101, there are two first gate structures, so there are also two control gate lines, which are represented by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0013] When programming selected storage bits of the storage unit 101, in order to... Figure 2 In the first gate structure 102a, the storage bit corresponding to the floating gate 104 is selected as the storage bit, and the applied voltage includes:

[0014] The control gate line CG1 is connected to 5V and is used to open, i.e., conduct, the region segment of the channel controlled by the first gate structure 102b.

[0015] The word line WL is connected to 1.4V and is used to open the region segment of the channel region controlled by the second gate structure 103;

[0016] Bit line BLb is connected to the programming current.

[0017] The control gate line CG0 is connected to a 9V high voltage, and the bit line BLa is connected to a 4.5V high voltage. In this way, after the programming current passes through the channel region controlled by the first gate structure 102b and the second gate structure 103 and reaches the bottom of the first gate structure 102a, the source-side hot electron injection programming can be realized because both the control gate line CG0 and the bit line BLa are high voltage.

[0018] like Figure 3 As shown, in the array structure, the memory cells 101 are arranged in rows and columns. The first source-drain region 205b and the second source-drain region 205a of each memory cell 101 are connected to the corresponding bit lines. Each bit line is shared by two adjacent columns of memory cells 101. The shared connection structure includes:

[0019] The first source-drain region 205b of each of the storage cells 101 in the same column and the first source-drain region 205b of the adjacent storage cell 101 are connected together, and the second source-drain region 205a of each of the storage cells 101 in the same column and the second source-drain region 205a of the adjacent storage cell 101 are connected together. Figure 3 The CCP lists four storage cells 101 to represent the connection relationships in the array structure, and each of the four storage cells is individually labeled 101a, 101b, 101c, and 101d. It can be seen that storage cells 101a and 101b are located in the same column, and the first source-drain region 205b of storage cell 101a is connected to the first source-drain region 205b of storage cell 101b. Similarly, the second source-drain region 205a of storage cell 101a is connected to the second source-drain region 205a of the storage cell (not shown) in the previous row of the same column.

[0020] The second source-drain region 205a of each of the memory cells 101 in the current column and the second source-drain region 205a of the memory cells 101 in the same row in the next column are connected together and connected to the first line.

[0021] The first source-drain region 205b of each of the memory cells 101 in the current column and the first source-drain region 205b of the memory cells 101 in the same row of the previous column are connected together and connected to the second bit line.

[0022] The first source-drain region 205b of each of the memory cells 101 in the next column and the first source-drain region 205b of the memory cells 101 in the same row in the second column are connected together and connected to the third bit line.

[0023] Let the selected storage bit be the storage bit of the selected storage cell 101 in the current column that is close to the second source-drain region 205a.

[0024] The first source-drain region 205b and the second source-drain region 205a of each of the memory cells 101 are symmetrically arranged. Depending on the selected memory bit, the specific bit lines corresponding to adjacent first bit lines, second bit lines, and third bit lines will change accordingly, but their relative positional relationships and... Figure 3 same, Figure 3 In this context, the selected storage bit is storage bit 'a' in storage cell 101a, the corresponding first bit line is bit line BLk, the second bit line is bit line BL(k-1), and the third bit line is bit line BL(k+1). That is, for... Figure 3 The storage unit 101a in, Figure 2 The bit line BLa in the middle is Figure 3 The bit line BLk in the middle, Figure 2 The bit line BLB in the middle is Figure 3 The bit line BL(k-1) in the middle. It can be seen that for... Figure 3 When memory cell 101a is programmed, the control gate line CG1 of the row containing memory cell 101a is connected to a high voltage of 5V, the word line WL is connected to 1.4V, and the control gate line CG0 is connected to 9V. These voltage settings also enable the channel region of memory cell 101c in the same row. To prevent leakage current caused by the channel of memory cell 101c being turned on, in the prior art, the voltage of bit line BL(k+1) is set to the same as that of bit line BLk, that is, it is also set to 4.5V. In addition, since the 4.5V potential is already available, no additional voltage is needed in flash memory.

[0025] However, the applicant discovered that existing flash memory is prone to programming interference during programming operations. Summary of the Invention

[0026] The technical problem to be solved by the present invention is to provide a flash memory that can reduce or eliminate programming interference. To this end, the present invention also provides a method for operating the flash memory.

[0027] Therefore, the flash memory provided by the present invention includes multiple storage cells; each storage cell adopts a discrete gate floating gate device, and the multiple storage cells are arranged to form an array structure of flash memory.

[0028] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0029] In the array structure, the memory cells are arranged in rows and columns. The first source-drain region and the second source-drain region of each memory cell are connected to the corresponding bit line. Each bit line is shared by two adjacent columns of memory cells. The shared connection structure includes:

[0030] The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

[0031] The second source-drain regions of each memory cell in the current column and the second source-drain regions of the memory cells in the same row of the next column are connected together and connected to the first line.

[0032] The first source-drain region of each memory cell in the current column is connected to the first source-drain region of the memory cell in the same row of the previous column and connected to the second bit line.

[0033] The first source-drain regions of each memory cell in the next column and the first source-drain regions of the memory cells in the same row of the second column are connected together and connected to the third bit line.

[0034] Let the selected memory location be the memory location closest to the second source-drain region of the selected memory cell in the current column. When programming the selected memory location, the electrical signals set on the first bit line, the second bit line, and the third bit line include:

[0035] The bit line programming voltage is set on the first bit line.

[0036] The programming current is set on the second line.

[0037] A first voltage is set on the third bit line, which is lower than the bit line programming voltage. By reducing the first voltage, programming interference is prevented from occurring to each memory cell connected to the third bit line.

[0038] A further improvement is that, when programming the selected memory bit, the voltage change phases of the electrical signals on the first bit line, the second bit line, and the third bit line include:

[0039] In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential.

[0040] In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage.

[0041] In the third stage, the first bit line rises to the bit line programming voltage, the second bit line falls to the second voltage, and the third bit line remains at the first voltage, while the second voltage is greater than the ground potential.

[0042] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0043] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0044] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0045] A further improvement is that, in the array structure, the second gate structures of each memory cell in the same row are all connected to the word lines of the same row, and the control gates of the first gate structures of each memory cell in the same row are all connected to the control gate lines of the same row.

[0046] When performing programming operations on the selected memory bit:

[0047] The word line to which the memory cell selected in the current column is connected is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel region controlled by the second gate structure and turns on the region segment of the channel region controlled by the second gate structure.

[0048] The control gate line connected to the control gate of the non-selected memory bit of the selected memory cell in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel controlled by the first gate structure of the non-selected memory bit.

[0049] The control gate line connected to the control gate corresponding to the selected memory bit is connected to the control gate programming voltage.

[0050] A further improvement is that the control gate programming voltage is above 8V and the bit line programming voltage is above 4V.

[0051] The first voltage is 0.9V to 2.5V.

[0052] The second voltage is less than 1V.

[0053] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0054] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0055] To solve the above-mentioned technical problems, the present invention provides a flash memory operation method in which the flash memory includes multiple storage cells; each storage cell adopts a split-gate floating-gate device, and the multiple storage cells are arranged to form an array structure of flash memory.

[0056] The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate.

[0057] In the array structure, the memory cells are arranged in rows and columns. The first source-drain region and the second source-drain region of each memory cell are connected to the corresponding bit line. Each bit line is shared by two adjacent columns of memory cells. The shared connection structure includes:

[0058] The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together, and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together.

[0059] The second source-drain regions of each memory cell in the current column and the second source-drain regions of the memory cells in the same row of the next column are connected together and connected to the first line.

[0060] The first source-drain region of each memory cell in the current column is connected to the first source-drain region of the memory cell in the same row of the previous column and connected to the second bit line.

[0061] The first source-drain regions of each memory cell in the next column and the first source-drain regions of the memory cells in the same row of the second column are connected together and connected to the third bit line.

[0062] The selected memory location is defined as the memory location closest to the second source-drain region of the selected memory cell in the current column. The flash memory operation method includes programming the selected memory location. The programming operation includes setting electrical signals on the first bit line, the second bit line, and the third bit line, including:

[0063] The bit line programming voltage is set on the first bit line.

[0064] The programming current is set on the second line.

[0065] A first voltage is set on the third bit line, which is lower than the bit line programming voltage. By reducing the first voltage, programming interference is prevented from occurring to each memory cell connected to the third bit line.

[0066] A further improvement is that, when programming the selected memory bit, the voltage change phases of the electrical signals on the first bit line, the second bit line, and the third bit line include:

[0067] In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential.

[0068] In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage.

[0069] In the third stage, the first bit line rises to the bit line programming voltage, the second bit line falls to the second voltage, and the third bit line remains at the first voltage, while the second voltage is greater than the ground potential.

[0070] A further improvement is that the split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

[0071] A further improvement is that the separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions.

[0072] The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

[0073] A further improvement is that, in the array structure, the second gate structures of each memory cell in the same row are all connected to the word lines of the same row, and the control gates of the first gate structures of each memory cell in the same row are all connected to the control gate lines of the same row.

[0074] When performing programming operations on the selected memory bit:

[0075] The word line to which the memory cell selected in the current column is connected is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel region controlled by the second gate structure and turns on the region segment of the channel region controlled by the second gate structure.

[0076] The control gate line connected to the control gate of the non-selected memory bit of the selected memory cell in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel controlled by the first gate structure of the non-selected memory bit.

[0077] The control gate line connected to the control gate corresponding to the selected memory bit is connected to the control gate programming voltage.

[0078] A further improvement is that the control gate programming voltage is above 8V, and the bit line programming voltage is above 4V;

[0079] The first voltage is 0.9V to 2.5V;

[0080] The second voltage is less than 1V.

[0081] A further improvement is that each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate.

[0082] Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

[0083] A further improvement is that the floating gate is made of polysilicon, the control gate is made of polysilicon, and the word line gate is made of polysilicon.

[0084] In existing flash memory, when programming a selected memory bit, to prevent leakage from adjacent memory cells that share a higher bit line programming voltage with the selected memory cell's bit line, an equal bit line programming voltage is applied to the other bit line of the adjacent memory cell. However, this invention breaks with conventional thinking by introducing a first voltage lower than the bit line programming voltage on the other bit line of the adjacent memory cell. Since the other bit line of the adjacent memory cell is connected to multiple memory cells in two adjacent columns, reducing the first voltage can reduce or eliminate the programming interference caused by the voltage of the other bit line of the adjacent memory cell on the connected memory cells. Therefore, this invention can reduce or eliminate the programming interference caused by the high voltage of the other bit line of the adjacent memory cell that shares a bit line programming voltage with the selected memory cell when programming a selected memory bit. Attached Figure Description

[0085] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0086] Figure 1 This is a schematic diagram of the circuit structure of an existing flash memory storage cell;

[0087] Figure 2 This is a cross-sectional structural diagram of an existing flash memory storage cell;

[0088] Figure 3 This is a diagram of the existing flash memory array structure;

[0089] Figure 4 This is a timing diagram of the voltage changes of three adjacent bit lines when a selected memory bit is programmed in the flash memory according to an embodiment of the present invention. Detailed Implementation

[0090] Please also refer to the structure of the flash memory storage cell 101 in this embodiment of the invention. Figure 1 and Figure 2 As shown, the array structure of the flash memory in this embodiment of the invention is also referenced. Figure 3 As shown, the flash memory in this embodiment of the invention includes a plurality of storage cells 101; each of the storage cells 101 adopts a split-gate floating gate 104 device, and the plurality of storage cells 101 are arranged to form an array structure of flash memory.

[0091] The separate gate floating gate 104 device includes: a first source / drain region 205b and a second source / drain region 205a symmetrically arranged, a plurality of separate first gate structures with floating gates 104 located between the first source / drain region 205b and the second source / drain region 205a, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

[0092] In this embodiment of the invention, the split-gate floating gate 104 device is a dual split-gate floating gate 104 device, and the number of the first gate structures is two. Figure 1 In the diagram, the two first gate structures shown are marked with labels 102a and 102b, respectively. The two first gate structures can store two bits of data.

[0093] The separated gate floating gate 104 device is an N-type device, and both the first source / drain region 205b and the second source / drain region 205a are composed of N+ regions.

[0094] The p-type doped channel region is located between the first source / drain region 205b and the second source / drain region 205a and is covered by each of the first gate structure and the second gate structure 103, each of the first gate structure and the second gate structure 103 controlling a region segment of the covered channel region. The first source / drain region 205b and the second source / drain region 205a are self-aligned and formed on the surfaces of the semiconductor substrate 201 on both sides of the overall gate structure formed by the arrangement of each of the first gate structure and the second gate structure 103.

[0095] The second source / drain region 205a of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BLa.

[0096] The first source-drain region 205b of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BLb.

[0097] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WLWL. Figure 1 In the memory cell 101, there are two first gate structures, so there are also two control gate lines, which are represented by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0098] In this embodiment of the invention, each of the first gate structures is formed by stacking a tunneling dielectric layer 202, a floating gate 104, a control gate dielectric layer 203, and a control gate 105.

[0099] Each of the second gate structures 103 is formed by stacking a word line gate 106 dielectric layer 204 and a word line gate 106.

[0100] In some preferred embodiments, the floating gate 104 is made of polysilicon, the control gate 105 is made of polysilicon, and the word line gate 106 is made of polysilicon.

[0101] like Figure 3 As shown, in the array structure, the memory cells 101 are arranged in rows and columns. The first source-drain region 205b and the second source-drain region 205a of each memory cell 101 are connected to the corresponding bit lines. Each bit line is shared by two adjacent columns of memory cells 101. The shared connection structure includes:

[0102] The first source-drain region 205b of each of the storage cells 101 in the same column and the first source-drain region 205b of the adjacent storage cell 101 are connected together, and the second source-drain region 205a of each of the storage cells 101 in the same column and the second source-drain region 205a of the adjacent storage cell 101 are connected together. Figure 3 The CCP lists four storage cells 101 to represent the connection relationships in the array structure, and each of the four storage cells is individually labeled 101a, 101b, 101c, and 101d. It can be seen that storage cells 101a and 101b are located in the same column, and the first source-drain region 205b of storage cell 101a is connected to the first source-drain region 205b of storage cell 101b. Similarly, the second source-drain region 205a of storage cell 101a is connected to the second source-drain region 205a of the storage cell (not shown) in the previous row of the same column.

[0103] The second source-drain region 205a of each of the memory cells 101 in the current column and the second source-drain region 205a of the memory cells 101 in the same row in the next column are connected together and connected to the first line.

[0104] The first source-drain region 205b of each of the memory cells 101 in the current column and the first source-drain region 205b of the memory cells 101 in the same row of the previous column are connected together and connected to the second bit line.

[0105] The first source-drain region 205b of each of the memory cells 101 in the next column and the first source-drain region 205b of the memory cells 101 in the same row in the second column are connected together and connected to the third bit line.

[0106] Let the selected storage bit be the storage bit of the selected storage cell 101 in the current column that is close to the second source-drain region 205a.

[0107] In this embodiment of the invention, the first source-drain region 205b and the second source-drain region 205a of each memory cell 101 are symmetrically arranged. Depending on the selected memory bit, the specific bit lines corresponding to adjacent first bit lines, second bit lines, and third bit lines will change accordingly, but their relative positional relationships and... Figure 3 same, Figure 3 In this context, the selected storage bit is storage bit 'a' in the storage cell 101a, the corresponding first bit line is bit line BLk, the second bit line is bit line BL(k-1), and the third bit line is bit line BL(k+1).

[0108] In this embodiment of the invention, in the array structure, the second gate structures 103 of each memory cell 101 in the same row are all connected to the word line WL of the same row, and the control gates 105 of the first gate structures of each memory cell 101 in the same row are all connected to the control gate line of the same row. Figure 3 In the diagram, the two rows of control gate lines connected to each of the storage cells 101 are marked with CG0 and CG1, respectively.

[0109] When programming the selected memory bit, the electrical signals set on the first bit line, the second bit line, and the third bit line include:

[0110] The bit line programming voltage Vblp is set on the first bit line.

[0111] The programming current is set on the second line.

[0112] A first voltage V1 is set on the third bit line. The first voltage V1 is less than the bit line programming voltage Vblp. By reducing the first voltage V1, programming interference is prevented from occurring to each of the memory cells 101 connected to the third bit line.

[0113] The better option is, such as Figure 4 The figure shown is a timing diagram of the voltage changes of three adjacent bit lines when a selected memory bit is programmed in the flash memory according to an embodiment of the present invention. Figure 4 In the diagram, BL(k-1) represents the voltage change curve of the second bit line, BLk represents the voltage change curve of the first bit line, and BL(k+1) represents the voltage change curve of the third bit line. When programming the selected memory bit, the voltage change stages of the electrical signals on the first, second, and third bit lines include:

[0114] In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential.

[0115] In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage V1.

[0116] In the third stage, the first bit line rises to the bit line programming voltage Vblp, the second bit line drops to the second voltage V2, and the third bit line remains at the first voltage V1, while the second voltage V2 is greater than the ground potential.

[0117] When performing programming operations on the selected memory bit, the method further includes:

[0118] The word line WL connected to the memory cell 101 selected in the current column is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the second gate structure 103 and turns on the region segment of the channel controlled by the second gate structure 103.

[0119] The control gate line connected to the control gate 105 corresponding to the non-selected memory bit of the selected memory cell 101 in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel controlled by the first gate structure of the non-selected memory bit.

[0120] The control gate line connected to the control gate 105 corresponding to the selected memory bit is connected to the control gate programming voltage.

[0121] Depend on Figure 3 As shown, during programming, the bit line BLk is supplied with a bit line programming voltage Vblp, and the word line WL is supplied with a third voltage. The control gate line CG1 of the memory cell 101a is the control gate line connected to the control gate 105 corresponding to the non-selected memory bit, so the control gate line CG1 of the memory cell 101a is connected to a fourth voltage. The control gate line CG0 of the memory cell 101a is the control gate line connected to the control gate 105 corresponding to the selected memory bit, so the control gate line CG0 of the memory cell 101a is connected to the control gate programming voltage. The channel of the memory cell 101a will be turned on, and source-end hot electron injection will be generated at the first gate structure corresponding to the selected memory bit 'a' of the memory cell 101a, thereby realizing the programming of the selected memory bit 'a'.

[0122] In some embodiments, the first potential V1 is 0.9V to 2.5V, such as when the first potential V1 is 1.5V. Figure 4 The diagram shows that the first potential V1 is 1.5V.

[0123] The control gate programming voltage is above 8V, for example, 9V, i.e., CG0 is connected to 9V;

[0124] The bit line programming voltage Vblp is above 4V, for example, 4.5V, that is, BLk is connected to 4.5V.

[0125] The second voltage V2 is less than 1V. Figure 4 The text lists the second voltage V2 as 0.4V.

[0126] In some embodiments, the third voltage is 1.4V, i.e., WL is connected to 1.4V;

[0127] The third voltage is connected to 5V, that is, CG1 is connected to 5V.

[0128] Depend on Figure 3 As shown, the WL, CG0, and CG1 of the memory cell 101c in the same row as the memory cell 101a are shared, so the channel region of the memory cell 1c is also turned on. Unlike the prior art, in order to prevent conduction current from being generated between bit line BL(k+1) and bit line BLk, the voltage of bit line BL(k+1) needs to be set to the same voltage as that of bit line BLk, such as 4.5V. In this embodiment of the invention, the voltage of bit line BL(k+1) is set to a lower first voltage V1, such as 1.5V. Thus, because the voltage of bit line BL(k+1) is reduced, programming interference caused by setting bit line BL(k+1) to a high voltage can be reduced or eliminated, that is, programming interference to each memory cell 101 connected to bit line BL(k+1) is reduced or eliminated.

[0129] because Figure 3 The diagram only illustrates the programming interference of one storage bit 'a' of the storage unit 101a. The same problem exists when programming each storage bit. Therefore, the embodiments of the present invention can eliminate the programming interference caused by the programming operation of each storage bit.

[0130] In existing flash memory, when programming a selected memory bit, to prevent leakage of adjacent memory cells 101 that share a bit line with the selected memory cell 101 that is close to the selected memory bit (i.e., a bit line connected to a higher bit line programming voltage Vblp), an equal bit line programming voltage Vblp is applied to another bit line of the adjacent memory cell 101. However, this embodiment of the invention breaks with conventional thinking by introducing a first voltage V1, which is lower than the bit line programming voltage Vblp, onto the other bit line of the adjacent memory cell 101. Since the other bit line of the adjacent memory cell 101 is connected to multiple memory cells 101 in two adjacent columns, reducing the first voltage V1 can reduce or eliminate the programming interference caused by the voltage of the other bit line of the adjacent memory cell 101 on each connected memory cell 101. Therefore, this embodiment of the invention can reduce or eliminate the programming interference caused by the high voltage of the other bit line of the adjacent memory cell 101 that shares a bit line connected to the bit line programming voltage Vblp when programming a selected memory bit.

[0131] The flash memory operation method of this invention embodiment:

[0132] In the flash memory operation method of this embodiment of the invention, please also refer to the structure of the flash memory storage cell 101. Figure 1 and Figure 2 As shown, please also refer to the array structure of the flash memory. Figure 3 As shown, the flash memory includes multiple storage cells 101; each of the storage cells 101 employs a split-gate floating gate 104 device, and the multiple storage cells 101 are arranged to form an array structure of the flash memory.

[0133] The separate gate floating gate 104 device includes: a first source / drain region 205b and a second source / drain region 205a symmetrically arranged, a plurality of separate first gate structures with floating gates 104 located between the first source / drain region 205b and the second source / drain region 205a, and a second gate structure 103 located between the first gate structures; the first gate structure has a control gate 105 located on top of the floating gate 104.

[0134] In the method of this embodiment of the invention, the split-gate floating gate 104 device is a dual split-gate floating gate 104 device, and the number of the first gate structures is two. Figure 1 In the diagram, the two first gate structures shown are marked with labels 102a and 102b, respectively. The two first gate structures can store two bits of data.

[0135] The separated gate floating gate 104 device is an N-type device, and both the first source / drain region 205b and the second source / drain region 205a are composed of N+ regions.

[0136] The p-type doped channel region is located between the first source / drain region 205b and the second source / drain region 205a and is covered by each of the first gate structure and the second gate structure 103, each of the first gate structure and the second gate structure 103 controlling a region segment of the covered channel region. The first source / drain region 205b and the second source / drain region 205a are self-aligned and formed on the surfaces of the semiconductor substrate 201 on both sides of the overall gate structure formed by the arrangement of each of the first gate structure and the second gate structure 103.

[0137] The second source / drain region 205a of the memory cell 101 is connected to the second source / drain electrode, which is connected to the bit line BLa.

[0138] The first source-drain region 205b of the memory cell 101 is connected to the first source-drain electrode, which is connected to the bit line BLb.

[0139] The control gate 105 is connected to the corresponding control gate line, and the word line gate 106 is connected to the word line WLWL. Figure 1 In the memory cell 101, there are two first gate structures, so there are also two control gate lines, which are represented by CG0 and CG1 respectively. The control gate 105 of the first gate structure 102a is connected to the control gate line CG0, and the control gate 105 of the first gate structure 102b is connected to the control gate line CG1.

[0140] In the method of this embodiment of the invention, each of the first gate structures is formed by stacking a tunneling dielectric layer 202, a floating gate 104, a control gate dielectric layer 203, and a control gate 105.

[0141] Each of the second gate structures 103 is formed by stacking a word line gate 106 dielectric layer 204 and a word line gate 106.

[0142] In some preferred embodiments, the floating gate 104 is made of polysilicon, the control gate 105 is made of polysilicon, and the word line gate 106 is made of polysilicon.

[0143] like Figure 3 As shown, in the array structure, the memory cells 101 are arranged in rows and columns. The first source-drain region 205b and the second source-drain region 205a of each memory cell 101 are connected to the corresponding bit lines. Each bit line is shared by two adjacent columns of memory cells 101. The shared connection structure includes:

[0144] The first source-drain region 205b of each of the storage cells 101 in the same column and the first source-drain region 205b of the adjacent storage cell 101 are connected together, and the second source-drain region 205a of each of the storage cells 101 in the same column and the second source-drain region 205a of the adjacent storage cell 101 are connected together. Figure 3 The CCP lists four storage cells 101 to represent the connection relationships in the array structure, and each of the four storage cells is individually labeled 101a, 101b, 101c, and 101d. It can be seen that storage cells 101a and 101b are located in the same column, and the first source-drain region 205b of storage cell 101a is connected to the first source-drain region 205b of storage cell 101b. Similarly, the second source-drain region 205a of storage cell 101a is connected to the second source-drain region 205a of the storage cell (not shown) in the previous row of the same column.

[0145] The second source-drain region 205a of each of the memory cells 101 in the current column and the second source-drain region 205a of the memory cells 101 in the same row in the next column are connected together and connected to the first line.

[0146] The first source-drain region 205b of each of the memory cells 101 in the current column and the first source-drain region 205b of the memory cells 101 in the same row of the previous column are connected together and connected to the second bit line.

[0147] The first source-drain region 205b of each of the memory cells 101 in the next column and the first source-drain region 205b of the memory cells 101 in the same row in the second column are connected together and connected to the third bit line.

[0148] Let the selected storage bit be the storage bit of the selected storage cell 101 in the current column that is close to the second source-drain region 205a.

[0149] In the method of this embodiment of the invention, the first source-drain region 205b and the second source-drain region 205a of each memory cell 101 are symmetrically arranged. Depending on the selected memory bit, the specific bit lines corresponding to adjacent first bit lines, second bit lines, and third bit lines will change accordingly, but the relative positional relationship and... Figure 3 same, Figure 3 In this context, the selected storage bit is storage bit 'a' in the storage cell 101a, the corresponding first bit line is bit line BLk, the second bit line is bit line BL(k-1), and the third bit line is bit line BL(k+1).

[0150] In the method of this embodiment of the invention, in the array structure, the second gate structures 103 of each memory cell 101 in the same row are all connected to the word line WL of the same row, and the control gates 105 of the first gate structures of each memory cell 101 in the same row are all connected to the control gate line of the same row. Figure 3 In the diagram, the two rows of control gate lines connected to each of the storage cells 101 are marked with CG0 and CG1, respectively.

[0151] The flash memory operation method includes programming the selected memory bit, wherein the programming operation includes setting the electrical signals on the first bit line, the second bit line, and the third bit line, including:

[0152] The bit line programming voltage Vblp is set on the first bit line.

[0153] The programming current is set on the second line.

[0154] A first voltage V1 is set on the third bit line. The first voltage V1 is less than the bit line programming voltage Vblp. By reducing the first voltage V1, programming interference is prevented from occurring to each of the memory cells 101 connected to the third bit line.

[0155] The better option is, such as Figure 4 The figure shown is a timing diagram of the voltage changes of three adjacent bit lines when a selected memory bit is programmed in the flash memory according to an embodiment of the present invention. Figure 4 In the diagram, BL(k-1) represents the voltage change curve of the second bit line, BLk represents the voltage change curve of the first bit line, and BL(k+1) represents the voltage change curve of the third bit line. When programming the selected memory bit, the voltage change stages of the electrical signals on the first, second, and third bit lines include:

[0156] In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential.

[0157] In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage V1.

[0158] In the third stage, the first bit line rises to the bit line programming voltage Vblp, the second bit line drops to the second voltage V2, and the third bit line remains at the first voltage V1, while the second voltage V2 is greater than the ground potential.

[0159] When performing programming operations on the selected memory bit, the method further includes:

[0160] The word line WL connected to the memory cell 101 selected in the current column is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the second gate structure 103 and turns on the region segment of the channel controlled by the second gate structure 103.

[0161] The control gate line connected to the control gate 105 corresponding to the non-selected memory bit of the selected memory cell 101 in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel controlled by the first gate structure of the non-selected memory bit.

[0162] The control gate line connected to the control gate 105 corresponding to the selected memory bit is connected to the control gate programming voltage.

[0163] Depend on Figure 3 As shown, during programming, the bit line BLk is supplied with a bit line programming voltage Vblp, and the word line WL is supplied with a third voltage. The control gate line CG1 of the memory cell 101a is the control gate line connected to the control gate 105 corresponding to the non-selected memory bit, so the control gate line CG1 of the memory cell 101a is connected to a fourth voltage. The control gate line CG0 of the memory cell 101a is the control gate line connected to the control gate 105 corresponding to the selected memory bit, so the control gate line CG0 of the memory cell 101a is connected to the control gate programming voltage. The channel of the memory cell 101a will be turned on, and source-end hot electron injection will be generated at the first gate structure corresponding to the selected memory bit 'a' of the memory cell 101a, thereby realizing the programming of the selected memory bit 'a'.

[0164] In some embodiments, the first potential V1 is 0.9V to 2.5V, such as when the first potential V1 is 1.5V. Figure 4 The diagram shows that the first potential V1 is 1.5V.

[0165] The control gate programming voltage is above 8V, for example, 9V, i.e., CG0 is connected to 9V;

[0166] The bit line programming voltage Vblp is above 4V, for example, 4.5V, that is, BLk is connected to 4.5V.

[0167] The second voltage V2 is less than 1V. Figure 4 The text lists the second voltage V2 as 0.4V.

[0168] In some embodiments, the third voltage is 1.4V, i.e., WL is connected to 1.4V;

[0169] The third voltage is connected to 5V, that is, CG1 is connected to 5V.

[0170] Depend on Figure 3 As shown, the WL, CG0, and CG1 of the memory cell 101b in the same row as the memory cell 101a are shared, so the channel region of the memory cell 1b is also turned on. In the prior art, to prevent conduction current from being generated between bit line BL(k+1) and bit line BLk, the voltage of bit line BL(k+1) needs to be set to the same voltage as bit line BLk, such as 4.5V. Unlike the prior art, in the method of this embodiment, the voltage of bit line BL(k+1) is set to a lower first voltage V1, such as 1.5V. Thus, because the voltage of bit line BL(k+1) is reduced, programming interference caused by setting bit line BL(k+1) to a high voltage can be reduced or eliminated, that is, programming interference to each memory cell 101 connected to bit line BL(k+1) can be reduced or eliminated.

[0171] because Figure 3 The diagram only illustrates the programming interference of one storage bit 'a' of the storage unit 101a. The same problem exists when programming each storage bit. Therefore, the method of the present invention can eliminate the programming interference caused by the programming operation of each storage bit.

[0172] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A flash memory, characterized in that, It includes multiple storage cells; each storage cell employs a discrete-gate floating-gate device, and the multiple storage cells are arranged to form a flash memory array structure; The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. In the array structure, the memory cells are arranged in rows and columns. The first source-drain region and the second source-drain region of each memory cell are connected to the corresponding bit line. Each bit line is shared by two adjacent columns of memory cells. The shared connection structure includes: The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together; and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together. The second source-drain regions of each memory cell in the current column and the second source-drain regions of the memory cells in the same row of the next column are connected together and connected to the first line; The first source-drain regions of each memory cell in the current column and the first source-drain regions of the memory cells in the same row of the previous column are connected together and connected to the second bit line; The first source-drain regions of each memory cell in the next column and the first source-drain regions of the memory cells in the same row of the second column are connected together and connected to the third bit line; Let the selected memory location be the memory location closest to the second source-drain region of the selected memory cell in the current column. When programming the selected memory location, the electrical signals set on the first bit line, the second bit line, and the third bit line include: The bit line programming voltage is set on the first bit line; The programming current is set on the second line; A first voltage is set on the third bit line, which is lower than the bit line programming voltage. By reducing the first voltage, programming interference is prevented from occurring to each memory cell connected to the third bit line. When programming the selected memory bit, the voltage change phases of the electrical signals on the first bit line, the second bit line, and the third bit line include: In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential; In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage. In the third stage, the first bit line rises to the bit line programming voltage, the second bit line falls to the second voltage, and the third bit line remains at the first voltage, while the second voltage is greater than the ground potential.

2. The flash memory as described in claim 1, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

3. The flash memory as described in claim 2, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

4. The flash memory as described in claim 1 or 2, characterized in that: In the array structure, the second gate structures of each memory cell in the same row are connected to the word line of the same row, and the control gates of the first gate structures of each memory cell in the same row are connected to the control gate line of the same row. When performing programming operations on the selected memory bit: The word line connected to the memory cell selected in the current column is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the second gate structure and turns on the region segment of the channel controlled by the second gate structure. The control gate line connected to the control gate of the non-selected memory bit of the selected memory cell in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel region controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel region controlled by the first gate structure of the non-selected memory bit. The control gate line connected to the control gate corresponding to the selected memory bit is connected to the control gate programming voltage.

5. The flash memory as described in claim 4, characterized in that: The control gate programming voltage is above 8V, and the bit line programming voltage is above 4V; The first voltage is 0.9V to 2.5V; The second voltage is less than 1V.

6. The flash memory as described in claim 1, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

7. A method for operating a flash memory, characterized in that, Flash memory includes multiple storage cells; each storage cell employs a discrete-gate floating-gate device, and the multiple storage cells are arranged to form an array structure of flash memory; The split-gate floating gate device includes: a first source-drain region and a second source-drain region symmetrically arranged, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. In the array structure, the memory cells are arranged in rows and columns. The first source-drain region and the second source-drain region of each memory cell are connected to the corresponding bit line. Each bit line is shared by two adjacent columns of memory cells. The shared connection structure includes: The first source-drain regions of each of the memory cells in the same column and the first source-drain regions of adjacent memory cells are connected together; and the second source-drain regions of each of the memory cells in the same column and the second source-drain regions of adjacent memory cells are connected together. The second source-drain regions of each memory cell in the current column and the second source-drain regions of the memory cells in the same row of the next column are connected together and connected to the first line; The first source-drain regions of each memory cell in the current column and the first source-drain regions of the memory cells in the same row of the previous column are connected together and connected to the second bit line; The first source-drain regions of each memory cell in the next column and the first source-drain regions of the memory cells in the same row of the second column are connected together and connected to the third bit line; The selected memory location is defined as the memory location closest to the second source-drain region of the selected memory cell in the current column. The flash memory operation method includes programming the selected memory location. The programming operation includes setting electrical signals on the first bit line, the second bit line, and the third bit line, including: The bit line programming voltage is set on the first bit line; The programming current is set on the second line; A first voltage is set on the third bit line, which is lower than the bit line programming voltage. By reducing the first voltage, programming interference is prevented from occurring to each memory cell connected to the third bit line. When programming the selected memory bit, the voltage change phases of the electrical signals on the first bit line, the second bit line, and the third bit line include: In the first stage, the first bit line, the second bit line, and the third bit line are all at ground potential; In the second stage, the first bit line, the second bit line, and the third bit line all rise from ground potential to the first voltage. In the third stage, the first bit line rises to the bit line programming voltage, the second bit line falls to the second voltage, and the third bit line remains at the first voltage, while the second voltage is greater than the ground potential.

8. The flash memory operation method as described in claim 7, characterized in that: The split-gate floating gate device is a dual split-gate floating gate device, and the number of the first gate structures is two.

9. The flash memory operation method as described in claim 8, characterized in that: The separated gate floating gate device is an N-type device, and both the first source / drain region and the second source / drain region are composed of N+ regions; The P-type doped channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling the region segment of the covered channel region respectively.

10. The method of operating flash memory as described in claim 7 or 8, characterized in that: In the array structure, the second gate structures of each memory cell in the same row are connected to the word line of the same row, and the control gates of the first gate structures of each memory cell in the same row are connected to the control gate line of the same row. When performing programming operations on the selected memory bit: The word line connected to the memory cell selected in the current column is connected to a third voltage, which is greater than or equal to the threshold voltage of the region segment of the channel controlled by the second gate structure and turns on the region segment of the channel controlled by the second gate structure. The control gate line connected to the control gate of the non-selected memory bit of the selected memory cell in the current column is connected to a fourth voltage, which is greater than or equal to the threshold voltage of the region segment of the channel region controlled by the first gate structure of the non-selected memory bit and turns on the region segment of the channel region controlled by the first gate structure of the non-selected memory bit. The control gate line connected to the control gate corresponding to the selected memory bit is connected to the control gate programming voltage.

11. The method of operating flash memory as described in claim 10, characterized in that: The control gate programming voltage is above 8V, and the bit line programming voltage is above 4V; The first voltage is 0.9V to 2.5V; The second voltage is less than 1V.

12. The flash memory operation method as described in claim 7, characterized in that: Each of the first gate structures is formed by stacking a tunneling dielectric layer, the floating gate, the control gate dielectric layer, and the control gate; Each of the second gate structures is formed by stacking a word line gate dielectric layer and a word line gate.

13. The flash memory operation method as described in claim 12, characterized in that: The floating gate is made of polysilicon, the control gate is made of polysilicon, and the word line gate is made of polysilicon.

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