A method for manufacturing a high-density trench MOSFET

Abstract

The application discloses a manufacturing method of a high-density trench MOSFET, and belongs to the field of semiconductor power devices. The manufacturing method comprises the following steps: first, a well region is implanted before a trench; a hard mask layer for trench etching adopts an epitaxial silicon-silicon oxide-silicon nitride structure, and the film layer structure is retained until polycrystal etching; after polycrystal etching, SPACER etching treatment is performed on a second silicon oxide layer and a first silicon nitride layer in the hard mask layer, so as to form SPACER side walls on both sides of the polycrystal; after dielectric hole etching, a silicon nitride hard mask layer is formed in a hole opening area, so as to realize self-alignment etching of a silicon hole and ensure that the silicon hole is always located at a central position between the trenches. Through optimization of process steps and process flow processing sequences, the application does not need to increase additional photoetching levels, and can effectively improve product reliability under the condition that process difficulty and manufacturing cost increase are limited.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to a method for manufacturing a high-density trench MOSFET. Background Technology

[0002] Trench MOSFETs are a new type of discrete power MOSFET device. Compared with bipolar power devices, they offer advantages such as lower conduction losses, higher operating frequencies, voltage-controlled operation, and simpler control circuits, making them increasingly popular in industry. Compared to planar MOSFETs, the vertical trench gate and conductive channel of trench MOSFETs eliminate the JFET region effect, enabling smaller cell sizes and higher current draw, thus improving the device's current capability and switching performance, especially in the medium- and low-voltage power MOSFET field.

[0003] Trench MOSFETs, unrestricted by the JFET region, can maximize the advantages of channel density. For low- and medium-voltage products with high channel resistance, increasing the trench density of the cells is crucial for trench MOSFETs. However, as trench density increases, the critical process windows in the cell region inevitably decrease. This can lead to misalignment of silicon vias in high-density trench MOSFETs, resulting in uneven overcurrent and localized burn-out during operation. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing high-density trench MOSFETs to solve the problems in the prior art.

[0005] To address the aforementioned technical problems, this invention provides a method for manufacturing a high-density trench MOSFET, comprising:

[0006] A first silicon oxide layer is grown on an epitaxial silicon wafer, trap implantation is achieved through ion implantation, a first silicon nitride layer is deposited, forming a three-layer thin film structure of epitaxial silicon-silicon oxide-silicon nitride, and then a second silicon oxide layer is deposited.

[0007] Trench structures were excavated using TR lithography and etching processes, and then the sidewalls and bottom of the trench structures were repaired using a high-temperature sacrificial oxidation process.

[0008] The gate oxide layer is grown and polycrystalline material is deposited using the gate oxide process. The polycrystalline material outside the trench is etched away using the polycrystalline etch-back process. The etching stops on the dielectric layer. Then, a high-temperature thermal process is used to push the junction to form a well region.

[0009] By using a dielectric dry etching process, the sidewall effect of the polycrystalline material is utilized to leave a SPACER structure on both sides of the polycrystalline material. Then, the exposed first silicon nitride layer is etched away by silicon nitride etching.

[0010] Source implantation and activation are achieved through N+ lithography and ion implantation, thus realizing the source contact region in the cellular region;

[0011] Perform dielectric deposition and planarization, and complete the dielectric hole process for the contact hole section using hole photolithography and dielectric hole etching;

[0012] Remove the photoresist from the holes to achieve silicon via etching in the contact holes. Since there is a silicon nitride hard masking layer in the cell region, the silicon via etching only etches the area without silicon nitride protection, thus realizing a self-aligned process for silicon via etching.

[0013] By utilizing hole injection and activation to form a solid region, and through tungsten hole filling and polishing, contact hole metal is brought out; through metal deposition, photolithography and etching, metal interconnection is achieved, and the overall device is completed.

[0014] In one embodiment, the thickness of the first silicon oxide layer is The thickness of the first silicon nitride layer is The thickness of the second silicon oxide layer is

[0015]

[0016] In one embodiment, the ions used for trap implantation are boron (B), with an energy of 50–120 keV and a dose of 1–5 E13 ions / cm². 2 .

[0017] In one embodiment, the trench structure has smooth sidewalls, an inclination angle of 88-90°, and a semi-circular bottom. The depth of the trench structure needs to match the actual requirements of the product. The rated voltage of the product is 20V-150V. Corresponding trench structures include strip-shaped grid structures and triangular grid structures, with a depth range of 0.7-2µm.

[0018] In one embodiment, the temperature range of the sacrificial oxidation process is 1000–1150°C, and the oxidation thickness is [missing information].

[0019] In one embodiment, the source implantation element is As or P, the implantation energy is 60–100 keV, and the implantation dose is 5E15–1E16 cells / cm³. 2 .

[0020] In one embodiment, the depth of the silicon hole etching is

[0021] This invention provides a method for manufacturing high-density trench MOSFETs. Before trench etching, well region implantation is performed. The hard masking layer for trench etching adopts an epitaxial silicon-silicon oxide-silicon nitride structure, which is retained until polycrystalline etching. After polycrystalline etching, the second silicon oxide layer and the first silicon nitride layer in the hard masking layer are subjected to SPACER etching to form SPACER sidewalls on both sides of the polycrystalline layer. After via etching, a silicon nitride hard masking layer is formed in the via opening area, achieving self-aligned via etching and ensuring that the via is always centered between trenches. This invention optimizes process steps and process flow sequence, eliminating the need for additional photolithography layers. With limited increases in process difficulty and manufacturing cost, it can effectively improve product reliability. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of trap injection and hard masking layer deposition;

[0023] Figure 2 This is a schematic diagram of the formation of the trench structure;

[0024] Figure 3 This is a schematic diagram of the polycrystalline etch-back cross-section structure;

[0025] Figure 4 This is a schematic diagram of a high-temperature push-junction trap;

[0026] Figure 5 This is a schematic diagram of the SPACER etching structure for the hard masking layer;

[0027] Figure 6 This is a schematic diagram of N+ injection and activation;

[0028] Figure 7 This is a schematic diagram of dielectric deposition and surface planarization;

[0029] Figure 8 This is a schematic diagram of the medium pore corrosion structure;

[0030] Figure 9 This is a schematic diagram of the silicon pore etching structure;

[0031] Figure 10 This is a schematic diagram of the contact lead-out of the injection body through the hole;

[0032] Figure 11 This is a schematic diagram of device interconnects completed by metal photolithography / etching. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the manufacturing method of a high-density trench-type MOSFET proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0034] Trench-type MOSFET devices are three-terminal discrete devices. The front side of the wafer is divided into two parts: the source region and the gate region. These two regions are isolated from the outside environment by a trench. The drain region of the device is on the back side of the wafer. The process of this invention mainly focuses on the wafer source; the gate is led out to the edge of the die through polysilicon in the trench, and then interconnected with metal by drilling contact holes on it. The drain only needs to be led out by thinning and plating metal on the back side, which is understood by those skilled in the art, and therefore will not be described in detail in this invention. This invention mainly proposes a process technology for the trench cell region of the source region, using a trench isolation ring around the entire die region to achieve junction termination.

[0035] This invention provides a method for manufacturing high-density trench MOSFETs. Based on conventional trench MOSFET devices, by improving some processes, self-aligned etching of silicon vias in the cells is achieved, effectively improving the reliability and quality of trench MOSFETs.

[0036] Specifically, self-aligned etching of silicon vias is achieved in the cell region of a trench-type MOSFET using the following method. This embodiment takes an N-type device as an example; a P-type device can be obtained using the corresponding method:

[0037] A first silicon oxide layer 2 is grown on a silicon epitaxial wafer 1, wherein the thickness of the first silicon oxide layer 2 is... P-well (P-trap) implantation was achieved using ion implantation technology, with boron (B) implanted at energies of 50–120 keV and doses of 1–5 E13 ions / cm². 2 Then, a first silicon nitride layer 3 is deposited using chemical vapor deposition to form an epitaxial silicon-silicon oxide-silicon nitride three-layer thin film structure, the thickness of which is... Then, a second silicon oxide layer 4 is deposited by chemical vapor deposition, wherein the thickness of the second silicon oxide layer 4 is... like Figure 1 As shown. In this invention, well region implantation is first achieved, and the hard masking layer used as the trench etching layer is a silicon oxide-silicon nitride-silicon oxide film structure, which is different from the conventional trench MOSFT silicon dioxide film.

[0038] Trench structures with smooth sidewalls, tilt angles of 88–90°, semi-circular bottoms, and a certain depth were created using TR lithography and etching processes. Figure 2 As shown, the depth of the trench structure is 0.7 to 2 μm, which needs to be matched with the actual needs of the product. For example, the depth of the trench structure in the N40V product is about 1.2 μm.

[0039] After completing the trench structure process, a sacrificial oxide layer needs to be grown to repair the damage to the sidewalls and bottom silicon surface of the trench structure during dry etching. This oxide layer is then removed using wet etching. Generally, the sacrificial oxide temperature range is 1000–1150°C, and the oxide thickness is [missing information].

[0040] After completing the trench process, a gate oxide layer 5 and polycrystalline material 6 are grown using a gate oxide process. The polycrystalline material outside the trench area is then etched away using a polycrystalline etch-back process. Figure 3 As shown. It can be seen that the surface of polycrystalline 6 is higher than the first silicon oxide layer 2 by a certain height, which is the thickness of the remaining hard masking layer after trench etching.

[0041] By utilizing a high-temperature thermal process, PW is subjected to push-junction treatment to form a well region, such as... Figure 4 As shown;

[0042] Utilizing the high selectivity of dry etching for the polycrystalline layer, the second silicon oxide layer 4, retained during trench etching, is etched away, forming spacer sidewalls on both sides of the polycrystalline layer 6. Then, the spacer sidewalls are used to etch away the first silicon nitride layer 3 exposed in the cell region, such as... Figure 5 As shown.

[0043] Source implantation and activation were achieved using N+ lithography and ion implantation to create source contact regions in the cellular region. The implanted element was As or P, the implantation energy was 60–100 keV, and the implantation dose was 5E15–1E16 ions / cm². 2 ,like Figure 6 As shown.

[0044] At this point, the front-end device fabrication process has been completed. Then, chemical vapor deposition (CVD) is used to deposit and planarize the dielectric material, such as... Figure 7 As shown, the deposited medium is SiO2, which is integrated with the second silicon oxide layer 4.

[0045] Using hole lithography, the first step is dielectric hole etching. The etching stops at the silicon surface and the surface of the first silicon nitride layer 3, such as... Figure 8 As shown.

[0046] Next, the surface photoresist is removed for the second step of silicon via etching. Because silicon etching has a high selectivity for silicon nitride, the first silicon nitride layer 3 becomes a hard masking layer for etching the silicon vias. The via etching only etches the areas without silicon nitride protection, thus achieving a self-aligned process for silicon via etching. The etching depth is [insert depth here]. like Figure 9 As shown in the diagram. This process ensures that the silicon via etching location is centered between the trenches, solving the problem of via overlay misalignment in photolithography.

[0047] P-type impurities are doped into the deep bulk region using hole injection, and then thermally activated to form a P+ bulk region 7 for extraction, such as... Figure 10 As shown.

[0048] Tungsten filling and polishing are used to bring out the contact hole metal 8. Metal interconnects are then achieved through metal deposition, photolithography, and etching, completing the overall device as follows: Figure 11 As shown.

[0049] This invention achieves self-aligned etching of silicon vias in high-density cellular structures through process optimization, improving the overlay accuracy of vias to trenches in the cellular region, enhancing product quality, and avoiding uneven overcurrent in the channel caused by via photolithography overlay deviation, which can lead to localized burnout.

[0050] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing a high-density trench-type MOSFET, characterized in that, include: A first silicon oxide layer is grown on an epitaxial silicon wafer, trap implantation is achieved through ion implantation, a first silicon nitride layer is deposited, forming a three-layer thin film structure of epitaxial silicon-silicon oxide-silicon nitride, and then a second silicon oxide layer is deposited. Trench structures were excavated using TR lithography and etching processes, and then the sidewalls and bottom of the trench structures were repaired using a high-temperature sacrificial oxidation process. The gate oxide layer is grown and polycrystalline material is deposited using the gate oxide process. The polycrystalline material outside the trench is etched away using the polycrystalline etch-back process. The etching stops on the dielectric layer. Then, a high-temperature thermal process is used to push the junction to form a well region. By using a dielectric dry etching process, the sidewall effect of the polycrystalline material is utilized to leave a SPACER structure on both sides of the polycrystalline material. Then, the exposed first silicon nitride layer is etched away by silicon nitride etching. Source implantation and activation are achieved through N+ lithography and ion implantation, thus realizing the source contact region in the cellular region; Perform dielectric deposition and planarization, and complete the dielectric hole process for the contact hole section using hole photolithography and dielectric hole etching; Remove the photoresist from the holes to achieve silicon via etching in the contact holes. Since there is a silicon nitride hard masking layer in the cell region, the silicon via etching only etches the area without silicon nitride protection, thus realizing a self-aligned process for silicon via etching. By utilizing hole injection and activation to form a solid region, and through tungsten hole filling and polishing, contact hole metal is brought out; through metal deposition, photolithography and etching, metal interconnection is achieved, and the overall device is completed.

2. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The thickness of the first silicon oxide layer is The thickness of the first silicon nitride layer is The thickness of the second silicon oxide layer is 3. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The ions used for trap implantation are boron (B), with energies of 50–120 keV and doses of 1–5 E13 ions / cm². 2 .

4. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The trench structure has smooth sidewalls, an inclination angle of 88-90°, and a semi-circular bottom. The depth of the trench structure needs to match the actual requirements of the product. The rated voltage of the product is 20V-150V. The corresponding trench structures are strip-shaped and triangular-shaped, with a depth range of 0.7-2µm.

5. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The sacrificial oxidation process has a temperature range of 1000–1150°C and an oxidation thickness of [missing information].

6. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The source implantation element is As or P, the implantation energy is 60–100 keV, and the implantation dose is 5E15–1E16 cells / cm³. 2 .

7. The method for manufacturing a high-density trench-type MOSFET as described in claim 1, characterized in that, The depth of the silicon hole etching is

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