Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same are described, particularly a semiconductor structure having a metal ion trapping layer and a method of forming the structure. The method includes forming a first fin structure and a second fin structure over a substrate, and forming a first gate structure over the first fin structure and a second gate structure over the second fin structure, wherein the first gate structure and the second gate structure are adjacent. The method further includes forming a dielectric layer over the first gate structure and the second gate structure, removing a portion of the dielectric layer over an adjacent portion of the first gate structure and the second gate structure to form an opening, and forming a metal ion trapping layer in the opening. The metal ion trapping layer can reduce metal drift and / or migration, reduce leakage current in adjacent metal gates having different work function metals, and improve device performance.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure and a method for forming the same. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to increase. To meet this demand, the semiconductor industry continues to shrink the size of semiconductor devices and increase transistor density. In miniaturized semiconductor devices, metal gates with different work function metals (WFM) can be adjacent to each other. Summary of the Invention

[0003] According to some embodiments disclosed herein, a method for forming a semiconductor structure includes: forming a first fin structure and a second fin structure on a substrate; forming a first gate structure above the first fin structure and a second gate structure above the second fin structure, wherein the first gate structure and the second gate structure are adjacent to each other; forming a dielectric layer on the first gate structure and the second gate structure; removing a portion of the dielectric layer over an adjacent portion of the first gate structure and the second gate structure to form an opening; and forming a metal ion trapping layer in the opening.

[0004] According to some embodiments disclosed herein, a method of forming a semiconductor structure includes: forming a first gate structure, wherein forming the first gate structure includes forming a first type work function metal layer and a metal fill layer; forming a second gate structure adjacent to the first gate structure, wherein forming the second gate structure includes forming a second type work function metal layer and the metal fill layer, and wherein the second type work function metal layer is different from the first type work function metal layer; forming a mask layer having an opening on an adjacent portion of the first gate structure and the second gate structure; forming a metal ion trapping layer in a top portion of the metal fill layer exposed by the opening; and removing the mask layer.

[0005] According to some embodiments disclosed herein, a semiconductor structure includes a first fin structure and a second fin structure on a substrate, and a first gate structure above the first fin structure. The first gate structure includes a first-type work function metal layer and a metal fill layer. The semiconductor structure further includes a second gate structure above the second fin structure and adjacent to the first gate structure. The second gate structure includes a second-type work function metal layer, wherein the second-type work function metal layer is different from the first-type work function metal layer; and a metal fill layer. The semiconductor structure further includes a metal ion trapping layer in the top portion of the metal fill layer above the adjacent portion of the first gate structure and the second gate structure. Attached Figure Description

[0006] The nature of this disclosure is best understood when read in conjunction with the accompanying drawings from the following detailed description.

[0007] Figure 1A The illustration shows an isometric view of a semiconductor structure with a metal ion trapping layer according to some embodiments;

[0008] Figure 1B The illustrations are based on some embodiments. Figure 1A The semiconductor structure shown is a cross-sectional view along line AA;

[0009] Figure 1C The illustration shows the concentration distribution of different ions relative to the width of a semiconductor structure having a metal ion trapping layer, according to some embodiments.

[0010] Figure 1D The figure shows an isometric view of another semiconductor structure having a metal ion trapping layer according to some embodiments;

[0011] Figure 1E The illustrations are based on some embodiments. Figure 1D The semiconductor structure shown is a cross-sectional view along line BB;

[0012] Figure 1F The illustration shows the concentration distribution of ions formed by different methods relative to the depth in a semiconductor structure having a metal ion trapping layer, according to some embodiments.

[0013] Figures 1G to 1I The illustration shows a metal gate layout in a semiconductor device according to some embodiments;

[0014] Figure 2 This is a flowchart of a method for manufacturing a semiconductor structure having a metal ion trapping layer according to some embodiments;

[0015] Figures 3 to 10 The illustration shows cross-sectional views of a semiconductor structure with a metal ion trapping layer at various stages of its manufacturing process, according to some embodiments.

[0016] Figure 11 This is a flowchart of another method for manufacturing a semiconductor structure having a metal ion trapping layer according to some embodiments;

[0017] Figures 12 to 18 The illustration shows cross-sectional views of a semiconductor structure with a metal ion trapping layer at various stages of its manufacturing process, according to some embodiments.

[0018] [Symbol Explanation]

[0019] 100A:FET

[0020] 100D:FET

[0021] 104:Substrate

[0022] 106A: n-type fin structure

[0023] 106B: p-type fin structure

[0024] 110A~110B: S / D Zone

[0025] 112A: Gate structure

[0026] 112B: Gate structure

[0027] 114: Gate spacer

[0028] 116: STI area

[0029] 117:ESL

[0030] 118: ILD layer

[0031] 120: Metal ion trapping layer

[0032] 121: Metal ion trapping layer

[0033] 122:HK dielectric layer

[0034] 124: p-type WFM layer

[0035] 126:n-type WFM layer

[0036] 128: Adhesive layer

[0037] 130: Metal filler layer

[0038] 132: Cutting the metal gate

[0039] 200: Method

[0040] 202~216: Operation

[0041] 302: First gate opening

[0042] 304: Second gate opening

[0043] 902: Opening

[0044] 1100: Method

[0045] 1102~1112: Operation

[0046] 1702: Photoresist layer

[0047] 1704: Opening

[0048] A~F: Area

[0049] H1~H8: Thickness

[0050] W1~W2: Width Detailed Implementation

[0051] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, the formation of a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0052] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0053] Note that references to "an embodiment," "an example embodiment," "an exemplary embodiment," "illustrative," etc., in the specification indicate that the described embodiment may include specific features, structures, or characteristics, but each embodiment does not necessarily include specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0054] It should be understood that the phrases or terms used herein are for descriptive purposes and not for limitation, and therefore the terms or phrases used herein will be interpreted by those skilled in the art based on the teachings herein.

[0055] In some embodiments, the terms “about” and “basic” may indicate the value of a given quantity that varies within a range of 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. The terms “about” and “basic” may refer to percentages of values ​​as interpreted by those skilled in the art(s) based on the teachings herein.

[0056] Fins associated with fin field-effect transistors (finFETs) and gate-all-around (GAA) FETs can be patterned using any suitable method. For example, fins can be patterned using one or more optical lithography processes, including dual-patterning and multi-patterning processes. Dual-patterning and multi-patterning processes can combine optical lithography with self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than those obtained using a single, direct optical lithography process. For example, a sacrificial layer can be formed over a substrate and patterned using optical lithography. Spacers can be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer can be removed, and the remaining spacers can be used to pattern the fins.

[0057] exist Figure 1A , Figure 1B , Figure 1D , Figure 1E , Figures 1G to 1I , Figures 3 to 10 ,and Figures 12 to 18 Unless otherwise mentioned, the discussion of elements with the same annotation applies to each other.

[0058] As the semiconductor industry continues to shrink the size of semiconductor devices, metal gates with different work function metals (WFMs) can be designed to be adjacent to each other to reduce device footprint. Different WFMs can have different concentrations of the same metal. For example, some WFMs may have a higher concentration of aluminum (Al) or be aluminum-rich. A WFM alloy is considered aluminum-rich if it contains more than about 10% atomic percentage (at%) of aluminum. Some WFMs may have a lower aluminum concentration or be aluminum-free. When WFMs with different concentrations of the same metal are adjacent, the metal can diffuse from the high-concentration side to the low-concentration side. Metal drift and / or migration can cause leakage current in the metal gate and degrade device performance.

[0059] This disclosure provides example field-effect transistor (FET) structures (e.g., GAA FET, finFET, or planar FET) having a metal ion trapping layer in semiconductor devices and / or integrated circuits (ICs) and example methods for manufacturing the same. In some embodiments, the metal ion trapping layer may be formed in an interlayer dielectric (ILD) layer above an adjacent metal gate having different WFMs. Openings may be formed in the ILD layer by a dry etching process or a wet etching process. The metal ion trapping layer may be formed by depositing a fluorine-rich oxide layer in the opening using a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. An oxide layer is considered fluorine-rich if it contains more than 10% fluorine (F) atomic percentage. F in the fluorine-rich oxide layer can react with metal ions diffusing from the high concentration side to the low concentration side of the WFM, thereby reducing metal drift and / or migration. For example, F can react with Al to form aluminum fluoride (AlF3). This reaction can occur during the deposition of a fluorine-rich oxide layer. In some embodiments, the fluorine-rich oxide layer may be retained in the ILD layer after the reaction. In some embodiments, the fluorine-rich oxide layer may be removed after the reaction.

[0060] In some embodiments, a metal ion trapping layer may be formed in a metal filler layer of adjacent metal gates having different WFMs. In some embodiments, the metal ion trapping layer may be formed by diffusing carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), F, and combinations thereof in the metal filler layer using a thermal diffusion process, an atomic layer deposition (ALD) diffusion process, or a wet diffusion process. In some embodiments, the metal ion trapping layer may be formed by implanting C, N, P, As, Sb, F, and combinations thereof in the metal filler layer using an ion implantation process. In some embodiments, the ion implantation process may be plasma-enhanced. The region to be diffused or implanted may be defined by a masking layer such as a photoresist layer. The C, N, P, As, Sb, F, and combinations thereof in the metal ion trapping layer may react with metal ions diffusing from the high concentration side to the low concentration side of the WFM, thereby reducing metal drift and / or migration. For example, C, N, P, As, Sb, F, and Al may react to form an aluminum compound. This reaction may occur during the formation of the metal ion trapping layer. In some embodiments, the metal ion trapping layer may remain in the metal fill layer after the reaction. In some embodiments, the metal ion trapping layer may be removed after the reaction. The metal ion trapping layer can reduce metal drift and / or migration, reduce leakage current in adjacent metal gates with different WFM, and improve device performance.

[0061] According to some embodiments, Figure 1A The figure shows an isometric view of FET 100A, and Figure 1D The illustration shows an isometric view of FET 100D. In some embodiments, FETs 100A and 100D may represent a finFET or a GAA FET. In some embodiments, FETs 100A and 100D may include an n-type FET (NFET) adjacent to a p-type FET (PFET), and unless otherwise mentioned, the discussion of FETs 100A and 100D applies to both NFETs and PFETs. Figure 1B The figure shows a cross-sectional view of FET 100A along line AA, showing the relative positions between the metal ion trapping layer 120 and the ILD layer 118. Figure 1E The figure shows a cross-sectional view of FET 100D along the BB line, showing the relative positions between the metal ion trapping layer 121 and the metal filling layer 130. Figures 1G to 1I This illustrates the metal gate layout in a semiconductor device. Unless otherwise stated, Figure 1A , Figure 1B , Figure 1D , Figure 1E ,and Figures 1G to 1I The discussion of elements with the same annotation applies to each other.

[0062] refer to Figure 1A and Figure 1D FETs 100A and 100D can be formed on substrate 104. Other field-effect transistors and / or structures (e.g., isolation structures) can be formed on substrate 104. Substrate 104 can be a semiconductor material, such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. In addition, substrate 104 can be doped with p-type dopants, such as boron (B), indium (In), aluminum (Al), and gallium (Ga), or n-type dopants, such as P and As.

[0063] refer to Figure 1A , Figure 1D ,and Figures 1G to 1I FETs 100A and 100D may include an n-type fin structure 106A and a p-type fin structure 106B disposed on a substrate 104. For example, the n-type fin structure 106A may be doped with an n-type dopant, such as P and As. The p-type fin structure 106B may be doped with a p-type dopant, such as B, In, Al, and Ga. In some embodiments, the n-type fin structure 106A and the p-type fin structure 106B may comprise a material similar to the substrate 104 and extend along the X-axis. For a GAA FET, the n-type fin structure 106A and the p-type fin structure 106B may comprise a first type nanostructure and a second type nanostructure (…). Figure 1A , Figure 1D ,and Figures 1G to 1I (Not shown in the image). The first type of nanostructure may include a semiconductor material similar to substrate 104. The second type of nanostructure may include a semiconductor material similar to or different from substrate 104. In some embodiments, the second type of nanostructure may include silicon, silicon arsenide (SiAs), silicon phosphide (SiP), silicon carbide (SiC), silicon phosphide carbon (SiCP), SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), III-V semiconductor compounds, or other suitable semiconductor materials. The second type of nanostructure may be a nanosheet or a nanowire. The second type of nanostructure may have other geometric cross-sections, such as circular, elliptical, triangular, and polygonal shapes.

[0064] refer to Figure 1A and Figure 1DFETs 100A and 100D may include p-type source / drain (S / D) regions 110A disposed on a portion of the n-type fin structure 106A and n-type source / drain (S / D) regions 110B disposed on a portion of the p-type fin structure 106B. For a PFET, each of the S / D regions 110A may include epitaxially grown semiconductor materials such as Si and SiGe, and p-type dopants such as B and other suitable p-type dopants. For an NFET, each of the S / D regions 110B may include epitaxially grown semiconductor materials such as Si and SiGe, and n-type dopants such as P and other suitable n-type dopants. The doping concentration in each of the S / D regions 110A and 110B may be approximately 1 x 10⁻⁶. 20 atoms / cm 3 To approximately 3 x 10 22 atoms / cm 3 Within the range. In some embodiments, S / D regions 110A and 110B may have a depth of about 50 nm to about 70 nm.

[0065] refer to Figure 1A , Figure 1D ,and Figures 1G to 1I FETs 100A and 100D may include a p-type gate structure 112A disposed on an n-type fin structure 106A and an n-type gate structure 112B disposed on a p-type fin structure 106B (in Figure 1A (Not visible in the image). The p-type gate structure 112A may have a p-type WFM. The p-type WFM may have a work function between about 4.5 eV and about 5.5 eV. The N-type gate structure 112B may have an n-type WFM. The n-type WFM has a work function between about 3.5 eV and about 4.5 eV. In some embodiments, the gate structures 112A and 112B may be multilayer structures. For simplicity, Figure 1A and Figure 1D The multilayer gate structures 112A and 112B are not shown.

[0066] refer to Figure 1B and Figure 1E Each of the gate structures 112A and 112B may include an interface oxide (IO) layer. Figure 1B and Figure 1E (Not shown in the image) A high-k (HK) dielectric layer 122 disposed on the IO layer, and a conductive layer disposed on the HK dielectric layer 122. The IO layer may include SiO2. x SiGeO x or germanium oxide (GeO) xThe HK dielectric layer 122 may include HK dielectric materials such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). The HK dielectric layer 122 may have a thickness H5 between about 1 nm and about 10 nm. The conductive layer may be a multilayer structure. The conductive layer may include a WFM layer disposed on the HK dielectric layer 122 and a metal filling layer 130 disposed on the WFM layer. In some embodiments, the n-type gate structure 112B may include an n-type WFM layer 126. The n-type WFM layer 126 may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium (Ti), aluminum-doped titanium nitride (TiN), aluminum-doped tantalum (Ta), aluminum-doped tantalum nitride (TaN), other suitable aluminum-based materials, and combinations thereof. The n-type WFM layer 126 may include other metal alloys having an N-type work function. In some embodiments, the p-type gate structure 112A may include a p-type WFM layer 124. The p-type WFM layer 124 may include a substantially aluminum-free (e.g., aluminum-free) Ti-based or Ta-based nitride or alloy, such as TiN, titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, TaN, tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, tantalum copper (Ta-Cu), and combinations thereof. The p-type WFM layer 124 may include other metal alloys having a p-type work function. In some embodiments, the WFM layer of the p-type gate structure 112A may include a stack of the same WFM. For example, the WFM layer of the p-type gate structure 112A may include two or more layers of TiN. In some embodiments, the WFM layer of the p-type gate structure 112A may include a stack of different WFMs. For example, the WFM layer of the p-type gate structure 112A may include a p-type WFM layer 124 and an n-type WFM layer 126 disposed on the p-type WFM layer 124.

[0067] For example, such as Figure 1B and Figure 1EAs shown, the p-type gate structure 112A may include a WFM stack, which includes a p-type WFM layer 124 such as TiN and an n-type WFM layer 126 such as TiAl. The n-type gate structure 112B may include an n-type WFM layer 126, such as TiAl. The p-type WFM layer 124 may have a thickness H6 between about 5 nm and about 50 nm. The n-type WFM layer 126 may have a thickness H4 between about 2 nm and about 30 nm. In some embodiments, the p-type gate structure 112A and the n-type gate structure 112B may include a binder layer 128 such as TiN. The binder layer 128 may increase the adhesion of the metal filler layer 130 to the WFM such as the n-type WFM layer 126. The binder layer 128 may have a thickness H3 between about 1 nm and about 10 nm. The metal filler layer 130 may include suitable conductive materials such as tungsten (W), low-fluorine tungsten (LFW), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof. The metal filler layer 130 on the p-type gate structure 112A side may have a thickness H7 between about 2 nm and about 40 nm. The metal filler layer 130 on the n-type gate structure 112B side may have a thickness H2 between about 5 nm and about 60 nm.

[0068] refer to Figure 1A and Figure 1D FETs 100A and 100D may include a gate spacer 114 and a shallow trench isolation (STI) region 116. FETs 100A and 100D may include an etch stop layer (ESL) 117 and an ILD layer 118. The ILD layer 118 may be disposed on the ESL 117. The GAA FET may further include internal spacers ( Figure 1A and Figure 1D (Not shown in the image). In some embodiments, the gate spacer 114, internal spacer, STI region 116, ESL 117, and ILD layer 118 may include an insulating material, such as silicon oxide (SiO2). x Silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeO) x In some embodiments, the gate spacer 114 and the internal spacer may have a thickness between about 2 nm and about 9 nm to ensure that the gate structures 112A and 112B are sufficiently electrically isolated from adjacent structures.

[0069] refer to Figure 1A and Figure 1B FET 100A may include an ILD layer 118 disposed in or near the adjacent region of gate structures 112A and 112B. Figure 1AThe metal ion trapping layer 120 is not visible in the image. The metal ion trapping layer 120 may include a fluorine-rich oxide layer, such as a fluorine-doped metal oxide (MO). x ) and fluorine-doped SiO x If the oxide layer contains more than 10% fluorine (F) atoms, it is considered fluorine-rich. The metal ion trapping layer 120 may have a thickness H1 between about 10 nm and about 20 nm, about 5 nm and about 30 nm, and about 2 nm and about 40 nm. If the thickness H1 is less than about 2 nm, the metal ion trapping layer 120 cannot effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 120 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 120, the reduction of diffused metal ions is ineffective. If the thickness H1 is greater than about 40 nm, the manufacturing cost of forming the metal ion trapping layer 120 may be too high. The width W1 of the metal ion trapping layer 120 may be between about 40 nm and about 100 nm, about 20 nm and about 150 nm, and about 10 nm and about 200 nm. If the width W1 is less than approximately 10 nm, the metal ion trapping layer 120 cannot effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 120 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 120, the reduction of diffused metal ions is ineffective. If the width W1 is greater than approximately 200 nm, the manufacturing cost of forming the metal ion trapping layer 120 may be too high.

[0070] refer to Figure 1CThe aluminum (F) concentration relative to the width is highest at the center (or near) of the metal ion trapping layer 120 or at the center (or near) of the adjacent junctions of gate structures 112A and 112B. F in the metal ion trapping layer 120 can diffuse along the Y-axis towards both sides of the metal ion trapping layer 120. The F concentration can decrease with increasing distance from the center of the metal ion trapping layer 120. The aluminum concentration relative to the width is highest in the n-type WFM layer 126 because it is aluminum-rich TiAl, and lowest in the p-type WFM layer 124 because it is aluminum-free TiN. A WFM alloy is considered aluminum-rich if it contains more than 10% aluminum atoms. Aluminum can diffuse and / or migrate from the n-type WFM layer 126 to the p-type WFM layer 124. At or near the adjacent junctions of gate structures 112A and 112B, Al can react with F from the metal ion trapping layer 120. For example, F and Al can react to form AlF3. This reaction can reduce the aluminum concentration. Since the F concentration is highest at (or near) the center of the metal ion trapping layer 120, the reaction is strongest. Therefore, the aluminum concentration can be lowest at (or near) the center of the metal ion trapping layer 120. At or near the center of the metal ion trapping layer 120, due to this reaction, the aluminum concentration can be similarly lower than the aluminum concentration of the n-type WFM layer 126. This reaction occurs and the aluminum concentration decreases as the metal ion trapping layer 120 is formed. In some embodiments, the ILD layer 118 and the metal ion trapping layer 120 can be removed after the reaction. In some embodiments, with Figure 1A Unlike the example shown, the ILD layer 118 and the metal ion trapping layer 120 are not present in the final FET structure.

[0071] refer to Figure 1D and Figure 1E The FET 100D may include a metal ion trapping layer 121 disposed within gate structures 112A and 112B. For example... Figure 1EAs shown, a metal ion trapping layer 121 may be disposed within a metal filling layer 130 at or near the adjacent region of gate structures 112A and 112B. The metal ion trapping layer 121 may include dopants such as C, N, P, As, Sb, F, and combinations thereof within the metal filling layer 130. The metal ion trapping layer 121 may have a thickness H8 between about 4 nm and about 10 nm, between about 2 nm and about 15 nm, and between about 1 nm and about 20 nm. The ratio between H8 and H7 may be between about 0.2 and about 0.3, between about 0.15 and about 0.4, and between about 0.1 and about 0.5. If the thickness H8 is less than about 1 nm or if the ratio H8 / H7 is less than about 0.1, the metal ion trapping layer 121 cannot effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, the reduction of diffused metal ions is ineffective. If the thickness H8 is greater than about 20 nm or if the ratio H8 / H7 is greater than about 0.5, the manufacturing cost of forming the metal ion trapping layer 121 may be too high. The metal ion trapping layer 121 may have a width W2 between about 40 nm and about 100 nm, between about 20 nm and about 150 nm, and between about 10 nm and about 200 nm. If the width W2 is less than about 10 nm, the metal ion trapping layer 121 cannot effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, the reduction of diffused metal ions is ineffective. If the width W2 is greater than approximately 200 nm, the manufacturing cost of forming the metal ion trapping layer 121 may be too high.

[0072] refer to Figure 1F The concentration of dopants in the diffused and / or implanted metal ion trapping layer 121 may initially increase with depth and then decrease. The point of maximum concentration relative to depth may become shallower with ion implantation and deeper with diffusion. The concentration of dopants implanted at the point of maximum concentration may be greater than the concentration of dopants diffused at the point of maximum concentration. The entire implantation depth may be less than the entire diffusion depth. In some embodiments, the concentration of dopants in the diffused and / or implanted metal ion trapping layer 121 may decrease with depth from the top surface of the metal ion trapping layer 121. In some embodiments, the concentration of dopants in the diffused and / or implanted metal ion trapping layer 121 may be substantially uniform. The dopant concentration in the metal ion trapping layer 121 ranges from approximately 1 x 10⁻⁶. 20 atoms / cm 3 To approximately 3 x 10 22 atoms / cm 3 Approximately 0.8 x 1020 atoms / cm 3 To approximately 3.3 x 10 22 atoms / cm 3 and approximately 0.5 x 10 20 atoms / cm 3 To approximately 3.5 x 10 22 atoms / cm 3 If the concentration is less than approximately 0.5 x 10⁻⁶ 20 atoms / cm 3 If the metal ion trapping layer 121 is not effective in reducing diffused metal ions, then the reduction of diffused metal ions is ineffective. If the metal ion concentration at or near the gate structure with the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, then the reduction of diffused metal ions is ineffective. If the concentration is greater than approximately 3.5 x 10⁻⁶, the reduction is even more significant. 22 atoms / cm 3 If this is not done, the manufacturing cost of forming the metal ion trapping layer 121 may be too high.

[0073] The concentration of doped atoms in the diffused and / or implanted metal ion trapping layer 121 can be similar to that in the reference layer. Figure 1C The F concentration is changed in a manner relative to the width. The Al concentration at or near the junction of gate structures 112A and 112B can be similar to that of the reference. Figure 1C The described change in Al concentration is relative to the width because Al can react with dopant atoms from the metal ion trapping layer 121. For example, the dopant atoms can react with aluminum to form an aluminum compound. This reaction occurs and the Al concentration decreases as the metal ion trapping layer 121 is formed. In some embodiments, the metal ion trapping layer 121 can be removed after the reaction. In some embodiments, with Figure 1D Unlike the example shown, the metal ion trapping layer 121 is not present in the final FET structure.

[0074] Figure 1G The diagram illustrates a metal gate layout design in a semiconductor device. The semiconductor device may include an n-type fin structure 106A and a p-type fin structure 106B. The semiconductor device may include a p-type gate structure 112A disposed on the n-type fin structure 106A and an n-type gate structure 112B disposed on the p-type fin structure 106B. Region A illustrates the adjacent region of the p-type gate structure 112A and the n-type gate structure 112B. Region A may include a metal ion trapping layer 120 or 121. Figure 1G (Not shown in the image). In some embodiments, Figure 1G The semiconductor device shown is a ring oscillator. Ring oscillators can be used to provide clock signals, reference device speed, and power backup.

[0075] Figure 1H The diagram illustrates a metal gate layout design in a semiconductor device. The semiconductor device may include an n-type fin structure 106A and a p-type fin structure 106B. The semiconductor device may include a p-type gate structure 112A disposed on the n-type fin structure 106A and an n-type gate structure 112B disposed on the p-type fin structure 106B. The semiconductor device may include a diced metal gate 132. The diced metal gate 132 may include an isolation structure between adjacent gate structures, thus eliminating the need for metal ion trapping layers 120 or 121. Region B illustrates the adjacent region of the p-type gate structure 112A and the n-type gate structure 112B. Region B may include metal ion trapping layers 120 or 121. Figure 1H (Not shown in the image). In some embodiments, Figure 1H The semiconductor device shown may be a 6-transistor (6T) static random access memory (SRAM). A 6T SRAM can be used to store, read, and write data. A 6T SRAM may include pull-up (PU) transistors, pull-down (PD) transistors, and pass-gate (PG) transistors.

[0076] Figure 1I The diagram illustrates a metal gate layout design in a semiconductor device. The semiconductor device may include an n-type fin structure 106A and a p-type fin structure 106B. The semiconductor device may include a p-type gate structure 112A disposed on the n-type fin structure 106A and an n-type gate structure 112B disposed on the p-type fin structure 106B. The semiconductor device may include a diced metal gate 132. The diced metal gate 132 may include an isolation structure between adjacent gate structures, thus eliminating the need for a metal ion trapping layer 120 or 121. Regions C, D, E, and F show the adjacent regions of the p-type gate structure 112A and the n-type gate structure 112B. Regions C, D, E, and F may include a metal ion trapping layer 120 or 121. Figure 1I (Not shown in the image). Figure 1I The illustration illustrates the versatility of forming the metal ion trapping layer 120 or 121. Optical lithography processes can be used to precisely locate adjacent regions where the metal ion trapping layer 120 or 121 is required. The metal ion trapping layer 120 or 121 can be formed at or near adjacent regions of gate structures with different WFMs. The metal ion trapping layer 120 or 121 can reduce leakage current caused by WFM ion drift and / or migration, and improve device performance.

[0077] According to some embodiments, Figure 2 This is a flowchart describing method 200 for manufacturing FET 100A, such as... Figure 1A and Figure 1BAs shown in the image. For illustrative purposes, reference will be made to... Figures 3 to 10 The example manufacturing process shown is used to describe the fabrication of FET 100A. Figure 2 The operation shown is illustrated. Figures 3 to 10 According to some embodiments, the FET 100A is manufactured at various stages. Figure 1A A cross-sectional view of line AA. Additional manufacturing operations may be performed between the various operations of method 200, but these operations are omitted for simplicity. These additional manufacturing operations are within the spirit and scope of this disclosure. Furthermore, not all operations require the performance of the disclosure provided herein. Additionally, some operations may be performed simultaneously or in conjunction with... Figure 2 The different orders of execution are shown. Figures 3 to 10 The components in have the same Figure 1A and Figure 1B The same annotations as those for the components mentioned above.

[0078] It should be noted that method 200 may not produce a complete FET 100A. Therefore, it should be understood that additional processes may be provided before, during, and after method 200, and some other processes will only be briefly described herein. For example, in some embodiments, the fin structure may be patterned on a semiconductor substrate using an optical lithography process. A polysilicon structure may be deposited over the fin structure using a CVD process and patterned using an optical lithography process. Spacers may be deposited on the polysilicon structure using a CVD process. A portion of the fin structure may be removed using a dry etching process to form an S / D opening, and the S / D region may be epitaxially grown within the S / D opening. In a GAA FET, internal spacers may be deposited using a CVD process prior to the formation of the S / D region. The polysilicon structure may then be removed using a dry etching process to form a gate opening, and a metal gate structure may be formed within the gate opening.

[0079] refer to Figure 2 In operation 202, an HK dielectric layer is deposited in the first opening and the second opening. For example, as... Figure 3 As shown, the HK dielectric layer 122 can be formed in the first gate opening 302 and the second gate opening 304. The first gate opening 302 and the second gate opening 304 are in Figure 3 Sidewalls are not shown. The first gate opening 302 and the second gate opening 304 are adjacent to each other. In some embodiments, the first gate opening 302 can be used to form a p-type metal gate with a p-type WFM, while the second gate opening 304 can be used to form an n-type metal gate with an n-type WFM. The HK dielectric layer 122 can be deposited by a CVD process or a PVD process. In some embodiments, an IO layer can be formed in the first gate opening 302 and the second gate opening 304 by a CVD process or a PVD process. Figure 3 (Not shown in the image).

[0080] refer to Figure 2 In operation 204, a first-type WFM layer is formed on the HK dielectric layer in the first gate opening. For example, as... Figure 4 As shown, the p-type WFM layer 124 can be formed on the HK dielectric layer 122 in the first gate opening 302. The p-type WFM layer 124 can be selectively formed in the first gate opening 302 instead of the second gate opening 304 by an optical lithography patterning process. The p-type WFM layer 124 can be formed by a CVD process, a PVD process, or a metal-organic chemical vapor deposition (MOCVD) process.

[0081] refer to Figure 2 In operation 206, a second-type WFM layer is formed on the HK dielectric layer in the second gate opening. In some embodiments, a second-type WFM layer is formed on the HK dielectric layer in both the first gate opening and the second gate opening. For example, such as Figure 5 As shown, an n-type WFM layer 126 can be formed on the p-type WFM layer 124 in the first gate opening 302 and the HK dielectric layer 122 in the second gate opening 304. The n-type WFM layer 126 can be formed by CVD process, PVD process, or MOCVD process.

[0082] refer to Figure 2 In operation 208, an adhesive layer is formed on the first type WFM layer and the second type WFM layer. In some embodiments, the adhesive layer is formed on the second type WFM layer, wherein the second type WFM layer covers the first type WFM layer. For example, such as Figure 6 As shown, an adhesive layer 128 can be formed on the n-type WFM layer 126 in the first gate opening 302 and the second gate opening 304. The adhesive layer 128 can be formed by CVD process, PVD process, MOCVD process, or ALD process.

[0083] refer to Figure 2 In operation 210, a metal filler layer is formed on the adhesive layer to form a first gate structure and a second gate structure. For example, such as Figure 7 As shown, a metal filler layer 130 may be formed on the adhesive layer 128 in the first gate opening 302 and the second gate opening 304 to form a first gate structure 112A and a second gate structure 112B. The first gate structure 112A and the second gate structure 112B are adjacent to each other. In some embodiments, the first gate structure 112A may be a p-type metal gate having a p-type WFM layer 124, and the second gate structure 112B may be an n-type metal gate having an n-type WFM layer 126. The metal filler layer 130 may be formed by a CVD process, a PVD process, or a MOCVD process.

[0084] refer to Figure 2 In operation 212, dielectric layers are formed on the first gate structure and the second gate structure. For example, such as Figure 8 As shown, the ILD layer 118 can be formed on the metal fill layer 130 on the first gate structure 112A and the second gate structure 112B. The ILD layer 118 can be formed by CVD or PVD processes.

[0085] refer to Figure 2 In operation 214, a portion of the dielectric layer over the adjacent portion of the first gate structure and the second gate structure is removed to form an opening. For example, as... Figure 9 As shown, an opening 902 can be formed in the ILD layer 118 to expose the adjacent regions of the first gate structure 112A and the second gate structure 112B. In some embodiments, the opening 902 can be formed using a fluorocarbon compound (C) having a flow rate in the range of about 100 sccm to about 400 sccm. x F y A dry etching process (e.g., reactive ion etching) using a gas is employed. The etching process can be performed at a temperature of about 10°C to about 90°C and a pressure of about 15 mTorr to about 100 mTorr for a time period of about 10 seconds to about 90 seconds. The etching conditions depend on the size of the opening 902. The etching process may have a higher etching rate in the vertical direction (e.g., the Z-direction) than in the horizontal direction (e.g., the Y-direction). The etching process may have a higher etching rate near the top of the opening 902 than near the bottom of the opening 902. In some embodiments, the opening 902 can be formed by a wet etching process using hydrogen peroxide at a temperature range of about 30°C to about 100°C. In some embodiments, the wet etching process may include a diluted solution of hydrogen fluoride (HF) and a buffer solution, such as ammonium fluoride (NH4F), diluted HF (HF / H2O), phosphoric acid (H3PO4), sulfuric acid and deionized water (H2SO4 / H2O), and combinations thereof. The etching process may be a timed etching process.

[0086] refer to Figure 2 In operation 216, a metal ion trapping layer is formed in the opening. For example, such as... Figure 10As shown, a metal ion trapping layer 120 may be formed in an opening 902 above the adjacent region between the first gate structure 112A and the second gate structure 112B. The metal ion trapping layer 120 may be formed by a CVD process. In some embodiments, the CVD process may use a precursor mixture of an organometallic compound, oxygen, fluorine, or a fluorinated compound with an inert carrier gas. In some embodiments, the CVD process may use a precursor mixture of hexachlorodisilazane (HCDS), oxygen, fluorine, or a fluorinated compound with an inert carrier gas. In some embodiments, the CVD process may be performed at a temperature of about 20°C to about 200°C and a pressure of about 30 Torr to about 150 Torr for a period of about 10 seconds to about 150 seconds. In some embodiments, the CVD process may be performed at atmospheric pressure. If the deposition time is less than about 10 seconds, or the temperature is less than about 20°C, or the pressure is less than about 30 Torr, the deposited metal ion trapping layer 120 may be too thin and may not effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure with the metal ion trapping layer 120 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 120, the reduction of diffused metal ions is ineffective. If the deposition time is greater than about 150 seconds, the temperature is greater than about 200°C, or the pressure is greater than about 150 Torr, the manufacturing cost of forming the metal ion trapping layer 120 may be too high. The metal ion trapping layer 120 can reduce leakage current caused by WFM ion drift and / or migration and improve device performance.

[0087] According to some embodiments, Figure 11 This is a flowchart describing method 1100 for manufacturing FET 100D, such as... Figure 1D and Figure 1E As shown in the image. For illustrative purposes, reference will be made to... Figures 12 to 18 The example manufacturing process shown is used to describe the fabrication of FET 100D. Figure 11 The operation shown is illustrated. Figures 12 to 18 According to some embodiments, the FET 100D is manufactured at various stages. Figure 1D A cross-sectional view of line BB. Additional manufacturing operations may be performed between the various operations of method 1100; for simplicity, these operations are omitted. These additional manufacturing operations are within the spirit and scope of this disclosure. Furthermore, not all operations require the performance of the disclosure provided herein. Additionally, some operations may be performed simultaneously or in conjunction with… Figure 11 The different orders of execution are shown. Figures 12 to 18 Components and Figure 1D and Figure 1EThe components in this paper have the same markings as described above. It should be noted that method 1100 may not produce a complete FET 100D. Therefore, it should be understood that additional processes may be provided before, during, and after method 1100, and some other processes are only briefly described here.

[0088] refer to Figure 11 In operation 1102, an HK dielectric layer is deposited in the first gate opening and the second gate opening. For example, as... Figure 12 As shown, an HK dielectric layer 122 can be formed in the first gate opening 302 and the second gate opening 304. The first gate opening 302 and the second gate opening 304 are in... Figure 12 Sidewalls are not shown. HK dielectric layer 122 can be similar to the reference. Figure 3 and Figure 2 The operation is formed in the manner described in operation 202.

[0089] refer to Figure 11 In operation 1104, a first-type WFM layer is formed on the HK dielectric layer in the first gate opening. For example, as... Figure 13 As shown, a p-type WFM layer 124 may be formed on the HK dielectric layer 122 in the first gate opening 302. The p-type WFM layer 124 may be similar to the reference... Figure 4 and Figure 2 The operation is formed in the manner described in operation 204.

[0090] refer to Figure 11 In operation 1106, a second type WFM layer is formed over the HK dielectric layer in the second gate opening. In some embodiments, a second type WFM layer is formed on the HK dielectric layers in both the first and second gate openings. For example, such as Figure 14 As shown, an n-type WFM layer 126 can be formed on the p-type WFM layer 124 in the first gate opening 302 and the HK dielectric layer 122 in the second gate opening 304. The n-type WFM layer 126 can be similar to the reference. Figure 5 and Figure 2 The operation is formed in the manner described in operation 206.

[0091] refer to Figure 11 In operation 1108, an adhesive layer is formed on the first type WFM layer and the second type WFM layer. In some embodiments, the adhesive layer is formed on the second type WFM layer, wherein the second type WFM layer covers the first type WFM layer. For example, such as Figure 15 As shown, an adhesive layer 128 can be formed on the n-type WFM layer 126 in the first gate opening 302 and the second gate opening 304. The adhesive layer 128 can be similar to the reference. Figure 6 and Figure 2 The operation is formed in the manner described in operation 208.

[0092] refer to Figure 11 In operation 1110, a metal filler layer is formed on the adhesive layer to form a first gate structure and a second gate structure. For example, such as Figure 16 As shown, a metal filler layer 130 may be formed on the adhesive layer 128 in the first gate opening 302 and the second gate opening 304 to form a first gate structure 112A and a second gate structure 112B. The first gate structure 112A and the second gate structure 112B are adjacent to each other. In some embodiments, the first gate structure 112A may be a p-type metal gate having a p-type WFM layer 124, and the second gate structure 112B may be an n-type metal gate having an n-type WFM layer 126. The metal filler layer 130 may be similar to the reference reference. Figure 7 and Figure 2 The operation is formed in the manner described in operation 210.

[0093] refer to Figure 11 In operation 1112, a metal ion trapping layer is formed in the top portion of the metal filling layer above the adjacent portion of the first gate structure and the second gate structure. For example, such as Figure 17 As shown, a photoresist layer 1702 can be spin-coated onto the metal filler layer 130. An opening 1704 can be formed above the adjacent region of the first gate structure 112A and the second gate structure 112B by transferring a pattern of a photomask, such as a master photomask, onto the photoresist layer 1702 through exposure and development processes. The opening 1704 can be exposed to thermal diffusion, ALD diffusion, wet diffusion, or ion implantation processes. In some embodiments, the ion implantation process may be plasma-enhanced. Figure 18 As shown, after a diffusion process or an ion implantation process, a metal ion trapping layer 121 can be formed in the top portion of the metal filling layer 130 above the adjacent region of the first gate structure 112A and the second gate structure 112B.

[0094] In some embodiments, the metal ion trapping layer 121 may be formed by a thermal diffusion process. In some embodiments, the thermal diffusion process may use a doping gas containing C, N, P, As, Sb, F, and combinations thereof. For example, the doping gas may include arsine (AsH3), phosphine (PH3), sulfur hexafluoride (SF6), bromotrifluoromethane (CBrF3), and combinations thereof. In some embodiments, the thermal diffusion process may be performed in a temperature range of about 50°C to about 300°C, about 30°C to about 400°C, and about 20°C to about 500°C. If the temperature is below about 20°C, the metal ion trapping layer 121 diffused into the metal fill layer 130 may be too thin and cannot effectively reduce the diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, the reduction of diffused metal ions is ineffective. If the temperature exceeds approximately 500°C, the manufacturing cost of forming the metal ion trapping layer 121 may be too high. In some embodiments, the metal ion trapping layer 121 may be formed by an ALD diffusion process or a wet diffusion process.

[0095] In some embodiments, the metal ion trapping layer 121 can be formed by an ion implantation process. In some embodiments, the ion implantation process may include dopant species containing C, N, P, As, Sb, F, and combinations thereof. In some embodiments, the ion implantation process may use an incident angle of approximately 0°. The ion beam energy may be between approximately 1 keV and approximately 10 keV, between approximately 0.8 keV and approximately 12 keV, and between approximately 0.5 keV and approximately 15 keV. The dose of the dopant species may be between approximately 1 x 10⁻⁶. 12 ions / cm 2 With approximately 1x10 15 ions / cm 2 Between, approximately 0.8 x 10 12 ions / cm 2 With approximately 1.2 x 10 15 ions / cm 2 Between, and approximately 0.5 x 10 12 ions / cm 2 With approximately 1.5 x 10 15 ions / cm 2 Between. If the ion beam energy is less than about 0.5 keV or the dose of the dopant species is less than about 0.5 x 10⁻⁶. 12 ions / cm 2If the metal ion trapping layer 121 implanted in the metal filling layer 130 is too thin, it may not effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure with the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, the reduction of diffused metal ions is ineffective. If the ion beam energy is greater than approximately 15 keV or the dose of the dopant species is greater than approximately 1.5 x 10⁻⁶, the reduction of diffused metal ions will also be ineffective. 15 ions / cm 2 If this is not done, the manufacturing cost of forming the metal ion trapping layer 121 may be too high.

[0096] In some embodiments, the ion implantation process may be plasma-enhanced. Enhanced ion implantation can be performed at pressures ranging from about 1 mTorr to about 100 mTorr and power ranging from about 500 V to about 1000 V. If the power is less than about 500 V or the pressure is less than about 1 mTorr, the metal ion trapping layer 121 implanted in the metal filler layer 130 may be too thin and cannot effectively reduce diffused metal ions. If the metal ion concentration at or near the gate structure having the metal ion trapping layer 121 is greater than 75% of the metal ion concentration at or near the gate structure without the metal ion trapping layer 121, the reduction of diffused metal ions is ineffective. If the power is greater than about 1000 V or the pressure is greater than about 100 mTorr, the manufacturing cost of forming the metal ion trapping layer 121 may be too high. The metal ion trapping layer 121 can reduce leakage current caused by WFM ion drift and / or migration and improve device performance.

[0097] This disclosure provides example FET structures (e.g., FET 100A and 100D, GAA FET, finFET, or planar FET) having metal ion trapping layers (e.g., metal ion trapping layers 120 and 121) in semiconductor devices and / or ICs, and example methods (e.g., methods 200 and 1100) for manufacturing them. In some embodiments, the metal ion trapping layer (e.g., metal ion trapping layer 120) may be formed in an interlayer dielectric (ILD) layer (e.g., ILD layer 118) above an adjacent metal gate having a different WFM. An opening (e.g., opening 902) may be formed in the ILD layer by a dry etching process or a wet etching process. The metal ion trapping layer may be formed by depositing a fluorine-rich oxide layer in the opening using a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. An oxide layer is considered fluorine-rich if the percentage of fluorine atoms in the oxide layer exceeds 10%. Fluorine in the fluorine-rich oxide layer can react with metal ions diffusing from the high-concentration side of the WFM to the low-concentration side, thereby reducing metal drift and / or migration. For example, fluorine (F) can react with aluminum (Al) to form aluminum fluoride (AlF3). This reaction can occur during the deposition of the fluorine-rich oxide layer. In some embodiments, the fluorine-rich oxide layer can be retained in the ILD layer after the reaction. In some embodiments, the fluorine-rich oxide layer can be removed after the reaction.

[0098] In some embodiments, a metal ion trapping layer (e.g., metal ion trapping layer 121) may be formed in a metal filler layer (e.g., metal filler layer 130) with a different WFM adjacent metal gate. In some embodiments, the metal ion trapping layer may be formed by diffusing C, N, P, As, Sb, F, and combinations thereof in the metal filler layer via a thermal diffusion process, an ALD diffusion process, or a wet diffusion process. In some embodiments, the metal ion trapping layer may be formed by implanting C, N, P, As, Sb, F, and combinations thereof in the metal filler layer via an ion implantation process. In some embodiments, the ion implantation process may be plasma-enhanced. The region to be diffused or implanted may be defined by a photoresist layer (e.g., photoresist layer 1702). The C, N, P, As, Sb, F, and combinations thereof in the metal ion trapping layer may react with metal ions diffusing from the high concentration side to the low concentration side of the WFM, thereby reducing metal drift and / or migration. For example, C, N, P, As, Sb, F, and Al may react to form an aluminum compound. This reaction may occur during the formation of the metal ion trapping layer. In some embodiments, the metal ion trapping layer may remain in the metal fill layer after the reaction. In some embodiments, the metal ion trapping layer may be removed after the reaction. The metal ion trapping layer can reduce metal drift and / or migration, reduce leakage current in adjacent metal gates with different WFM, and improve device performance.

[0099] In some embodiments, a method of forming a semiconductor structure includes forming a first fin structure and a second fin structure on a substrate, and forming a first gate structure over the first fin structure and a second gate structure over the second fin structure, wherein the first gate structure and the second gate structure are adjacent to each other. The method further includes forming a dielectric layer on the first gate structure and the second gate structure, removing a portion of the dielectric layer over the adjacent portion of the first gate structure and the second gate structure to form an opening, and forming a metal ion trapping layer in the opening. In some embodiments, the step of forming the first gate structure and the second gate structure includes forming an interface oxide layer and a high-k dielectric layer on the interface oxide layer. In some embodiments, the step of forming the first gate structure includes forming a first-type work function metal layer and a metal fill layer, wherein the step of forming the second gate structure includes forming a second-type work function metal layer and the metal fill layer, which is different from the first type. In some embodiments, the step of forming the first gate structure and the second gate structure further includes forming a binder layer on the first-type work function metal layer and the second-type work function metal layer. In some embodiments, the step of forming the first gate structure includes forming an aluminum-free work function metal layer, and the step of forming the second gate structure includes forming an aluminum-rich work function metal layer. In some embodiments, the step of removing the portion of the dielectric layer includes etching the portion of the dielectric layer by a dry etching process or a wet etching process. In some embodiments, the step of forming the metal ion trapping layer includes depositing a fluorine-rich oxide layer in the opening by a chemical vapor deposition process or a physical vapor deposition process. In some embodiments, the step of forming the metal ion trapping layer includes forming a fluorine-rich oxide layer having a width of at least about 50 nanometers. In some embodiments, the step of forming the metal ion trapping layer includes reacting the metal ion trapping layer with a plurality of metal ions diffused from a work function metal layer of the second gate structure. In some embodiments, the step of forming the metal ion trapping layer includes reducing an aluminum concentration in the adjacent portion of the first gate structure and the second gate structure.

[0100] In some embodiments, a method of forming a semiconductor structure includes forming a first gate structure, wherein forming the first gate structure includes forming a first type work function metal (WFM) layer and a metal fill layer. The method further includes forming a second gate structure adjacent to the first gate structure, wherein forming the second gate structure includes forming a second type WFM layer and a metal fill layer, and wherein the second type WFM layer is different from the first type WFM layer. The method further includes forming a mask layer with an opening over the adjacent portion of the first gate structure and the second gate structure, forming a metal ion trapping layer in the top portion of the metal fill layer exposed by the opening, and removing the mask layer. In some embodiments, the step of forming the first type work function metal layer includes forming an aluminum-free work function metal layer, and the step of forming the second work function metal layer includes forming an aluminum-rich work function metal layer. In some embodiments, the step of forming the metal ion trapping layer includes diffusing carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof in the metal fill layer by a thermal diffusion process, an atomic layer deposition diffusion process, or a wet diffusion process. In some embodiments, the step of forming the metal ion trapping layer includes implanting carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof into the metal filler layer by an ion implantation process or a plasma-enhanced ion implantation process. In some embodiments, the step of forming the metal ion trapping layer includes reacting the metal ion trapping layer with a plurality of metal ions diffused from the second type work function metal layer of the second gate structure. In some embodiments, the step of forming the metal ion trapping layer includes reducing an aluminum concentration in the adjacent portion of the first gate structure and the second gate structure.

[0101] In some embodiments, a semiconductor structure includes a first fin structure and a second fin structure on a substrate, and a first gate structure above the first fin structure. The first gate structure includes a first type work function metal (WFM) layer and a metal fill layer. The structure further includes a second gate structure above the second fin structure and adjacent to the first gate structure. The second gate structure includes a second type WFM layer, wherein the second type WFM layer is different from the first type WFM layer; and a metal fill layer. The structure further includes a metal ion trapping layer in the top portion of the metal fill layer above the adjacent portion of the first gate structure and the second gate structure. In some embodiments, the metal ion trapping layer comprises carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof. In some embodiments, the metal ion trapping layer has a width of at least about 50 nm. In some embodiments, a first aluminum concentration in the adjacent portion of the first gate structure and the second gate structure is lower than a second aluminum concentration in the second type work function metal layer of the second gate structure.

[0102] It should be understood that the Description of Embodiments section, rather than the Summary of Invention section, is intended to be used to interpret the claims. The Summary of Invention section may set forth one or more, but not all, possible embodiments of this disclosure conceived by the inventors(s), and therefore the summary of this disclosure is not intended to limit the appended claims in any way.

[0103] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, Include: A first fin structure and a second fin structure are formed on a substrate; A first gate structure is formed above the first fin structure, and a second gate structure is formed above the second fin structure, wherein the first gate structure and the second gate structure are adjacent to each other. A dielectric layer is formed on the first gate structure and the second gate structure; Remove a portion of the dielectric layer over an adjacent portion of the first gate structure and the second gate structure to form an opening; and A metal ion trapping layer is formed in the opening.

2. The method as described in claim 1, characterized in that, The steps of forming the first gate structure and the second gate structure include forming an interface oxide layer and a high-k dielectric layer on the interface oxide layer.

3. The method as described in claim 1, characterized in that, The step of forming the first gate structure includes: forming a first type work function metal layer and a metal fill layer, and the step of forming the second gate structure includes: forming a second type work function metal layer and the metal fill layer that are different from the first type.

4. The method as described in claim 3, characterized in that, The step of forming the first gate structure and the second gate structure further includes: forming an adhesive layer on the first type work function metal layer and the second type work function metal layer.

5. The method as described in claim 1, characterized in that, The step of forming the first gate structure includes forming an aluminum-free work function metal layer, and the step of forming the second gate structure includes forming an aluminum-rich work function metal layer.

6. The method as described in claim 1, characterized in that, The step of removing the portion of the dielectric layer includes etching the portion of the dielectric layer by a dry etching process or a wet etching process.

7. The method as described in claim 1, characterized in that, The step of forming the metal ion trapping layer includes depositing a fluorine-rich oxide layer in the opening by a chemical vapor deposition process or a physical vapor deposition process.

8. The method as described in claim 1, characterized in that, The step of forming the metal ion trapping layer includes: forming a fluorine-rich oxide layer with a width of at least 50 nanometers.

9. The method as described in claim 1, characterized in that, The step of forming the metal ion trapping layer includes reacting the metal ion trapping layer with a plurality of metal ions diffused from a work function metal layer of the second gate structure.

10. The method as described in claim 1, characterized in that, The step of forming the metal ion trapping layer includes: reducing the aluminum concentration in the adjacent portion of the first gate structure and the second gate structure.

11. A method for forming a semiconductor structure, characterized in that, Include: A first gate structure is formed, wherein forming the first gate structure includes forming a first type work function metal layer and a metal fill layer; A second gate structure is formed adjacent to the first gate structure, wherein forming the second gate structure includes forming a second type work function metal layer and the metal filling layer, and wherein the second type work function metal layer is different from the first type work function metal layer; A masking layer with an opening is formed on an adjacent portion of the first gate structure and the second gate structure; A metal ion trapping layer is formed in a top portion of the metal-filled layer exposed by the opening; and Remove the mask layer.

12. The method as described in claim 11, characterized in that, The step of forming the first type of work function metal layer includes forming an aluminum-free work function metal layer, and the step of forming the second type of work function metal layer includes forming an aluminum-rich work function metal layer.

13. The method as described in claim 11, characterized in that, The step of forming the metal ion trapping layer includes diffusing carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof into the metal filling layer by a thermal diffusion process, an atomic layer deposition diffusion process, or a wet diffusion process.

14. The method as described in claim 11, characterized in that, The step of forming the metal ion trapping layer includes implanting carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof into the metal filling layer by an ion implantation process or a plasma-enhanced ion implantation process.

15. The method as described in claim 11, characterized in that, The step of forming the metal ion trapping layer includes reacting the metal ion trapping layer with a plurality of metal ions diffused from the second type work function metal layer of the second gate structure.

16. The method as described in claim 11, characterized in that, The step of forming the metal ion trapping layer includes reducing the aluminum concentration in the adjacent portion of the first gate structure and the second gate structure.

17. A semiconductor structure, characterized in that, Include: A first fin structure and a second fin structure on a substrate; A first gate structure is located above the first fin structure, the first gate structure comprising: A first-type work function metal layer; and A metal filler layer; A second gate structure is located above the second fin structure and adjacent to the first gate structure, the second gate structure comprising: A second type work function metal layer, wherein the second type work function metal layer is different from the first type work function metal layer; and The metal filler layer; and A metal ion trapping layer is located in a top portion of the metal filling layer above an adjacent portion of the first gate structure and the second gate structure.

18. The semiconductor structure as claimed in claim 17, characterized in that, The metal ion trapping layer contains carbon (C), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), fluorine (F), and combinations thereof.

19. The semiconductor structure as claimed in claim 17, characterized in that, The metal ion trapping layer has a width of at least 50 nm.

20. The semiconductor structure as claimed in claim 17, characterized in that, The first aluminum concentration in the adjacent portion of the first gate structure and the second gate structure is lower than the second aluminum concentration in the second type work function metal layer of the second gate structure.

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