Test key structure for semiconductor elements

Abstract

A test key structure of a semiconductor device includes a substrate, a gate structure on the substrate, and a plurality of first dummy gate structures on the substrate and surrounding the gate structure, wherein a bottom surface of the gate structure is lower than bottom surfaces of the plurality of first dummy gate structures, and a top surface of the gate structure is flush with top surfaces of the plurality of first dummy gate structures.

Description

Technical Field

[0001] This invention relates to a test bond structure for semiconductor devices, and more particularly to a test bond structure for monitoring metal gate structures of semiconductor devices. Background Technology

[0002] In advanced semiconductor manufacturing processes, replacement metal gate fabrication is widely used to create metal gates. The process involves removing the sacrificial gate structure from the interlayer dielectric layer to form a gate trench, and then filling the trench with metal gate material (e.g., a work function metal layer and a low-resistivity metal layer) to obtain the replacement metal gate. The aspect ratio and opening profile of the gate trench significantly affect the filling capability of the metal gate material. An excessively large aspect ratio or an excessively small opening may cause premature sealing, resulting in void defects. Currently, optical defect inspection methods (e.g., bright field inspection) are used on production lines to check for void defects. However, optical defect inspection methods are limited by slow inspection speeds, allowing only a portion of wafers to be inspected to avoid impacting throughput. Furthermore, if void defects are buried inside the metal gate, they are difficult to identify using optical defect inspection methods.

[0003] Therefore, there is still a need in the art for a test bond structure that can quickly and effectively detect defects in poor metal gate filling online. Summary of the Invention

[0004] The purpose of this invention is to provide a test bond structure for semiconductor devices. More specifically, this invention provides a test bond structure for measuring the resistance of a gate structure. The WAT resistance data of this test bond structure can be analyzed to monitor whether any abnormalities have occurred in the metal gate structure of the semiconductor device.

[0005] According to an embodiment of the present invention, the test bond structure of a semiconductor device includes a substrate, a gate structure located on the substrate, and a plurality of first dummy gate structures located on the substrate and surrounding the gate structure, wherein a bottom surface of the gate structure is lower than the bottom surface of the plurality of first dummy gate structures, and a top surface of the gate structure is flush with the top surface of the plurality of first dummy gate structures. Attached Figure Description

[0006] Figure 1 This is a planar schematic diagram of a semiconductor element according to an embodiment of the present invention;

[0007] Figure 2 This is a planar schematic diagram of the test bond structure of the semiconductor element according to the first embodiment of the present invention;

[0008] Figures 3 to 8 They are Figure 2 A schematic diagram of the test key structure along tangent II at different stages of the manufacturing process;

[0009] Figure 9 This is a cross-sectional schematic diagram of the test key structure according to the second embodiment of the present invention;

[0010] Figure 10 This is a cross-sectional schematic diagram of the test key structure according to the third embodiment of the present invention;

[0011] Figure 11 This is a planar schematic diagram of the test key structure according to the fourth embodiment of the present invention;

[0012] Figure 12 This is a planar schematic diagram of the test bond structure of the semiconductor element according to the fifth embodiment of the present invention;

[0013] Figure 13 for Figure 12 A cross-sectional schematic diagram of the test bond structure along the tangent I-I';

[0014] Figure 14 This is a cross-sectional schematic diagram of the test key structure according to the sixth embodiment of the present invention;

[0015] Figure 15 This is a cross-sectional schematic diagram of the test key structure according to the seventh embodiment of the present invention;

[0016] Figure 16 This is a planar schematic diagram of the test key structure according to the eighth embodiment of the present invention.

[0017] Explanation of main component symbols

[0018] 100 base

[0019] 102 Active (Active) Region

[0020] 103. Virtual Active Zone

[0021] 104 Isolation Structure

[0022] 106 mask layers

[0023] 120 Sacrificial Material Layer

[0024] 122 Sacrificial Gate Structure

[0025] 124 Sacrificial Gate Structure

[0026] 126 Sacrificial Gate Structure

[0027] 132 Spacer wall

[0028] 134 Spacer wall

[0029] 140 Etching Stop Layer

[0030] 142 interlayer dielectric layer

[0031] 160 contact plug

[0032] 222 gate structure

[0033] 224 First Dummy Gate Structure

[0034] 226 Second Dummy Gate Structure

[0035] 104R dent

[0036] 122a Gate Trench

[0037] 124a Gate Trench

[0038] 126a Gate Trench

[0039] 140a Beak-like portion

[0040] 142a surface

[0041] 222a Bottom surface

[0042] 222b Top surface

[0043] 224a bottom surface

[0044] 224b Top surface

[0045] 230 Porous defects

[0046] A1 First District

[0047] A2 Second District

[0048] D1 Depth

[0049] H1 height

[0050] H2 height

[0051] II' Tangent

[0052] P1 Etching process

[0053] P2 Patterning process

[0054] P3 Remove manufacturing process

[0055] P4 Remove manufacturing process

[0056] P5 Etching Process

[0057] R1 chip area

[0058] R2 Cutting Zone

[0059] R3 Test Keyboard

[0060] S1 Spacing

[0061] SH step difference

[0062] T1 thickness

[0063] TG gate dielectric layer

[0064] X Second Direction

[0065] Y First direction

[0066] Z Third Direction Detailed Implementation

[0067] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below, along with the accompanying drawings, to explain in detail the composition and desired effects of the invention. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments to achieve other embodiments without departing from the spirit of the invention.

[0068] To facilitate reader comprehension and maintain the simplicity of the accompanying drawings, many of the accompanying drawings depict only a portion of the display device, and specific elements in the drawings are not drawn to scale. Furthermore, the number and dimensions of each element in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention. In the drawings, identical or similar elements can be represented by the same reference numerals. The description of the vertical relationships between relative elements in the drawings should be understood by those skilled in the art to refer to the relative positions of objects; therefore, the same components can be flipped to present the same information, and all of this should fall within the scope disclosed in this specification.

[0069] In this specification, "wafer," "substrate," or "base plate" means any structure having an exposed surface on which material can be deposited to fabricate an integrated circuit structure according to embodiments of the present invention. It should be understood that "substrate" includes, but is not limited to, semiconductor wafers. In the context of fabrication processes, "substrate" also means a semiconductor structure containing a layer of material fabricated thereon.

[0070] Please refer to Figure 1The diagram illustrates a planar schematic of a semiconductor device according to an embodiment of the present invention. The semiconductor device is, for example, a wafer W, which may include multiple chip regions R1 and dicing channels R2 located between the chip regions R1. Chip regions R1 are areas for fabricating integrated circuit chips. Dicing channels R2 are used to dice the wafer W to separate the individual chip regions R1 after the wafer W fabrication process is completed. Various alignment mark patterns, monitoring patterns, and test key structures used in the wafer W manufacturing process may be provided within the dicing channels R2. Figure 1 As shown, the dicing area R2 of wafer W may include multiple test key areas R3, respectively located near the center and edge of the wafer. The test key areas R3 may contain test key structures, allowing measurement steps to be inserted at different fabrication stages to measure the test key structures. The measured data is then analyzed to monitor the fabrication process, enabling timely detection of fabrication anomalies and ensuring that the integrated circuit structure on wafer W meets required specifications.

[0071] Please refer to Figure 2 . Figure 2 The diagram illustrates a planar schematic of the test bond structure of a semiconductor element according to a first embodiment of the present invention. The semiconductor element is, for example, a... Figure 1 The chip W shown is Figure 2 The test bond structure can be set in any one or more test bond regions R3 within the dicing zone R2 of the wafer W. For simplified illustration, Figure 2 Some detailed structures, such as spacer walls, etch stop layers, and interlayer dielectric layers, have been omitted.

[0072] like Figure 2 As shown, the test key structure includes a substrate 100, which includes multiple first regions A1 and second regions A2 located between the first regions A1. An isolation structure 104 is disposed in the first regions A1 and second regions A2 of the substrate 100. A gate structure 222 extending along a first direction Y is disposed on the isolation structure 104 in the second region A2 of the substrate 100. Multiple first dummy gate structures 224 extending along the first direction Y are disposed in the first regions A1 and arranged around the gate structure 222. Contact plugs 160 may be provided at both ends of the gate structure 222 for electrically connecting the gate structure 222 to an external circuit to measure the resistance of the gate structure 222. The first dummy gate structures 224 are not electrically connected to any conductive structure and are electrically isolated from the outside.

[0073] To obtain a more reliable resistance measurement, the gate structure 222 needs to have a sufficient length along the first direction Y. According to one embodiment of the present invention, the length of the gate structure 222 along the first direction Y is preferably not less than 15 μm.

[0074] To effectively monitor the stability of the gate replacement fabrication process, the width of the gate structure 222 along the second direction X is preferably designed according to the minimum gate line width provided by the design rule. For example, when the minimum gate width allowed by the design rule is 0.03 μm, the width of the gate structure 222 can be designed to be 0.03 μm, 0.035 μm, 0.04 μm, 0.045 μm, 0.05 μm, or a width within the range defined by the above values. The length of the first dummy gate structure 224 along the first direction Y is preferably greater than or equal to the length of the gate structure 222 along the first direction Y. For example, when the length of the gate structure 222 is approximately 15 μm, the first dummy gate structure 224 can be greater than or equal to 15 μm. The width of the first dummy gate structure 224 along the second direction X is preferably greater than the width of the gate structure 222 along the second direction X, for example, it can be approximately 2 to 5 times the width of the gate structure 222. For example, when the width of the gate structure 222 is approximately 0.03 μm, the width of the first dummy gate structure 224 can be approximately 0.135 μm. The gate structure 222 and the adjacent first dummy gate structures 224 on both sides have a spacing S1. According to some embodiments of the present invention, the spacing S1 can be approximately 0.2 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, or a spacing within the range defined by the above values.

[0075] In some embodiments, the test bond structure may further include dummy gate structures, such as a pair of second dummy gate structures 226 parallel to the gate structure 222 disposed on the isolation structures 104 on both sides of the gate structure 222, and a plurality of third dummy gate structures 128 disposed on the isolation structures 104 of the second region A2 and surrounding the first region A1. The length and width of the second dummy gate structure 226 may be the same as those of the gate structure 222. The length and width of the third dummy gate structure 128 may be smaller than those of the first dummy structure 224 and the second dummy structures. In some embodiments, the second dummy gate structure 226 is fabricated on the substrate 100 using the same replacement metal gate process as the gate structure 222 and the first dummy gate structure 224, and includes the same metal material. In some embodiments, the material of the third dummy gate structure 128 is different from that of the gate structure 222 and the first dummy gate structure 224, for example, it may include polysilicon.

[0076] Please refer to Figures 3 to 8 They are respectively Figure 2 The test key structure is shown in a cross-sectional view along tangent II at different stages of the manufacturing process. (See diagram.) Figure 3As shown, a substrate 100 is first provided, such as a silicon substrate, a silicon-on-insulator (SOI) substrate, a silicon-germanium substrate, a group III-V semiconductor substrate, or a substrate made of other suitable materials. Next, an isolation structure 104 is formed in the substrate 100 to pattern the substrate 100 and define an active region (not shown). The isolation structure 104 can be a shallow trench isolation (STI) structure or a region silicon oxide isolation (LOCOS) structure, and is made of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorosilicone glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or combinations of the above materials. Next, a gate dielectric layer TG, such as a silicon monoxide (SiO2) layer or a high-k dielectric layer, can be comprehensively formed on the substrate 100 using deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Then, a mask layer 106 (e.g., a patterned photoresist layer) can be formed to cover the gate dielectric layer TG on the first region A1 of the substrate 100 and expose the gate dielectric layer TG on the second region A2. An etching process P1 is then performed on the gate dielectric layer TG using the mask layer 106 as an etching mask until the gate dielectric layer TG on the second region A2 is completely removed, exposing the underlying isolation structure 104.

[0077] like Figure 4 As shown, after removing the mask layer 106, a sacrificial material layer 120 (e.g., a polysilicon layer) can be formed comprehensively on the substrate 100 using a chemical vapor deposition (CVD) process. Since the gate dielectric layer TG directly above the second region A2 is selectively removed, the surface of the sacrificial material layer 120 directly above the second region A2 is lower than the surface of the sacrificial material layer 120 directly above the first region A1, with a step difference SH between them. In this embodiment, the height of the step difference SH is approximately determined by the thickness of the gate dielectric layer TG.

[0078] like Figure 5As shown, a patterning process P2 (e.g., photolithography and etching) can then be performed on the sacrificial material layer 120 to obtain sacrificial gate structures 122 and 126 located directly above the second region A2 and sacrificial gate structure 124 located directly above the first region A1. The top surfaces of the sacrificial gate structures 122 and 126 are lower than the top surface of the sacrificial gate structure 124, for example, by approximately the height difference of a step difference SH. In some embodiments, the tops of the sacrificial gate structures 122, 124, and 126 may have a bowing profile. In some embodiments, a portion of the sacrificial material layer 120 may be patterned into a third dummy gate structure 128 (see reference). Figure 2 ).

[0079] like Figure 6As shown, spacer walls 132 (first spacer walls) are then formed on the sidewalls of the sacrificial gate structures 122 and 126, and spacer walls 134 (second spacer walls) are formed on the sidewalls of the sacrificial gate structure 124, using one or more deposition / etching processes. A deposition process is then performed to form an etch stop layer 140 and an interlayer dielectric layer 142 on the substrate 100, completely covering the sacrificial gate structures 122, 124, and 126 and filling the gaps between them. Next, a removal process P3 (e.g., chemical mechanical polishing) is performed to remove a portion of the interlayer dielectric layer 142 until the etch stop layer 140 on the top surface of the sacrificial gate structures 122, 124, and 126 is exposed. Then, another removal process P4 (e.g., chemical mechanical polishing or etching) is performed to remove a portion of the etch stop layer 140 until the top of the sacrificial gate structures 122, 124, and 126 is exposed. Spacer 132, spacer 134, and etch stop layer 140 can each be a single-layer or multi-layer structure, and the materials can include, but are not limited to, dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), etc. The interlayer dielectric layer 142 can include dielectric materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low-k dielectric materials such as fluorosilicone glass (FSG), silicon carbide oxide (SiCOH), spin-on glass, porous low-k dielectric materials, organic polymer dielectric materials, or combinations of the above materials. In some embodiments, the top of the arcuate profile of the sacrificial gate structure 124 (e.g., the portion above the top surface of spacer 134) can be completely removed during the removal fabrication process P4 to form a flat top profile. The top surface of spacer wall 134 is exposed from the surface of interlayer dielectric layer 142 and is generally flush with the surface of interlayer dielectric layer 142. In some embodiments, the top of sacrificial gate structures 122, 126 may be partially removed in removal fabrication process P4 while retaining most of the arcuate profile. The top surface of spacer wall 132 is lower than the top surface of sacrificial gate structures 122, 126 and is covered by etch stop layer 140 and is not exposed.

[0080] like Figure 7 and Figure 8As shown, a replacement metal gate process is then performed to replace the sacrificial gate structures 122, 124, and 126 with gate structure 222, the first dummy gate structure 224, and the second dummy gate structure 226. The replacement metal gate fabrication process includes first performing an etching process P5 (e.g., a wet etching process) to remove the sacrificial gate structures 122, 124, and 126 to form gate trenches 122a, 124a, and 126a in the interlayer dielectric layer 142. Then, a high-dielectric-constant dielectric layer and metal gate material are formed to fill the gate trenches 122a, 124a, and 126a. Next, a chemical mechanical polishing (CMP) or etching process is used to remove the high-dielectric-constant dielectric layer and metal gate material outside the gate trenches 122a, 124a, and 126a until the surface 142a of the interlayer dielectric layer 142 is exposed, resulting in gate structures 222, a first dummy gate structure 224, and a second dummy gate structure 226 respectively filled within the gate trenches 122a, 124a, and 126a. The high-dielectric-constant dielectric layer may include silicon nitride (SiN), silicon oxynitride (SiON), or a metal oxide. The metal gate material may include a multilayer structure, for example, it may include at least one work function metal layer and a low-resistivity metal layer, wherein the work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or combinations of the above materials, but is not limited thereto. The low-resistivity metal layer may include aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), or titanium and titanium nitride (Ti / TiN), or combinations of the above materials, but is not limited thereto. In some embodiments, the low-resistivity metal layers of the gate structure 222, the first dummy gate structure 224, and the second dummy gate structure 226 may comprise the same material, such as aluminum (Al). Subsequently, another dielectric layer (not shown) may be formed over the substrate 100 to cover the interlayer dielectric layer 142 and the gate structure 222, the first dummy gate structure 224, and the second dummy gate structure 226. Then, a contact plug 160 (see reference) is formed that penetrates the dielectric layer and directly contacts and electrically connects to the gate structure 222. Figure 2 The contact plug 160 may include conductive materials such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., but is not limited thereto. No contact plugs are disposed on the first dummy gate structure 224 and the second dummy gate structure 226.

[0081] It is worth noting that in some embodiments, such as Figure 7 As shown, the portion of the etch stop layer 140 covering the arcuate sidewall at the top of the sacrificial gate structure 122 becomes a beak-shaped portion 140a extending horizontally toward the opening of the gate trench 122a after the sacrificial gate structure 122 is removed. The beak-shaped portion 140a reduces the opening width of the gate trench 122a, thus increasing the difficulty of filling the gate trench 122a with metal gate material. The formation and size of the beak-shaped portion 140a are significantly affected by the step difference SH (reference). Figure 4 Due to the influence of the step difference SH, a larger step difference SH makes it easier to form a noticeable beak-like portion 140a, making it more difficult for the metal gate material to completely fill the gate trench 122a, resulting in a void defect 230 within the gate structure 222. This void defect 230 causes abnormal resistance in the gate structure 222, and in severe cases, even leads to a break in the gate structure 222. Currently, the mechanism of void defects 230 in the gate structure 222 (the step difference SH causing a beak-like portion 140a resulting in incomplete filling of the metal gate material) is also the chip region R1 of the semiconductor device (refer to...). Figure 1 One of the main causes of void defects 230 in the gate structure of semiconductor devices is the poor control of the manufacturing process. In other words, if the manufacturing process is not well controlled, void defects 230 can occur simultaneously in both the gate structure 222 and the chip region R1 of the semiconductor device. Therefore, this invention can conveniently use the wafer acceptance test (WAT) step to measure the resistance of the gate structure 222, and then determine whether void defects 230 exist in both the gate structure 222 and the gate structure of the chip region R1 based on the resistance data. Compared with existing methods that use optical defect detection (e.g., bright field inspection), this invention has a faster inspection speed and can be used to comprehensively inspect all wafers in mass production.

[0082] Please continue to refer to this. Figure 8The test bond structure according to a first embodiment of the present invention includes a substrate 100, which includes a first region A1 and a second region A2 located between the first regions A1. An isolation structure 104 is disposed in the substrate 100 and extends to cover the first region A1 and the second region A2. A gate dielectric layer TG is disposed on the isolation structure 104, covering the portion of the isolation structure 104 directly above the first region A1 and exposing the portion of the isolation structure 104 directly above the second region A2. An interlayer dielectric layer 142 is disposed on the isolation structure 104 and the gate dielectric layer TG. A first dummy gate structure 224 is embedded in the interlayer dielectric layer 142 directly above the first region A1 of the substrate 100, and its bottom surface 224a is in direct contact with the surface of the gate dielectric layer TG, and its top surface 224b is flush with the surface 142a of the interlayer dielectric layer 142. The gate structure 222 is embedded in the interlayer dielectric layer 142 directly above the second region A2 of the substrate 100. Its bottom surface 222a is in direct contact with the surface of the isolation structure 104 and is lower than the bottom surface 224a of the first dummy gate structure 224. Its top surface 222b is flush with the surface 142a of the interlayer dielectric layer 142 and the top surface 224b of the first dummy gate structure 224. The height H1 of the gate structure 222 is greater than the height H2 of the first dummy gate structure 224. The height H1 of the gate structure 222 can be approximately equal to the height H2 of the first dummy gate structure 224 plus the thickness T1 of the gate dielectric layer TG (H1 = H2 + T1). The top sidewall of the gate structure 222 can have an arcuate profile and is covered by the beak-shaped portion 140a of the etch stop layer 140.

[0083] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0084] Please refer to Figure 9 The diagram shown is a cross-sectional schematic of the test key structure according to the second embodiment of the present invention. Figure 9 The test bond structure and Figure 8 The main difference in the test bond structure is that Figure 9 The isolation structure 104 in the second region A2 will be in the etching process P1 (refer to...) Figure 3 The 104R depression was partially removed from the ) and therefore the step difference SH (reference) Figure 4The height of the gate structure 222 is approximately determined by the thickness T1 of the gate dielectric layer TG and the depth D1 of the recess 104R. The edge of the recess 104R is aligned with the edge of the gate dielectric layer TG along a vertical direction (e.g., the third direction Z). The gate structure 222 is disposed in the recess 104R, so the bottom surface 222a is lower than the bottom surface 224a of the first dummy gate structure 224. The height H1 of the gate structure 222 can be approximately equal to the height H2 of the first dummy gate structure 224 plus the thickness T1 of the gate dielectric layer TG and the depth D1 of the recess 140R (H1 = H2 + T1 + D1).

[0085] Please refer to Figure 10 The diagram shown is a cross-sectional schematic of the test key structure according to a third embodiment of the present invention. Figure 10 The test bond structure and Figure 8 The main difference in the test bond structure is that Figure 10 The test bond structure does not include the gate dielectric layer TG. The first dummy gate structure 224 is directly disposed on the isolation structure 104 of the first region A1, and the isolation structure 104 of the second region A2 will be fabricated in the etching process P1 (see reference). Figure 3 The 104R depression was partially removed from the ) and therefore the step difference SH (reference) Figure 4 The height of the gate structure 222 is roughly determined by the depth D1 of the recess 104R. The height H1 of the gate structure 222 can be approximately equal to the height H2 of the first dummy gate structure 224 plus the depth D1 of the recess 140R (H1 = H2 + D1).

[0086] Please refer to Figure 11 The diagram shown is a planar schematic of the test key structure according to the fourth embodiment of the present invention. Figure 11 The test bond structure and Figure 2 The main difference in the test bond structure is that Figure 11 The first region A1 of the substrate 100 of the test bond structure is a closed ring and completely surrounds the second region A2, which is provided with the gate structure 222. Figure 11 The test bond structure along the tangent I-I' can have the same Figure 8 , Figure 9 or Figure 10 The same cross-sectional structure.

[0087] Please refer to Figure 12 and Figure 13 . Figure 12 The diagram shown is a plan view of the test bond structure of a semiconductor element according to a fifth embodiment of the present invention. Figure 13 for Figure 12 A schematic cross-sectional view of the test bond structure along the tangent I-I'. Figure 12 and Figure 13 The test bond structure and Figure 2 and Figure 8The main difference in the test bond structure is that Figure 12 and Figure 13 The first region A1 of the test key structure also includes an active region 102 surrounded by an isolation structure 104, and a plurality of dummy active regions 103 arranged around the first region A1. A first dummy gate structure 224 is disposed on the active region 102 and extends across the active region 102 along the first direction Y. Figure 13 As shown, the gate dielectric layer TG covers the surface of the active region 102 and extends into the isolation structure 104, covering part of the surface of the isolation structure 104. The height H1 of the gate structure 222 can be approximately equal to the height H2 of the first dummy gate structure 224 plus the thickness T1 of the gate dielectric layer TG (H1 = H2 + T1).

[0088] Please refer to Figure 14 The diagram shown is a cross-sectional schematic of the test key structure according to the sixth embodiment of the present invention. Figure 14 The test bond structure and Figure 13 The main difference in the test bond structure is that Figure 14 The isolation structure 104 in the second region A2 will be in the etching process P1 (refer to...) Figure 3 The recess 104R is formed by partially removing material from the isolation structure 104. The edge of the recess 104R is aligned with the edge of the gate dielectric layer TG on the isolation structure 104 along a vertical direction (e.g., the third direction Z). The height H1 of the gate structure 222 can be approximately equal to the height H2 of the first dummy gate structure 224 plus the thickness T1 of the gate dielectric layer TG and the depth D1 of the recess 140R (H1 = H2 + T1 + D1).

[0089] Please refer to Figure 15 The diagram shown is a cross-sectional schematic of the test key structure according to the seventh embodiment of the present invention. Figure 15 The test bond structure and Figure 13 The main difference in the test bond structure is that Figure 15 The gate dielectric layer TG can be formed using the material of the active region 102, so it will only be formed on the active region 102 and will not cover the isolation structure 104, and the edge of the gate dielectric layer TG can be aligned with the edge of the active region 102 along the vertical direction (e.g., the third direction Z).

[0090] Please refer to Figure 16 The diagram shown is a planar schematic of the test key structure according to the eighth embodiment of the present invention. Figure 16 The test bond structure and Figure 12 The main difference in the test bond structure is that Figure 16 The first region A1 of the substrate 100 of the test bond structure is a closed ring and completely surrounds the second region A2, which is provided with the gate structure 222. Figure 16 The test bond structure along the tangent I-I' can have the same Figure 13 , Figure 14 or Figure 15 The same cross-sectional structure.

[0091] In summary, the test bond structure design of the semiconductor device provided by this invention can reflect the impact of the step difference caused by the recess of the gate dielectric layer and / or isolation structure on the replacement metal gate fabrication process. Furthermore, it allows for convenient WAT (Wastewater Analysis) measurement of resistance data, which can then be used to determine whether the gate structure may have void defects. Compared to existing methods using optical defect detection, this invention offers faster inspection speeds and can be used for rapid inspection of individual wafers.

[0092] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A test bond structure for a semiconductor device, comprising: Base; The gate structure is located on this substrate; as well as A plurality of first dummy gate structures are located on the substrate and around the gate structure, wherein the bottom surface of the gate structure is lower than the bottom surface of the plurality of first dummy gate structures, and the top surface of the gate structure is flush with the top surface of the plurality of first dummy gate structures.

2. The test bond structure of the semiconductor device as claimed in claim 1, further comprising an etch stop layer located on the substrate and covering the sidewalls of the gate structure and the plurality of first dummy gate structures, wherein the etch stop layer includes a beak-shaped portion located on the sidewall of the top of the gate structure.

3. The test bond structure of the semiconductor device as claimed in claim 1, wherein the top of the gate structure includes an arcuate profile.

4. The test bond structure of the semiconductor device as described in claim 1, further comprising: A first gap wall is located on the side wall of the gate structure, wherein the top surface of the first gap wall is lower than the top surface of the gate structure; as well as Multiple second gap walls are located on the sidewalls of the multiple first dummy gate structures, wherein the top surface of the second gap wall is flush with the top surface of the multiple first dummy gate structures.

5. The test bond structure of the semiconductor element as claimed in claim 1, further comprising an isolation structure located on the substrate.

6. The test bond structure of the semiconductor element as claimed in claim 5, wherein the gate structure is disposed on the recess of the isolation structure, the plurality of first dummy gate structures are disposed on the isolation structure outside the recess, and the height of the gate structure is equal to the height of the plurality of first dummy gate structures plus the depth of the recess.

7. The test bond structure of the semiconductor device as claimed in claim 5, further comprising a gate dielectric layer located between the plurality of first dummy gate structures and the isolation structure, wherein the height of the gate structure is equal to the thickness of the gate structure plus the height of the plurality of first dummy gate structures.

8. The test bond structure of the semiconductor device as described in claim 1, further comprising: An isolation structure is located on the substrate, and the gate structure is directly disposed on the isolation structure; Multiple active regions are located on the substrate and around the gate structure, wherein the multiple first dummy gate structures are disposed on the multiple active regions; as well as A gate dielectric layer is located between the plurality of active regions and the plurality of first dummy gate structures.

9. The test bond structure of the semiconductor device as claimed in claim 8, wherein the gate structure is disposed on the recessed region of the isolation structure, and the height of the gate structure is equal to the thickness of the gate dielectric layer plus the height of the plurality of first dummy gate structures and the depth of the recessed region.

10. The test bond structure of the semiconductor element as claimed in claim 9, wherein the edge of the gate dielectric layer is aligned with the edge of the recessed region.

11. The test bond structure of the semiconductor element as claimed in claim 9, wherein the edge of the gate dielectric layer is aligned with the edge of the plurality of active regions.

12. The test bond structure of the semiconductor element as claimed in claim 1, further comprising two second dummy gate structures, respectively disposed on both sides of the gate structure and located between the gate structure and the plurality of first dummy gate structures.

13. The test bond structure of the semiconductor element as claimed in claim 1, wherein the gate structure and the plurality of first dummy gate structures comprise a metal gate material.

14. The test key structure of the semiconductor element as claimed in claim 1, further comprising a plurality of contact plugs disposed on the gate structure and electrically connected to the gate structure.

15. The test bond structure of the semiconductor element as claimed in claim 1, wherein the plurality of first dummy gate structures are electrically insulated from the outside.

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