Inverter based on quasi-enhancement gallium nitride device and method of manufacturing the same

Abstract

The application provides a kind of inverter based on quasi-enhancement gallium nitride device and its manufacturing method, inverter includes depletion load transistor and one quasi-enhancement load transistor, quasi-enhancement load transistor is formed by the series connection of several diodes between the source and gate of one depletion load transistor, diode is the Schottky barrier diode prepared together with transistor, the drain of quasi-enhancement load transistor is connected with the source and gate of depletion load transistor, the application changes the device structure, prepares the quasi-enhancement GaN HEMT device with positive threshold voltage, does not need to etch semiconductor layer, reduces the demand for etching equipment, simplifies the preparation process flow, at the same time avoids the damage caused by etching, improves the performance of device;Quasi-enhancement device and depletion device are integrated on one epitaxial wafer at the same time, and the two devices are connected by metal to form a monolithic integrated inverter circuit.

Description

Technical Field

[0001] This invention relates to an inverter based on a quasi-enhancement-mode gallium nitride device and a method for manufacturing the same. Background Technology

[0002] Gallium nitride (GaN) material has a large bandgap, high electron saturation velocity, and high breakdown voltage. Therefore, high electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunction structures offer advantages such as high saturation current and low on-state resistance. Consequently, GaN HEMTs can operate under extreme conditions such as high voltage, high frequency, and high temperature, and are widely used in important fields such as the automotive industry, aerospace, and military equipment.

[0003] GaN HEMT devices form a two-dimensional electron gas under the combined effects of spontaneous polarization and piezoelectric polarization, thus constituting the conductive channel between the drain and source. Due to the presence of the AlGaN / GaN heterojunction, the two-dimensional electron gas can only be depleted and the device turned off when a negative voltage is applied to the gate; therefore, it is called a depletion-mode (D-mode) device. Inverter circuits typically consist of a D-mode device and an enhancement-mode (E-mode) device connected in series, thus requiring the fabrication of an E-mode GaNHEMT, which only conducts when a positive voltage is applied to the gate. Currently, there are four main methods for realizing E-mode GaN HEMTs: gate recess technology, p-GaN cap technology, fluorine ion implantation technology, and cascade structure technology. The first two methods have high requirements for etching technology and equipment, and are prone to causing surface damage to the device, leading to performance degradation. Fluorine ion implantation technology reduces the thermal stability of the device, while cascade technology increases the device resistance and reduces the operating frequency.

[0004] Gate trench type:

[0005] E-mode devices are achieved by etching the AlGaN barrier layer under the gate using techniques such as ICP, which depletes the conductive channel. However, the damage caused by gate trench etching and the interface states can affect device performance, leading to problems such as increased gate leakage current, reduced channel electron mobility, and increased on-resistance.

[0006] p-GaN layer full etching scheme:

[0007] This method involves depleting the two-dimensional electron gas through a p-GaN layer and then etching away the p-GaN layer below the gate using techniques such as ICP. However, this method still requires etching, which inevitably leads to etching damage, resulting in poor device interface characteristics and a susceptibility to current collapse.

[0008] Fluoride ion implantation technology:

[0009] This technology enables enhancement-mode devices by implanting fluorine ions, and the concentration and depth distribution of the implanted fluorine ions are controllable. However, this technology can affect the thermal stability of the device, leading to a deterioration in its high-temperature characteristics.

[0010] Cascade structure technology:

[0011] This technology cascades enhancement-mode silicon (Si)-based field-effect transistors (MOSFETs) with depletion-mode GaN devices to form a Cascade structure. Therefore, the total on-resistance is the sum of the two. Due to the higher on-state resistance of the Si-based device, the total on-resistance of the device is also higher. Furthermore, the switching speed of the device also depends on the Si-based device, resulting in a lower operating frequency for this technology. Summary of the Invention

[0012] The purpose of this invention is to overcome the shortcomings of the prior art and provide an inverter based on quasi-enhanced gallium nitride devices and its manufacturing method, which does not require etching processes, achieves high reliability with a simple process, and reduces the damage and interface state problems caused by etching.

[0013] To achieve the above objectives, the present invention provides the following technical solution:

[0014] An inverter based on a quasi-enhancement-mode gallium nitride device includes:

[0015] Depletion-type first load transistor;

[0016] The second load transistor is a depletion-type transistor, the drain of which is connected to the source and gate of the first load transistor; and

[0017] Several diodes are connected in series between the source and gate electrodes of the depletion-type second load transistor;

[0018] Among them, the first load transistor and the second load transistor of depletion type are both normally open gallium nitride high electron mobility transistors;

[0019] The depletion-type second load transistor and several diodes constitute a normally closed quasi-enhancement-type gallium nitride high electron mobility transistor.

[0020] An inverter based on a quasi-enhancement-mode gallium nitride (GaN) device includes a base layer and a passivation layer sequentially disposed thereon. The base layer sequentially includes a silicon substrate, a GaN epitaxial layer, and an aluminum gallium nitride (AlGaN) barrier layer. The base layer is isolated to form a first device region and a second device region. A depletion-mode first load transistor's source, gate, and drain electrodes are formed on the first device region, and a depletion-mode second load transistor's source, gate, and drain electrodes are formed on the second device region. The source, gate, and drain electrodes are formed within the passivation layer, and a metal connection is formed on the passivation layer, electrically connecting the gate and source electrodes of the depletion-mode first load transistor and the drain electrode of the depletion-mode second load transistor. A plurality of Schottky barriers are formed on the second device region, and an insulating portion is formed within the second device region, isolating the sub-regions containing the Schottky barriers from each other. Ohmic contact regions are also formed on the second device region corresponding to the Schottky barriers. The source and drain electrodes of the depletion-mode second load transistor form a current path within the second device region through the ohmic contact regions and the Schottky barriers.

[0021] Furthermore, an aluminum oxide structure is formed between the gate electrode and the aluminum gallium nitride barrier layer.

[0022] Based on this, the present invention also provides a method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device, comprising the following specific steps:

[0023] 1) Provide a silicon substrate, and sequentially form a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer on the silicon substrate to form a base layer;

[0024] 2) An isolation portion is formed in the aluminum gallium nitride barrier layer and the gallium nitride epitaxial layer to isolate the two sides of the isolation portion to form a first device region and a second device region, and a plurality of insulating portions are formed in the aluminum gallium nitride barrier layer and the gallium nitride epitaxial layer corresponding to the second device region.

[0025] 3) Photolithographically etch the source and drain electrode regions of the depletion-type first load transistor on the aluminum gallium nitride barrier layer corresponding to the first device region, and photolithographically etch the source, drain, and ohmic contact regions of the depletion-type second load transistor on the aluminum gallium nitride barrier layer corresponding to the second device region. Then, deposit metal on the source and drain electrode regions of the first device region and the source, drain, and ohmic contact regions of the second device region using an electron beam evaporation process to form the source and drain electrodes of the depletion-type first load transistor, the source and drain electrodes of the depletion-type second load transistor, and the ohmic contact region.

[0026] 4) An aluminum oxide insulating layer is grown on the aluminum gallium nitride barrier layer;

[0027] 5) Photolithographically etch the gate electrode region window of the depletion-type first load transistor in the first device region, and photolithographically etch the gate electrode region window of the depletion-type second load transistor in the second device region, and remove the aluminum oxide insulating layer in the first device region and the second device region except for the gate electrode window.

[0028] 6) Photolithographically etch the gate electrode region window of the depletion-type first load transistor on the aluminum gallium nitride barrier layer corresponding to the first device region, and photolithographically etch the gate electrode and Schottky contact region window of the depletion-type second load transistor on the aluminum gallium nitride barrier layer corresponding to the second device region. Then, use electron beam evaporation to deposit metal on the gate electrode region window of the first device region and the gate electrode and Schottky contact region window of the second device region to form the gate electrode of the depletion-type first load transistor and the gate electrode of the depletion-type second load transistor, and form a Schottky barrier.

[0029] 7) A passivation layer is grown on the aluminum gallium nitride barrier layer;

[0030] 8) Open holes on the passivation layer at the locations of the gate electrode, source electrode, and drain electrode of the first depletion-type load transistor and at the locations of the gate electrode, source electrode, and drain electrode of the second depletion-type load transistor;

[0031] 9) By using electron beam evaporation, metal is deposited on the gate electrode, source electrode of the depletion-type load transistor, and drain electrode of the depletion-type second load transistor to form a metal connection so that the three are electrically connected, thus forming an inverter.

[0032] Further, in step 3, the deposited metal is one of the following combinations: Ti / Al / Ni / Au, Ti / Al / Ni / TiN, or Ti / Al / Ni / W; in step 4, the deposited metal is a combination of Ni / TiN or Ni / Au.

[0033] Furthermore, in step 3, after the electron beam evaporation process, an annealing step in a nitrogen atmosphere is also included.

[0034] Furthermore, the annealing temperature is 200℃~1030℃.

[0035] Furthermore, the annealing temperature is 880℃.

[0036] Furthermore, the opening method in step 6 adopts one of the following processes: RIE, ICP, or BOE.

[0037] Furthermore, the isolation section and the insulation section in step 2 are implemented by implanting positively charged ions using an ion implantation process.

[0038] The beneficial effects of this invention are as follows:

[0039] By modifying the device structure, a quasi-enhancement GaN HEMT device with a positive threshold voltage was fabricated. This eliminates the need for etching the semiconductor layer, reducing the demand for etching equipment, simplifying the circuit fabrication process, and avoiding damage caused by etching, thereby improving device performance. The quasi-enhancement device and the depletion-mode device are simultaneously integrated on a single epitaxial wafer, and these two devices are connected by a metal to form a monolithically integrated inverter circuit. The method of this invention can also be combined with a MIS HEMT structure to reduce gate electrode leakage current.

[0040] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0041] Figure 1 This is an equivalent circuit diagram of an inverter according to an embodiment of the present invention;

[0042] Figure 2 In order to be in Figure 1 The equivalent circuit diagram includes a resistor connected in series to reduce on-state losses.

[0043] Figure 3 This is a schematic diagram of the inverter in an embodiment of the present invention after step 2 of fabrication has been completed;

[0044] Figure 4 This is a schematic diagram of the inverter of an embodiment of the present invention after completing steps 3 to 6 of the fabrication process;

[0045] Figure 5 This is a schematic diagram of the inverter in an embodiment of the present invention after step 7 of the fabrication process has been completed;

[0046] Figure 6 This is a schematic diagram of the inverter in an embodiment of the present invention after completing steps 8-9 of the fabrication process;

[0047] Figure 7 The transfer characteristic curve of a quasi-enhancement load transistor according to an embodiment of the present invention is shown.

[0048] Figure 8 The curve showing the relationship between the input voltage and the output voltage of an inverter constructed using a quasi-enhancement device according to an embodiment of the present invention. Detailed Implementation

[0049] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0052] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0053] The inverter based on a quasi-enhancement gallium nitride device proposed in this embodiment has the structure shown in the attached figure. Figure 1 As shown, the transistor includes a depletion-type first load transistor, a depletion-type second load transistor, and several diodes. The drain electrode 9 of the depletion-type second load transistor is connected to the source electrode 8 and gate electrode 7 of the depletion-type first load transistor. Several diodes are connected in series between the source electrode 11 and the gate electrode 10 of the depletion-type second load transistor. These diodes are Schottky barriers formed between the source electrode 11 and the gate electrode 10 through a process, thereby making the depletion-type second load transistor a quasi-enhancement-type load transistor. In practical applications, the number of diodes can be set according to actual needs. Both the depletion-type first load transistor and the depletion-type second load transistor are normally-on gallium nitride high electron mobility transistors. Due to the addition of the Schottky barrier, the threshold voltage of the depletion-type second load transistor becomes positive, forming a normally-closed gallium nitride high electron mobility transistor. Preferably, a resistor is connected between the source electrode 8 of the depletion-type first load transistor and the drain electrode 9 of the quasi-enhancement-type load transistor, as shown in the attached figure. Figure 2This can reduce the on-state losses of the inverter.

[0054] Specifically, the inverter includes a base layer and a passivation layer 14 disposed sequentially. The base layer sequentially includes a silicon substrate 1, a gallium nitride epitaxial layer 2, and an aluminum gallium nitride barrier layer 3. The base layer is also called an epitaxial layer. The base layer is isolated to form a first device region and a second device region. The first device region forms the source electrode 8, gate electrode 7, and drain electrode 6 of a depletion-type first load transistor. The second device region forms the source electrode 11, gate electrode 10, and drain electrode 9 of a depletion-type second load transistor. The source electrodes 8, 11, gate electrodes 7, 10, and drain electrodes 6, 9 of both the depletion-type first load transistor and the depletion-type second load transistor are formed within the passivation layer 14. A metal layer is formed on the passivation layer 14. The metal connection portion 15 electrically connects the gate electrode 7 and source electrode 8 of the depletion-type first load transistor and the drain electrode 9 of the depletion-type second load transistor. An aluminum oxide structure is formed between the gate electrode 7 of the depletion-type first load transistor and the aluminum gallium nitride barrier layer 3. A plurality of Schottky barriers are formed on the second device region, and an insulating portion 5 is formed within the second device region. The insulating portion 5 isolates the sub-regions containing the plurality of Schottky barriers from each other. Ohmic contact regions 13 are also formed on the second device region corresponding to the plurality of Schottky barriers 12. The source electrode 11 and drain electrode 9 of the depletion-type second load transistor form a current path within the second device region through the ohmic contact region 13 and the Schottky barrier 12.

[0055] See attached document Figure 3 To be continued Figure 6 The specific process for manufacturing the inverter in this embodiment is as follows:

[0056] 1) Provide a silicon substrate 1, and sequentially form a gallium nitride epitaxial layer 2 and an aluminum gallium nitride barrier layer 3 on the silicon substrate 1 to form a base layer.

[0057] The base structure can be prepared using metal-organic chemical vapor deposition (MOCVD) equipment, which is currently in use.

[0058] 2) An isolation portion 4 is formed in the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 to isolate the two sides of the isolation portion 4 to form a first device region and a second device region, and a plurality of insulating portions 5 are formed in the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 corresponding to the second device region.

[0059] The isolation section 4 and the insulation section 5 can be formed by implanting positively charged ions, such as oxygen ions, through an ion implantation process.

[0060] 3) On the aluminum gallium nitride barrier layer 3 corresponding to the first device region, photolithographically etch the source electrode 8 and drain electrode 6 region windows of the depletion-type first load transistor. On the aluminum gallium nitride barrier layer 3 corresponding to the second device region, photolithographically etch the source electrode 8, drain electrode 11, and ohmic contact region windows of the depletion-type second load transistor. Electron beam evaporation is then used to deposit metal on the source electrode 8 and drain electrode 6 region windows of the first device region and the source electrode 11, drain electrode 9, and ohmic contact region windows of the second device region. The deposited metal can be one of the following combinations: Ti / Al / Ni / Au, Ti / Al / Ni / TiN, or Ti / Al / Ni / W, with Ti / Al / Ni / TiN being the optimal combination. After deposition, a lift-off process is performed to remove excess metal, leaving an ohmic metal layer. Annealing is then performed in a nitrogen atmosphere, or other inert atmospheres. The annealing temperature is 200℃~1030℃, with 880℃ being optimal. After annealing, ohmic contact electrodes with smooth surface morphology are formed, namely, the source electrode 8 and drain electrode 6 of the depletion-type first load transistor and the source electrode 11 and drain electrode 9 of the depletion-type second load transistor, and an ohmic contact region 13 located in the second device region is also formed.

[0061] Several insulating portions 5 divide the second device region into multiple sub-regions, with each ohmic contact 13 corresponding to one sub-region. The source electrode 11 of the depletion-type second load transistor is located in the sub-region at the edge. After annealing, Ti and Al ions from the drain electrode 9, source electrode 11 region, and ohmic contact region 13 of the depletion-type second load transistor diffuse into the underlying aluminum gallium nitride barrier layer 3. The ohmic contact region 13 forms a current path between the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 in this sub-region. Therefore, the conductive channel is connected to the ohmic contact region 13 corresponding to this sub-region.

[0062] 4) An aluminum oxide structure (not shown in the attached figure) is grown on the aluminum gallium nitride barrier layer 3 using atomic layer deposition (ALD) equipment as an insulating layer. Other insulating materials can also be deposited as insulating layers.

[0063] 5) Photolithographically etch the gate electrode 7 region window of the first depletion-type first load transistor in the first device region, and photolithographically etch the gate electrode 10 region window of the second depletion-type second load transistor (i.e., the quasi-enhancement-type load transistor described in step 3) in the second device region, and remove the aluminum oxide insulating layer in the regions of the first device region other than the gate electrode window and the regions of the second device region other than the gate electrode window using BOE solution.

[0064] 6) On the aluminum gallium nitride (ANU) barrier layer 3 corresponding to the second device region, photolithographically etch the region windows of the Schottky contact area and the gate region of the depletion-type second load transistor (i.e., the quasi-enhancement-type load transistor) and the gate window of the first load transistor. Electron beam evaporation is then used to deposit metal on the region windows of the gate electrode 7 in the first device region and the gate electrode 10 and Schottky contact area in the second device region. The deposited metal is a combination of Ni / TiN or Ni / Au, with Ni / TiN being the optimal combination. After deposition, the metal is stripped to form the gate electrode 7 of the depletion-type first load transistor, the gate electrode 10 of the depletion-type second load transistor (quasi-enhancement-type load transistor), and the Schottky barrier 12. Schottky contacts are formed between the gate electrode 7 of the depletion-type first load transistor, the gate electrode 10 of the depletion-type second load transistor, and the ANU barrier layer 3. At this point, the aforementioned depletion-type second load transistor becomes a complete quasi-enhancement-type load transistor.

[0065] Due to the formation of the Schottky barrier 12, the threshold voltage of the depletion-type second load transistor becomes positive, thus forming a quasi-enhancement-type load transistor. The diode in the inverter equivalent circuit diagram has no physical structure; its body is the Schottky barrier 12. In reality, the diode is formed between the source electrode 11 and the gate electrode 10 of the enhancement-type load transistor.

[0066] The gate electrode 10 of the quasi-enhancement type load transistor, together with the aluminum gallium nitride barrier layer 3 and the insulating layer between them, forms a MIS structure. The gate electrode 7 of the depletion type first load transistor, together with the aluminum gallium nitride barrier layer 3 and the insulating layer between them, also forms a MIS structure. The MIS structure alleviates the leakage of the gate electrodes 10 / 7.

[0067] The Schottky barrier 12 and the ohmic contact region 13 are used to make the two sub-regions conductive, thereby forming a current path in each sub-region. (Appendix) Figure 4 The dashed line segment and the direction of the arrow indicate the direction of conduction. The current path between the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 corresponding to the horizontal dashed line segment is also called the conductive channel. The conductive channel has no physical structure.

[0068] 7) A passivation layer 14 is grown on the aluminum gallium nitride barrier layer 3.

[0069] This step can be achieved by growing silicon nitride or other dielectric materials using PECVD or LPCVD. The passivation layer 14 structure corresponding to the gate electrode 7 and source electrode 8 of the depletion-type first load transistor, and the passivation layer 14 structure corresponding to the source electrode 8 of the depletion-type first load transistor and the drain electrode 9 of the quasi-enhancement-type load transistor, serves to prevent circuit interconnection and is also known as a circuit interconnection isolation layer, while improving the interface state.

[0070] 8) Using one of the following processes, RIE, ICP, and BOE, holes are made on the passivation layer 14 at the positions of the gate electrode 7, source electrode 8, and drain electrode 6 of the depletion-type first load transistor and at the positions of the gate electrode 10, source electrode 11, and drain electrode 9 of the quasi-enhancement-type load transistor.

[0071] Although RIE, ICP, and BOE are all etching processes, the etching in step 6 is performed on the passivation layer 14, which acts on the electrode metal surface and has no effect on the semiconductor. It does not etch the conductive channel between the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2. The etching processes used in the prior art all act on the semiconductor layer, causing certain etching damage and resulting in poor device interface characteristics.

[0072] 9) Metal interconnection 15 is formed by depositing metal on the gate electrode 7 and source electrode 8 of the depletion-type first load transistor and the drain electrode 9 of the quasi-enhancement-type load transistor through an electron beam evaporation process to electrically connect the three and form an inverter.

[0073] The inverter in this embodiment operates as follows: The drain electrode 6 of the depletion-type GaN HEMT is connected to the VDD power supply. Its source electrode 8 is connected to the gate electrode 7, and then connected to the drain electrode 9 of the quasi-enhancement-type GaN HEMT. The source electrode 11 of the quasi-enhancement-type GaN HEMT is grounded. When no voltage is applied to the gate electrode 10 of the quasi-enhancement-type GaN HEMT, the lower transistor is off. Since the upper transistor is a depletion-type device, it is on at this time, and the output voltage is high. When a positive voltage is applied to the gate electrode 10 of the quasi-enhancement-type GaN HEMT, the lower transistor is on, and the output voltage of the circuit is low. Therefore, the circuit can achieve the function of inversion.

[0074] The proposed quasi-enhancement GaN HEMT and its inverter circuit were verified using the Advanced Design System simulation software. Figure 1 This is the equivalent circuit diagram of a quasi-enhancement GaN HEMT. This structure introduces multiple Schottky barriers 12 (i.e., diodes) into the conductive channel. The quasi-enhancement GaN HEMT will only conduct when the voltage applied to the gate electrode 10 reaches the PN junction turn-on voltage. Therefore, the threshold voltage of the quasi-enhancement GaN HEMT is positive, meaning the device is a quasi-enhancement device. Figure 7 The transmission characteristic curve of the quasi-enhancement GaN HEMT is shown, and the threshold voltage of the quasi-enhancement GaN HEMT is positive. Figure 8 The curve showing the relationship between the input and output voltages of an inverter constructed from quasi-enhancement type devices indicates that when the input voltage is low, the output voltage is high, and when the input voltage is high, the output voltage is low, satisfying the logic relationship of the inverter circuit.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An inverter based on a quasi-enhancement-mode gallium nitride device, characterized by, The device comprises a base layer and a passivation layer arranged sequentially. The base layer includes a silicon substrate, a gallium nitride epitaxial layer, and an aluminum gallium nitride barrier layer. The base layer is isolated to form a first device region and a second device region. The first device region forms the source, gate, and drain electrodes of a depletion-type first load transistor, and the second device region forms the source, gate, and drain electrodes of a depletion-type second load transistor. The source, gate, and drain electrodes are formed within the passivation layer. A metal connection is formed on the passivation layer, and the metal connection electrically connects the gate and source electrodes of the depletion-type first load transistor and the drain electrode of the depletion-type second load transistor. A plurality of Schottky barriers are formed on the second device region, and an insulating portion is formed within the second device region. The insulating portion isolates the sub-regions containing the plurality of Schottky barriers from each other. Ohmic contact regions are also formed on the second device region corresponding to the plurality of Schottky barriers. The source and drain electrodes of the depletion-type second load transistor form a current path within the second device region through the ohmic contact regions and the Schottky barriers.

2. The inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 1, characterized in that, An aluminum oxide structure is formed between the gate electrode and the aluminum gallium nitride barrier layer.

3. A method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device, characterized in that, The specific steps include the following: 1) A silicon substrate is provided, on which a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer are sequentially formed to form a base layer; 2) An isolation portion is formed in the aluminum gallium nitride barrier layer and the gallium nitride epitaxial layer to isolate the two sides of the isolation portion to form a first device region and a second device region, and a plurality of insulating portions are formed in the aluminum gallium nitride barrier layer and the gallium nitride epitaxial layer corresponding to the second device region. 3) Photolithographically etch the source and drain electrode regions of the depletion-type first load transistor on the aluminum gallium nitride barrier layer corresponding to the first device region, and photolithographically etch the source, drain, and ohmic contact region windows of the depletion-type load transistor on the aluminum gallium nitride barrier layer corresponding to the second device region. Then, deposit metal on the source and drain electrode regions of the first device region and the source, drain, and ohmic contact region windows of the second device region using an electron beam evaporation process to form the source and drain electrodes of the depletion-type first load transistor, the source and drain electrodes of the depletion-type second load transistor, and the ohmic contact region. 4) An aluminum oxide insulating layer is grown on the aluminum gallium nitride barrier layer; 5) Photolithographically etch the gate electrode region window of the depletion-type first load transistor in the first device region, and photolithographically etch the gate electrode region window of the depletion-type second load transistor in the second device region, and remove the aluminum oxide insulating layer in the first device region and the second device region except for the gate electrode window. 6) Photolithographically etch the gate electrode region window of the depletion-type first load transistor in the first device region, and photolithographically etch the gate electrode region window and Schottky region window of the depletion-type second load transistor in the second device region. Then, deposit metal on the gate electrode region window of the first device region and the gate electrode and Schottky contact region window of the second device region using an electron beam evaporation process to form the gate electrode of the depletion-type first load transistor and the gate electrode of the depletion-type second load transistor, and form a Schottky barrier. 7) A passivation layer is grown on the aluminum gallium nitride barrier layer; 8) Openings are made on the passivation layer at the positions of the gate electrode, source electrode, and drain electrode of the first depletion-type load transistor and at the positions of the gate electrode, source electrode, and drain electrode of the second depletion-type load transistor; 9) Metal is deposited on the gate electrode, source electrode, and drain electrode of the depletion-type first load transistor by electron beam evaporation to form a metal connection so that the three are electrically connected, thereby constituting the inverter.

4. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 3, characterized in that, In step 3, the deposited metal is one of the following combinations: Ti / Al / Ni / Au, Ti / Al / Ni / TiN, or Ti / Al / Ni / W; in step 4, the deposited metal is a combination of Ni / TiN or Ni / Au.

5. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 3, characterized in that, In step 3, after the electron beam evaporation process, an annealing step in a nitrogen atmosphere is also included.

6. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 5, characterized in that, The annealing temperature is 200℃~1030℃.

7. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 6, characterized in that, The annealing temperature is 880℃.

8. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 3, characterized in that, The opening method in step 6 adopts one of the following processes: RIE, ICP, or BOE.

9. The method for manufacturing an inverter based on a quasi-enhancement-mode gallium nitride device as described in claim 3, characterized in that, The isolation section and insulation section described in step 2 are implemented by implanting positively charged ions using an ion implantation process.

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