A four-terminal tunneling field effect transistor and a method of fabricating the same
By designing a four-terminal tunneling field-effect transistor and utilizing the connection between the doped region and the body lead-out region to suppress leakage current, the problem of increased power consumption of TFETs in CMOS hybrid integrated circuits is solved, achieving low power consumption and reliable circuit operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2023-05-26
- Publication Date
- 2026-07-21
AI Technical Summary
In large-scale integrated circuits, tunneling field-effect transistors (TFETs) suffer from increased leakage current and static power consumption due to their lightly doped substrates and asymmetric source-drain doping characteristics. This can even lead to circuit malfunction. Designing TFET devices to maintain low power consumption and ensure normal operation in CMOS hybrid integrated circuits has become an urgent problem to be solved.
A four-terminal tunneling field-effect transistor is designed by introducing two types of doped regions in the substrate region and connecting them to a constant voltage through the body lead-out region to form a zero-biased or reverse-biased PN junction, suppressing leakage current while maintaining a lightly doped channel region to reduce off-state current.
It effectively suppresses leakage current between TFET devices and between TFET and CMOS, improves circuit reliability and reduces power consumption, and ensures that the circuit works normally under low power consumption.
Smart Images
Figure CN116565000B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a tunneling field-effect transistor device and its fabrication method that can be applied to all circuit scenarios. Background Technology
[0002] With the continuous advancement of semiconductor technology, device sizes are shrinking, circuit performance is improving, and chip power density is increasing dramatically. Low power consumption has become an important design direction. At the device level, reducing the power supply voltage can effectively reduce circuit power consumption. However, to maintain sufficient drive capability, the threshold voltage of MOSFET devices must also decrease, leading to an increase in off-state current and static power consumption. Tunneling field-effect transistors (TFETs) employ a band-to-band tunneling current mechanism, effectively cutting off carriers at the tail of the high-energy band. This results in an ultra-steep subthreshold slope of less than 60mV / dec, providing a high current on / off ratio and enabling low-voltage operation. TFETs are considered a promising ultra-steep device to replace MOSFETs.
[0003] Based on Sentaurus TCAD and HSPICE simulations, tunneling field-effect transistors (TFTSs) have been shown to have significantly better power-delay product (PDP) than MOSFETs under certain low-voltage, low-frequency operating conditions, indicating promising applications. However, in large-scale integrated circuit applications, the lightly doped substrate and asymmetric source-drain doping characteristics of TFTSs lead to higher leakage currents between individual TFTSs and between TFTSs and the CMOS device substrate compared to the TFTS's own off-state current. This results in increased static power consumption and may even cause circuit malfunction.
[0004] Furthermore, existing TFET devices are all three-terminal devices with no electrodes leading out from the substrate, and are in a floating state. In large-scale integrated circuits, if a forward-biased PN junction is formed between the floating substrate and the source and drain of the zero-biased TFET device, it will introduce additional leakage current, increasing the static power consumption of the circuit and potentially causing the circuit to malfunction.
[0005] Therefore, how to design TFET devices so that they can still maintain their low power consumption advantage and operate normally in large-scale hybrid integrated circuit applications with CMOS has become an urgent problem to be solved. Summary of the Invention
[0006] The purpose of this invention is to propose a four-terminal tunneling field-effect transistor and its fabrication method, so that it can still maintain the advantage of low power consumption and operate normally in large-scale hybrid integrated circuit applications with CMOS.
[0007] The technical solution provided by this invention is as follows:
[0008] A four-terminal tunneling field-effect transistor (TEFET) includes an active region (AA) and a body lead-out region (BC) defined by shallow trench isolation (STI). The active region is internally composed of three parts: the TFET source / drain region (SD), the TFET channel region (Channel), and the TFET substrate region (SUB) along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate, the doping type of which is determined by the doping type of the first type of doped region in the substrate region. The channel region is located in the middle and at the bottom of the source / drain region, enclosing the source / drain region and thus separating the substrate region from the source / drain region. The TFET substrate region (SUB) consists of two parts: a first type of doped region (SUB-I) and a second type of doped region (SUB-II) along the direction perpendicular to the channel. The first type of doped region can be N-type or P-type doped, and the doping type of the second type of doped region is the opposite of the first type of doped region. The peak value of the second type of doped region (SUB-I) is located below the bottom of the shallow trench isolation (STI). The body lead-out region (BC) consists of two parts: the TFET substrate electrode region (BE) and the substrate doped region (BWELL) along the direction perpendicular to the channel. The doping type of the substrate doped region is the same as that of the second type of doped region of the substrate region. The two are spatially connected at the bottom of the shallow trench isolation, thereby ensuring that the TFET substrate region (SUB) can be led out by the TFET substrate electrode region (BE) of the body lead-out region (BC).
[0009] The technical advantage of the proposed device structure is that if the first type of doped region (SUB-I) is P-type doped, it is led out by the heavily P-type doped source / drain region of the TFET, while the second type of doped region (SUB-II) is led out to the power supply voltage VDD by the body lead-out region (BC). If the first type of doped region (SUB-I) is N-type doped, it is led out by the heavily N-type doped source / drain region of the TFET, while the second type of doped region (SUB-II) is led out to the power supply voltage GND by the body lead-out region (BC). Therefore, regardless of whether the TFET device is designed in a forward-biased or reverse-biased PIN region in the circuit application, a zero-biased or reverse-biased PN junction will be formed between the first type of doped region (SUB-I) and the second type of doped region (SUB-II), which can suppress leakage current between TFET devices and between the TFET and the CMOS. Furthermore, since the substrate of a quad-terminal TFET device is always connected to a constant voltage, compared to a traditional three-terminal TFET device, leakage current between the substrate and the source / drain regions of a zero-bias TFET device is avoided in large-scale integrated circuits, improving circuit reliability and reducing power consumption. In addition, the lightly doped channel region above the TFET substrate ensures the advantage of low off-state current in the TFET device.
[0010] The aforementioned four-terminal tunneling field-effect transistor (TF-FET) devices can all be fabricated using the following process. This process enables the hybrid integration of four-terminal TF-FETs and CMOS devices, characterized by...
[0011] Step 1: Select wafers corresponding to high-resistivity silicon for device and circuit fabrication;
[0012] Step 2: Perform shallow trench isolation (STI). The specific method is to anisotropically etch silicon outside the active region and then anisotropically deposit an oxide layer outside the active region.
[0013] Step 3: Deposit an oxide layer on the substrate in an anisotropic manner;
[0014] Step 4: Define the P-well implantation region of CMOS and the body lead-out implantation region that requires P-type doping in TFET device using photolithography. The boundaries of the implantation regions are all located in the center of STI.
[0015] Step 5: Form the P-well of CMOS and the body lead-out region that requires P-type doping in TFET devices by ion implantation, and remove the adhesive after ion implantation.
[0016] Step 6: Define the N-well injection region of CMOS and the body lead-out injection region that requires N-type doping in TFET device using photolithography. The boundary of the injection region is located in the center of STI.
[0017] Step 7: Form the N-well of CMOS and the body lead-out region that requires N-type doping in TFET devices by ion implantation, and remove the adhesive after ion implantation;
[0018] Step 8: After removing the oxide layer formed in step 3, repeat step 3;
[0019] Step 9: Define the implantation region of the N-type TFET substrate using photolithography. The width of the implantation region of the N-type TFET substrate is greater than the width of the active region, and the boundary of the implantation region is located in the center of the STI.
[0020] Step 10: P-type impurities and N-type impurities are implanted by ion implantation to form the first type of doped region (SUB-I) and the second type of doped region (SUB-II) of the N-type TFET substrate region. The ion implantation energy corresponding to the first type of doped region (SUB-I) is lower, and the ion implantation energy corresponding to the second type of doped region (SUB-II) is higher. After ion implantation, the resist is removed.
[0021] Step 11: Define the implantation region of the P-type TFET substrate using photolithography. The width of the implantation region of the P-type TFET substrate is greater than the width of the active region, and the boundary of the implantation region is located in the center of the STI.
[0022] Step 12: P-type impurities and N-type impurities are implanted by ion implantation to form the first type of doped region (SUB-I) and the second type of doped region (SUB-II) of the P-type TFET substrate region. The ion implantation energy corresponding to the first type of doped region (SUB-I) is lower, and the ion implantation energy corresponding to the second type of doped region (SUB-II) is higher. After ion implantation, the resist is removed.
[0023] Step 13: The oxide layer is etched anisotropically across the entire wafer, followed by subsequent steps such as gate stacking and heavy doping region implantation to complete device fabrication.
[0024] In step 1, the wafer doping type can be boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm.
[0025] In step 2, the thickness of the STI should be between 200nm and 1000nm;
[0026] The thickness of the oxide layer deposited in step 3 and the thickness of the oxide layer etched in step 8 are between 1 nm and 2 nm.
[0027] Steps 5 and 7 are the well implantation conditions in mature CMOS processes. These two steps form the substrate region of the CMOS device and the substrate doped region (BWELL) of the body lead-out region (BC) of the four-terminal TFET device at the same time.
[0028] In steps 10 and 12, the ion implantation energy for the first type of doped region (SUB-I) in the TFET substrate is relatively low, and the peak position of the impurity distribution is inside the STI, thus forming a doped region only between the STIs. For the second type of doped region (SUB-II) in the TFET substrate, the corresponding ion implantation energy is higher, and the peak position of the impurity distribution is below the bottom of the STI. Since the STI has the effect of suppressing the ion implantation channel effect, it can increase the peak concentration, reduce the band tail concentration, and reduce the peak position depth, thereby resulting in a higher doping concentration below the bottom of the STI. At the same depth, in the region far from the STI, the doping concentration decreases, and the boundary line between the upper and lower doped regions of the TFET substrate shifts towards the depth of the substrate.
[0029] In steps 10 and 12, the N-type impurity can be phosphorus (P) or arsenic (As), and the P-type impurity can be boron (B) or boron fluoride (BF2). The ion implantation conditions need to be adjusted so that only the second type of doped region (SUB-II) of the TFET substrate region (SUB) exists at the bottom of the STI, while ensuring that the boundary between the first type of doped region (SUB-I) and the second type of doped region (SUB-II) of the TFET substrate region is located at or above the bottom of the STI. The peak impurity distribution position corresponding to the first type of doped region (SUB-I) of the TFET substrate region is located between 200 nm and the bottom of the STI, thus ensuring the simultaneous formation of a lightly doped TFET channel region above the first type of doped region (SUB-I). The ion implantation conditions also need to ensure that the peak concentrations corresponding to the first type of doped region (SUB-I) and the second type of doped region (SUB-II) of the TFET substrate region (SUB) are both greater than 5E16 cm⁻¹. -2 The surface concentration in the channel is less than 1E16cm. -2 Furthermore, the STI (Surface Injection Mask) is used to define the active region (AA) and the bulk extraction region (BC), and also serves as a hard mask for ion implantation. Because the STI suppresses the ion implantation channel effect, it can increase the peak concentration, decrease the band tail concentration, and reduce the peak position depth. This results in a higher doping concentration region (SUB-II) below the bottom of the STI. At the same depth, in regions further away from the STI, the doping concentration of the SIB-II region decreases, and the boundary between the SIB-I and SIB-II regions shifts deeper into the substrate.
[0030] Step 13 describes the fabrication methods for TFET and CMOS devices, including an annealing step for source / drain activation. The substrate electrode region (BE) of the body lead-out region (BC) of the four-terminal TFET device can be simultaneously formed by implanting the heavily doped region during the device fabrication process. The first type of doped region (SUB-I) and the second type of doped region (SUB-II) are activated by annealing during the device fabrication process. At the same time, the substrate electrode region of the body lead-out region of the four-terminal TFET device is simultaneously formed by implanting the heavily doped region during the device fabrication process.
[0031] This invention relates to large-scale integrated circuits, where TFET devices with the same substrate region can share the lead-out region (BC), saving layout area.
[0032] The four-terminal tunneling field-effect transistor structure proposed in this invention can ensure the low power consumption and normal operation of TFET circuits and TFET-CMOS hybrid circuits in all circuit application scenarios, thereby improving circuit reliability. Furthermore, the source terminal of the four-terminal TFET device can employ either a single-doped tunneling junction design or a hybrid junction design with two doping types.
[0033] The process method for the four-terminal tunneling field-effect transistor proposed in this invention adopts the mature process steps already available in bulk silicon CMOS, and does not introduce new materials, making the process simple and enabling the tunneling field-effect transistor to have the potential for large-scale application and mass production. Attached Figure Description
[0034] Figure 1 This is a cross-sectional schematic diagram of the four-terminal TFET device of the present invention, wherein: (a) the first type of doped region (SUB-I) of the substrate region (SUB) of the four-terminal TFET device is an N-type doped region, and the second type of doped region (SUB-II) is a P-type doped region; (b) the first type of doped region (SUB-I) of the substrate region (SUB) of the four-terminal TFET device is a P-type doped region, and the second type of doped region (SUB-II) is an N-type doped region;
[0035] Figure 2 It is a four-terminal TFET device that can apply a hybrid source junction. Its N-type device substrate region has a P-type doped region on the upper layer and an N-type doped region on the lower layer, and its P-type device substrate region has an N-type doped region on the upper layer and a P-type doped region on the lower layer.
[0036] Figure 3 This diagram illustrates the process steps for the hybrid integration of a quad-terminal TFET device with CMOS, where: (a) is the diagram after the shallow trench isolation process; (b) is the diagram after the oxide layer deposition process; (c) is the diagram after photolithography defining the P-well implantation region of the nMOSFET; (d) is the diagram after P-well implantation of the nMOSFET; (e) is the diagram after photolithography defining the N-well implantation region of the pMOSFET; (f) is the diagram after N-well implantation of the pMOSFET; (g) is the diagram after photolithography defining the implantation region of the N-type TFET substrate; (h) is the diagram after N-type TFET substrate implantation; (i) is the diagram after photolithography defining the implantation region of the P-type TFET substrate; and (j) is the diagram after P-type TFET substrate implantation.
[0037] In the picture:
[0038] 1—Gate conductive layer; 2—Gate dielectric layer
[0039] 3 – P-type heavily doped region; 4 – N-type heavily doped region
[0040] 5 — Shallow trench isolation; 6 — Lightly doped substrate
[0041] 7 – P-type doped region; 8 – N-type doped region
[0042] 9 — N-well of pMOSFET 10 — Deposited oxide layer
[0043] 11—Photoresist; 12—P-well of nMOSFET Detailed Implementation
[0044] The present invention will be further illustrated below with examples. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.
[0045] The first type of doped region (SUB-I) of the substrate region (SUB) of the proposed four-terminal tunneling field-effect transistor can be either N-type doped or P-type doped, depending on the actual circuit application scenario and the design of the doping type of the TFET source and drain terminals.
[0046] To avoid leakage current between the substrate and the source / drain regions of a zero-bias TFET device, the first type of doped region (SUB-I) of the substrate region (SUB) can be designed as N-type doped, and the second type of doped region (SUB-II) of the substrate region (SUB) can be designed as P-type doped. (Refer to...) Figure 1 (a) A four-terminal tunneling field-effect transistor (TEFET) includes an active region (AA) and a body lead-out region (BC) defined by shallow trench isolation (STI). The active region consists of three parts, which are the TFET source / drain region (SD), the TFET channel region (Channel), and the TFET substrate region (SUB) along the direction perpendicular to the channel. The active region (AA) is located between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2. The P-type heavily doped region 3 and the N-type heavily doped region 4 inside the AA region form the TFET source / drain region (SD). The TFET substrate region (SUB) consists of two parts, which are the N-type doped region (NSUB) 8 and the P-type doped region (PSUB) 7 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate located in the middle and at the bottom of the source / drain region, which can wrap around the source / drain region and thus separate the substrate region from the source / drain region. The body lead-out region (BC) consists of two parts, namely the TFET substrate electrode region (BE) 3 and the P-type doped region (PWELL) 12 along the direction perpendicular to the channel. PWELL 12 and PWELL 7 are interconnected, thereby ensuring that the TFET substrate region (SUB) can be led out to GND by the TFET substrate electrode region (BE) of the body lead-out region (BC).
[0047] If you want to apply a quad-terminal TFET device to applications requiring forward-biased PIN current, such as multi-state logic circuits, you can design the first type of doped region (SUB-I) of the substrate region (SUB) to be P-type doped, and the second type of doped region (SUB-II) of the substrate region (SUB) to be N-type doped.
[0048] refer to Figure 1 (b) A four-terminal tunneling field-effect transistor (TEFET) includes an active region (AA) and a body lead-out region (BC) defined by shallow trench isolation (STI). The active region consists of three parts, which are the TFET source / drain region (SD), the TFET channel region (Channel), and the TFET substrate region (SUB) along the direction perpendicular to the channel. The active region (AA) is located between the shallow trench isolation 5 and below the gate conductive layer 1 and the gate dielectric layer 2. The P-type heavily doped region 3 and the N-type heavily doped region 4 inside the AA region form the TFET source / drain region (SD). The TFET substrate region (SUB) consists of two parts, which are the P-type doped region (PSUB) 7 and the N-type doped region (NSUB) 8 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate located in the middle and at the bottom of the source / drain region, which can surround the source / drain region and thus separate the substrate region from the source / drain region. The body lead-out region (BC) consists of two parts, namely the TFET substrate electrode region (BE) 4 and the N-type doped region (NWELL) 9 along the direction perpendicular to the channel. NWELL 9 and NSUB 8 are interconnected, thereby ensuring that the TFET substrate region (SUB) can be led out to VDD by the TFET substrate electrode region (BE) of the body lead-out region (BC).
[0049] For some novel hybrid-mechanism TFET devices, the source terminal has two doping types: one the same as the drain terminal and one opposite to the drain terminal. Therefore, these devices require a channel region with the opposite drain doping type to suppress leakage current from the source to the drain. To address this, a four-terminal tunneling field-effect transistor (TFET) structure for this novel hybrid mechanism is designed as follows (refer to...). Figure 2 The left side shows N-type devices, and the right side shows P-type devices.
[0050] For an N-type TFET device, the active region (AA) and body lead-out region (BC) are defined by shallow trench isolation (STI). The active region consists of three parts, which are the TFET source / drain region (SD), the TFET channel region (Channel), and the TFET substrate region (SUB) along the direction perpendicular to the channel. The active region (AA) is located between the shallow trench isolation layer 5 and below the gate conductive layer 1 and the gate dielectric layer 2. The P-type heavily doped region 3 and the N-type heavily doped region 4 within the AA region form a hybrid source junction. The TFET substrate region (SUB) consists of two parts, which are the P-type doped region (PSUB) 7 and the N-type doped region (NSUB) 8 along the direction perpendicular to the channel. The TFET channel region (Channel) is a lightly doped silicon substrate located in the middle and at the bottom of the source / drain region, which can surround the source / drain region and thus separate the substrate region from the source / drain region. The body lead-out region (BC) consists of two parts, namely the TFET substrate electrode region (BE) 4 and the N-type doped region (NWELL) 9 along the direction perpendicular to the channel. NWELL 9 and NSUB 8 are interconnected, thereby ensuring that the TFET substrate region (SUB) can be led out to VDD by the TFET substrate electrode region (BE) of the body lead-out region (BC).
[0051] For a P-type TFET device, it includes an active region (AA) and a body exit region (BC) defined by shallow trench isolation (STI). The active region consists of three parts, which, along the direction perpendicular to the channel, are the TFET source / drain region (SD), the TFET channel region (Channel), and the TFET substrate region (SUB). The active region (AA) is located between the shallow trench isolation layer 5 and below the gate conductive layer 1 and the gate dielectric layer 2. The N-type heavily doped region 4 and the P-type heavily doped region 3 within the AA region form a hybrid source junction. The TFET substrate region (SUB) consists of two parts, which, along the direction perpendicular to the channel, are the N-type doped region (NSUB) 8 and the P-type doped region (PSUB) 7. The TFET channel region (Channel) is a lightly doped silicon substrate located in the middle and at the bottom of the source / drain region, which can surround the source / drain region and thus separate the substrate region from the source / drain region. The body lead-out region (BC) consists of two parts, namely the TFET substrate electrode region (BE) 3 and the P-type doped region (PWELL) 12 along the direction perpendicular to the channel. PWELL 12 and PWELL 7 are interconnected, thereby ensuring that the TFET substrate region (SUB) can be led out to GND by the TFET substrate electrode region (BE) of the body lead-out region (BC).
[0052] Figure 2 The device structure shown can be used to... Figure 3 The preparation is achieved through the steps shown. The steps are as follows:
[0053] First, a boron-doped P-type high-resistivity silicon wafer was selected for device and circuit fabrication with a resistivity of 9 Ohm-cm.
[0054] Secondly, shallow trench isolation (STI) is performed. Specifically, this involves anisotropically etching silicon outside the active region, followed by anisotropically depositing an oxide layer outside the active region. For example... Figure 3 As shown in (a), 5 is a 300nm STI and 6 is a lightly doped P-type substrate.
[0055] Next, as Figure 3 (b) shows that a 2 nm oxide layer 10 is deposited on the substrate in an anisotropic manner;
[0056] Next, as Figure 3 As shown in (c), the P-type doped bulk lead-out implantation region of the P-type TFET device is defined by photolithography, and the boundary of the implantation region is located at the center of the STI.
[0057] Next, as Figure 3 As shown in (d), the P-type doped bulk lead-out region of the P-type TFET device is formed by ion implantation. A total of three ion implantations are performed under the conditions of 90 keV 1E 13 cm⁻¹. -3 200keV5E13cm -3 10keV1E13cm -3 After ion implantation, the adhesive is removed;
[0058] Next, as Figure 3 As shown in (e), the N-type doped bulk lead-out implantation regions of the N-type TFET device are defined by photolithography, and the boundaries of the implantation regions are all located in the center of the STI.
[0059] Next, as Figure 3 As shown in (f), the N-type doped bulk lead-out region of the N-type TFET device is formed by ion implantation. A total of three ion implantations are performed under the conditions of 30 keV 5E 12cm. -3 220keV5E12cm -3 380keV5E13cm -3 After ion implantation, the adhesive is removed;
[0060] Next, the oxide layer 10 is etched, and then a 2 nm oxide layer 10 is deposited on the substrate in an anisotropic manner; next, as Figure 3 As shown in (g), the substrate implantation region of the N-type TFET is defined by photolithography;
[0061] Next, as Figure 3As shown in (h), boron was implanted to form a P-type doped region 7 by ion implantation at an implantation energy of 60 keV and an implantation dose of 1e13cm. -3 Phosphorus was implanted via ion implantation to form an N-type doped region 8, with an implantation energy of 340 keV and an implantation dose of 1e13 cm⁻¹. -3 After ion implantation, the adhesive is removed;
[0062] Next, as Figure 3 As shown in (i), the substrate implantation region of the P-type TFET is defined by photolithography;
[0063] Next, as Figure 2 As shown in (j), phosphorus was implanted by ion implantation to form an N-type doped region 8, with an implantation energy of 180 keV and an implantation dose of 1e13cm. -3 Boron was implanted via ion implantation to form a P-type doped region 7, with an implantation energy of 140 keV and an implantation dose of 1e13cm. -3 After ion implantation, the adhesive is removed;
[0064] Next, the oxide layer 10 is etched anisotropically across the entire wafer, followed by gate stacking and heavily doped region implantation to complete device fabrication. Then, the impurities in the isolation trap are activated using a thermal budget for subsequent source / drain activation, forming the final device structure as shown below. Figure 2 As shown.
[0065] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. A four-terminal tunneling field-effect transistor (TFET) device, comprising an active region and a body lead-out region defined by shallow trench isolation. The active region is internally composed of three parts, which, along the direction perpendicular to the channel, are a TFET source / drain region, a TFET channel region, and a TFET substrate region. The TFET channel region is a lightly doped silicon substrate, the doping type of which is determined by the doping type of a first type of doped region in the substrate region. The channel region is located in the middle and at the bottom of the source / drain region, enclosing the source / drain region and thus separating the substrate region from the source / drain region. The TFET substrate region consists of two parts, which, along the direction perpendicular to the channel, are respectively a first type of doped region. The two types of doped regions are N-type and P-type. The first type of doped region is either N-type or P-type doped, while the second type of doped region has the opposite doping type. The peak value of the second type of doped region is located below the bottom of the shallow trench isolation. The body lead-out region consists of two parts, namely the TFET substrate electrode region and the substrate doped region along the direction perpendicular to the channel. The doping type of the substrate doped region is the same as that of the second type of doped region in the substrate region. The two are spatially connected at the bottom of the shallow trench isolation. The TFET substrate region is led out by the TFET substrate electrode region of the body lead-out region.
2. The four-terminal tunneling field-effect transistor device as described in claim 1, characterized in that, The bottom of the shallow trench isolation has only the second type of doped region of the TFET substrate region, while at the boundary of the shallow trench isolation, the boundary line between the first type of doped region and the second type of doped region of the TFET substrate region is located at and above the bottom of the shallow trench isolation. In the region between the shallow trench isolations, the boundary line between the first type of doped region and the second type of doped region of the TFET substrate region is located at or above and below the bottom of the shallow trench isolation.
3. The four-terminal tunneling field-effect transistor device as described in claim 1, characterized in that, The peak position of the impurity distribution corresponding to the first type of doped region in the TFET substrate region is located at a distance of more than 200 nm from the channel surface to the bottom of the shallow trench isolation.
4. A method for fabricating a four-terminal tunneling field-effect transistor device, comprising the following steps: 1) Select wafers corresponding to high-resistivity silicon for device and circuit fabrication; 2) Perform shallow trench isolation. The specific method is to anisotropically etch silicon outside the active region and then anisotropically deposit an oxide layer outside the active region. 3) An oxide layer is deposited on the substrate in an anisotropic manner; 4) Define the P-well injection region of CMOS and the body lead-out injection region that requires P-type doping in TFET devices using photolithography. The boundaries of the injection regions are located in the center of the shallow trench isolation. 5) Form the P-well of CMOS and the body lead-out region that requires P-type doping in TFET devices by ion implantation, and then remove the adhesive after ion implantation. 6) Define the N-well injection region of CMOS and the body lead-out injection region that requires N-type doping in TFET devices using photolithography. The boundaries of the injection regions are located in the center of the shallow trench isolation. 7) Form N-wells in CMOS and N-type doped bulk lead-out regions in TFET devices by ion implantation, and then remove the adhesive after ion implantation. 8) After removing the oxide layer formed in step 3), repeat step 3); 9) Define the implantation region of the N-type TFET substrate using photolithography. The width of the implantation region of the N-type TFET substrate is greater than the width of the active region, and the boundary of the implantation region is located in the center of the shallow trench isolation. 10) P-type and N-type impurities are implanted by ion implantation to form the first type of doped region and the second type of doped region of the N-type TFET substrate. The ion implantation energy corresponding to the first type of doped region is low, and the ion implantation energy corresponding to the second type of doped region is high. The resist is removed after ion implantation. 11) Define the implantation region of the P-type TFET substrate using photolithography. The width of the implantation region of the P-type TFET substrate is greater than the width of the active region, and the boundary of the implantation region is located in the center of the shallow trench isolation. 12) P-type and N-type impurities are implanted by ion implantation to form the first type doped region and the second type doped region of the P-type TFET substrate. The ion implantation energy corresponding to the first type doped region is low, and the ion implantation energy corresponding to the second type doped region is high. The resist is removed after ion implantation. 13) The oxide layer is etched anisotropically across the entire wafer, followed by gate stacking and heavy doping region implantation, to complete the device fabrication.
5. The preparation method according to claim 4, characterized in that, The wafer in step 1) is doped with boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm.
6. The preparation method according to claim 4, characterized in that, In step 2), the thickness of the shallow trench isolation ranges from 200nm to 1000nm.
7. The preparation method according to claim 4, characterized in that, The thickness of the oxide layer deposited in step 3) ranges from 1 nm to 2 nm.
8. The preparation method according to claim 4, characterized in that, The N-type doped impurity is phosphorus or arsenic, and the P-type doped impurity is boron or boron fluoride.
9. The preparation method according to claim 4, characterized in that, The peak concentrations corresponding to both the first and second type doped regions in the TFET substrate region are greater than 5E16cm⁻¹. -2 The surface concentration in the channel is less than 1E16cm. -2 .
10. The preparation method according to claim 4, characterized in that, Step 13) includes an annealing step for source / drain activation, and annealing to achieve impurity activation of the first type of doped region and the second type of doped region. At the same time, the substrate electrode region of the body lead-out region of the four-terminal TFET device is simultaneously formed by implanting the heavily doped region during the device fabrication process.