Semiconductor structure and method of manufacturing the same

Abstract

The present invention relates to a semiconductor structure and a method of fabricating the same. The semiconductor structure includes a core layer having a first conductivity type, and a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure further includes a first diffusion layer having the first conductivity type disposed in the substrate adjacent to the first surface, and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer having a second conductivity type disposed in the substrate adjacent to the second surface, and a plurality of diffusion regions having the first conductivity type disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer, and the substrate is sandwiched between the first electrode layer and the second electrode layer. Another embodiment of the present invention relates to a method of fabricating a semiconductor structure.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of manufacturing the same, and more specifically, to semiconductor structures having a plurality of diffusion regions. Background Technology

[0002] In flyback circuits, the diodes in the RCD (Resistor-Capacitor-Diode) circuit typically require high conduction speed and large reverse recovery charge to suppress or mitigate voltage spikes and circuit oscillations caused by transformer leakage inductance. Using a typical fast recovery diode (FRD) may prevent it from conducting quickly enough to transfer energy to the capacitor, resulting in voltage spikes and circuit oscillations, and even affecting overall circuit efficiency.

[0003] In conventional techniques, bipolar junction transistors (BJTs) can be used as diode components in RCD circuits by shorting their base and emitter to improve circuit efficiency. However, the manufacturing process of BJTs is complex and costly. Summary of the Invention

[0004] Embodiments of this disclosure relate to a semiconductor structure. The semiconductor structure includes a core layer having a first conductivity type and a substrate having a first surface and a second surface opposite to the first surface. The semiconductor structure further includes a first diffusion layer having the first conductivity type, disposed in the substrate and adjacent to the first surface; and a first electrode layer disposed on the first diffusion layer. The semiconductor structure further includes a second diffusion layer having a second conductivity type, disposed in the substrate and adjacent to the second surface; and a plurality of diffusion regions having the first conductivity type and disposed in the second diffusion layer. The semiconductor structure further includes a second electrode layer disposed on the second diffusion layer, with the substrate sandwiched between the first electrode layer and the second electrode layer.

[0005] Embodiments of this disclosure relate to a method of manufacturing a semiconductor structure. The method includes providing a core layer having a first conductivity type and a substrate having a first surface and a second surface opposite to the first surface. The method further includes diffusion from the first surface of the substrate into the substrate to form a first diffusion layer having the first conductivity type; and diffusion from the second surface of the substrate into the substrate to form a second diffusion layer having the second conductivity type. The method further includes forming a plurality of diffusion regions having the first conductivity type in the second diffusion layer; and forming a first electrode layer on the first diffusion layer. The method further includes forming a second electrode layer on the second diffusion layer, and sandwiching the substrate between the first electrode layer and the second electrode layer. Attached Figure Description

[0006] The various embodiments of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the structures are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various structures may be arbitrarily enlarged or reduced.

[0007] Figure 1 The diagram shown is a cross-sectional view of a semiconductor structure according to certain embodiments of this invention;

[0008] Figure 2 The diagram shown is a cross-sectional view of a semiconductor structure according to certain embodiments of this invention;

[0009] Figure 3A The diagram shown is a top view of a semiconductor structure according to certain embodiments of this invention;

[0010] Figure 3B The diagram shown is a top view of a semiconductor structure according to certain embodiments of this invention;

[0011] Figure 3C The diagram shown is a top view of a semiconductor structure according to certain embodiments of this invention; and

[0012] Figures 4A to 4H The diagram illustrates one or more stages in a method for manufacturing a semiconductor structure according to certain embodiments of this case.

[0013] Identical or similar components are designated using the same reference numerals in the drawings and detailed description. Several embodiments of this disclosure will be readily understood from the following detailed description in conjunction with the accompanying drawings. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0016] This disclosure provides a semiconductor structure and its manufacturing method. Compared to a conventional fast recovery diode (FRD), the semiconductor structure of this disclosure has an NPN or PNP structure similar to a bipolar junction transistor (BJT), exhibiting higher conduction speed and shorter reverse recovery time, thus effectively suppressing or mitigating voltage spikes and circuit oscillations. Furthermore, compared to a conventional BJT, the manufacturing method of the semiconductor structure of this disclosure utilizes double-diffusion technology and glass passivation technology, eliminating the need for epitaxial growth technology and requiring fewer masks, thereby simplifying the process and reducing costs.

[0017] Reference Figure 1 , Figure 1 The diagram shown is a cross-sectional view of a semiconductor structure 1 according to certain embodiments of the present invention. The semiconductor structure 1 may include a substrate 10, electrode layers 15 and 16, a polysilicon layer 17, and a glass layer 18.

[0018] The substrate 10 may include a semiconductor substrate, such as a silicon wafer. In some embodiments, the thickness H1 of the substrate 10 may be between about 220 micrometers (µm) and about 240 µm. In some embodiments, an N-type single-crystal silicon wafer with a volume resistivity between about 30 and about 45 Ohm-cm may be used to form the semiconductor structure 1.

[0019] The substrate 10 may have a surface 101 and a surface 102 opposite to the surface 101. In some embodiments, when viewed in cross-sectional view, the width of surface 101 may be greater than the width of surface 102. In some embodiments, the total surface area of ​​surface 101 may be greater than the total surface area of ​​surface 102.

[0020] In some embodiments, the substrate 10 may include a diffusion layer 11 adjacent to the surface 101, a diffusion layer 13 adjacent to the surface 102, and a core layer 12 located between the diffusion layer 11 and the diffusion layer 13. The diffusion layer 13 can be equivalently used as a base, and the diffusion layer 11 can be equivalently used as a collector.

[0021] The core layer 12 can be part of the original silicon wafer, and the core layer 12 can be doped with N-type impurities, for example in... Figure 1 The area marked with "N".

[0022] The diffusion layer 11 may include a semiconductor layer doped with N-type impurities. The diffusion layer 11 and the core layer 12 may have the same conductivity type; however, the impurity concentration of the diffusion layer 11 may be higher than that of the core layer 12. Figure 1 The region is designated as "N+". In some embodiments, the diffusion layer 11 can be formed by diffusing N-type impurities from the surface 101 of the substrate 10 into the substrate 10. N-type impurities may include pentavalent elements such as phosphorus, arsenic, and antimony. In some embodiments, a diffusion boundary 112 may be formed between the diffusion layer 11 and the core layer 12. In some embodiments, the diffusion boundary 112 is the boundary between a high-concentration N-type impurity (N+) region and an N-type impurity (N) region. The impurity concentration in the "N+" or "P+" regions used in this disclosure is higher than the impurity concentration in their neighboring regions.

[0023] The diffusion layer 13 may include a semiconductor layer doped with p-type impurities. The diffusion layer 13 and the core layer 12 may have opposite conductivity types. For example, a PN junction may be formed between the diffusion layer 13 and the core layer 12. The impurity concentration of the diffusion layer 13 may be higher than that of the core layer 12, therefore... Figure 1 The region is designated as "P+". In some embodiments, the diffusion layer 13 can be formed by diffusing P-type impurities from the surface 102 of the substrate 10 into the substrate 10. P-type impurities may include trivalent elements such as boron, aluminum, and gallium. In some embodiments, a diffusion boundary 131 may be formed between the diffusion layer 13 and the core layer 12. In some embodiments, the diffusion boundary 131 is the boundary between a high-concentration P-type impurity (P+) region and an N-type impurity (N) region.

[0024] In some embodiments, the diffusion layer 13 may include a plurality of diffusion regions 14 separated from each other. The diffusion regions 14 and the diffusion layer 13 may have opposite conductivity types. For example, each of the diffusion regions 14 may form a PN junction with the diffusion layer 13. The impurity concentration of the diffusion regions 14 may be higher than that of the diffusion layer 13, therefore... Figure 1 The region is marked as "N+". In some embodiments, the impurity concentration in the diffusion region 14 may be about 10 times or more higher than the impurity concentration in the diffusion layer 13.

[0025] The diffusion region 14 may be formed adjacent to the surface 102. For example, the diffusion region 14 may be partially exposed from the surface 102. For example, the surfaces of each of the diffusion regions 14 may be coplanar with the surface 102 of the substrate 10. In this embodiment, the diffusion region 14 does not extend to the diffusion boundary 131. In some embodiments, the distance (e.g., the minimum distance) between the diffusion region 14 and the diffusion boundary 131 is at least greater than about 15 µm.

[0026] Electrode layer 15 may be disposed on surface 101. For example, electrode layer 15 may be disposed on diffusion layer 11. For example, electrode layer 15 may contact or cover a portion of diffusion layer 11. For example, electrode layer 15 may completely cover surface 101. Electrode layer 15 may be considered as an electrical terminal of semiconductor structure 1. For example, electrode layer 15 may be electrically connected to an electrical terminal of semiconductor structure 1.

[0027] Electrode layer 16 may be disposed on surface 102. Substrate 10 may be sandwiched between electrode layer 15 and electrode layer 16. For example, electrode layer 16 may be disposed on diffusion layer 13. For example, electrode layer 16 may contact or cover a portion of diffusion layer 13.

[0028] In some embodiments, when viewed in cross-sectional view, the width of electrode layer 15 may be greater than the width of electrode layer 16. In some embodiments, the total surface area of ​​electrode layer 15 may be greater than the total surface area of ​​electrode layer 16.

[0029] In some embodiments, the surfaces of one or more diffusion regions 14 exposed from surface 102 may be covered by electrode layer 16. For example, electrode layer 16 may contact or cover one or more diffusion regions 14. In some embodiments, diffusion layer 13 may be coupled to each of diffusion regions 14 via electrode layer 16. For example, electrode layer 16 may be configured to short-circuit diffusion layer 13 and each of diffusion regions 14. For example, diffusion layer 13 and each of diffusion regions 14 may be considered as an electrical terminal of semiconductor structure 1. For example, diffusion layer 13 and each of diffusion regions 14 may be electrically connected to an electrical terminal of semiconductor structure 1, and electrode layer 15 may be electrically connected to another electrical terminal of semiconductor structure 1. For example, compared to a typical BJT, diffusion layer 13 and diffusion regions 14 can be short-circuited to each other without the need for other circuit components, achieving the effect of base-emitter short-circuit and being used as diode components in an RCD circuit.

[0030] In some embodiments, electrode layers 15 and 16 may comprise copper (Cu), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), tin (Sn), or other metals or alloys. In some embodiments, electrode layers 15 and 16 may comprise the same material, such as both being aluminum. In some embodiments, electrode layers 15 and 16 may comprise different materials, for example, electrode layer 15 may be aluminum, and electrode layer 16 may be silver, nickel, or titanium.

[0031] In some embodiments, substrate 10 may include a recessed ring 10r that is recessed downward or inward from surface 102. The recessed ring 10r may be located at the edge of substrate 10. The recessed ring 10r may surround electrode layer 16. In some embodiments, when viewed in cross-sectional view, the recessed ring 10r may have an arcuate surface. In some embodiments, when viewed in top view, the recessed ring 10r may be rectangular, such as square or elongated. Electrode layer 16 may be located within said rectangle. However, the semiconductor structure 1 of the present invention may have a recessed ring 10r of any shape.

[0032] In some embodiments, the groove ring 10r may extend downward from the surface 102 beyond the diffusion boundary 112 to facilitate a higher breakdown voltage in the semiconductor structure. For example, the groove ring 10r may extend to the diffusion layer 11. For example, a portion of the diffusion layer 11 may be exposed from the groove ring 10r. For example, the bottom of the groove ring 10r may be located within the diffusion layer 11. In some embodiments, the thickness H2 of the groove ring 10r (e.g., the longest distance from the surface 102 to the bottom of the groove ring 10r) may be about 80 µm. In some embodiments, the thickness H2 of the groove ring 10r may be between about 30% and about 50% of the thickness H1 of the substrate 10.

[0033] A polysilicon layer 17 may be disposed on the groove ring 10r. The polysilicon layer 17 may be located at the edge of the substrate 10. The polysilicon layer 17 may surround the electrode layer 16. The polysilicon layer 17 may include semi-insulating polycrystalline silicon (SIPOS). In some embodiments, the polysilicon layer 17 may contact or cover the surface of the groove ring 10r. For example, the polysilicon layer 17 may completely contact or cover the surface of the groove ring 10r. For example, the polysilicon layer 17 may contact or cover a portion of the diffusion layer 11. For example, the polysilicon layer 17 may contact or cover a portion of the core layer 12. For example, the polysilicon layer 17 may contact or cover a portion of the diffusion layer 13.

[0034] In some embodiments, the polysilicon layer 17 may contact or cover a portion of the surface 102. In some embodiments, the polysilicon layer 17 may contact or cover a portion of one or more diffusion regions 14. In some embodiments, the polysilicon layer 17 may extend from the groove ring 10r toward the electrode layer 16 and contact the edge of the electrode layer 16. In some embodiments, the polysilicon layer 17 and the electrode layer 16 may be coplanar. In some embodiments, the thickness of the polysilicon layer 17 may be greater than the thickness of the electrode layer 16. In some embodiments, the thickness of the electrode layer 16 may be greater than the thickness of the polysilicon layer 17.

[0035] A glass layer 18 may be disposed on the groove ring 10r and the polysilicon layer 17. The polysilicon layer 17 may be located between the glass layer 18 and the groove ring 10r. The glass layer 18 may be located at the edge of the substrate 10. The glass layer 18 may surround the electrode layer 16. In some embodiments, the glass layer 18 may fill the groove ring 10r. For example, the glass layer 18 may completely fill the groove ring 10r. In some embodiments, the glass layer 18 may contact or cover a portion of the polysilicon layer 17.

[0036] In some embodiments, glass layer 18 may cover a portion of surface 102. In some embodiments, glass layer 18 may cover a portion of diffusion region 14. In some embodiments, glass layer 18 may cover a portion of diffusion layer 13. In some embodiments, glass layer 18 may cover a portion of core layer 12. In some embodiments, glass layer 18 may cover a portion of diffusion layer 11.

[0037] In some embodiments, the glass layer 18 may be separated from the surface 102 by the polysilicon layer 17. In some embodiments, the glass layer 18 may be separated from the diffusion region 14 by the polysilicon layer 17. In some embodiments, the glass layer 18 may be separated from the diffusion layer 13 by the polysilicon layer 17. In some embodiments, the glass layer 18 may be separated from the core layer 12 by the polysilicon layer 17. In some embodiments, the glass layer 18 may be separated from the diffusion layer 11 by the polysilicon layer 17. In some embodiments, the glass layer 18 may not contact the electrode layer 16.

[0038] Reference Figure 2 , Figure 2 The diagram shown is a cross-sectional view of a semiconductor structure 2 according to certain embodiments of this case. Figure 2 Semiconductor structure 2 shown Figure 1 Elements that are the same as or similar to those in the semiconductor structure 1 shown are identified by the same element symbols, and detailed descriptions of the elements will not be repeated.

[0039] The conductivity type of semiconductor structure 2 may be the opposite of that of semiconductor structure 1. Semiconductor structure 2 may use a semiconductor substrate doped with P-type impurities. The core layer 12 may be part of a pristine P-type single-crystal silicon wafer, for example... Figure 2 The region marked "P" is shown in the diagram. The diffusion layer 11 may include a semiconductor layer doped with P-type impurities. The diffusion layer 11 and the core layer 12 may have the same conductivity type; however, the impurity concentration of the diffusion layer 11 may be higher than that of the core layer 12. Figure 2 The area marked as "P+" is the center mark.

[0040] The diffusion layer 13 may include a semiconductor layer doped with N-type impurities. The diffusion layer 13 and the core layer 12 may have opposite conductivity types. For example, a PN junction may be formed between the diffusion layer 13 and the core layer 12. The impurity concentration of the diffusion layer 13 may be higher than that of the core layer 12, therefore... Figure 2 The area marked as "N+" is the central label.

[0041] The diffusion layer 13 may include a plurality of diffusion regions 14 separated from each other. The diffusion regions 14 and the diffusion layer 13 may have opposite conductivity types. For example, each of the diffusion regions 14 may form a PN junction with the diffusion layer 13. The impurity concentration of the diffusion regions 14 may be higher than that of the diffusion layer 13, therefore... Figure 2 The area marked as "P+" is the center mark.

[0042] In some embodiments, the thickness H1 of the substrate 10 of the semiconductor structure 2 may be between about 240 µm and about 260 µm. In some embodiments, the thickness H2 of the groove ring 10r (e.g., the longest distance from the surface 102 to the bottom of the groove ring 10r) may be about 80-120 µm. In some embodiments, the thickness H2 of the groove ring 10r may be between about 30% and about 50% of the thickness H1 of the substrate 10.

[0043] In some embodiments, the electrode layer 16 of the semiconductor structure 2 may contact or cover the polysilicon layer 17. For example, in a direction perpendicular to surface 102, a portion of the polysilicon layer 17 may be located between surface 102 and electrode layer 16. For example, in a direction perpendicular to surface 102, polysilicon layer 17 and electrode layer 16 may partially overlap. In some embodiments, the electrode layer 16 of the semiconductor structure 2 may contact the glass layer 18. However, in some embodiments, the electrode layer 16 of the semiconductor structure 2 may also be coplanar with the polysilicon layer 17, for example... Figure 1 As shown. Similarly, in some embodiments, the polysilicon layer 17 and the electrode layer 16 of the semiconductor structure 1 may partially overlap in a direction perpendicular to the surface 102, for example... Figure 2 As shown.

[0044] Reference Figures 3A to 3C , Figures 3A to 3C The diagram shown is a top view of a semiconductor structure according to certain embodiments of this invention. In some embodiments, semiconductor structure 1 and semiconductor structure 2 may have the following characteristics: Figures 3A to 3C The top view shown in either of them.

[0045] like Figure 3A As shown, in some embodiments, the diffusion regions (e.g., diffusion regions 14 of semiconductor structure 1 and semiconductor structure 2) may include diffusion regions 14a and 14b that are separated from each other. In some embodiments, the diffusion regions including diffusion regions 14a and 14b may be arranged in a matrix. Although the figures disclosed herein depict a 4-column, 4-row matrix, the semiconductor structure of the present invention may also have diffusion regions arranged in a matrix of any number of columns or rows.

[0046] In some embodiments, the diffusion regions, including diffusion regions 14a and 14b, may be circular or near-circular (e.g., elliptical). However, the semiconductor structure of the present invention may also have diffusion regions of any shape.

[0047] like Figure 3BAs shown, in some embodiments, the diffusion region (e.g., diffusion region 14 of semiconductor structure 1 and semiconductor structure 2) may include diffusion regions 14c, 14d, and 14e that are separated from each other. Diffusion region 14e may be located in the central region of diffusion layer 13 and may be rounded rectangular. Diffusion region 14d may surround diffusion region 14e. Diffusion region 14c may surround diffusion region 14d. For example, diffusion regions 14c, 14d, and 14e are concentric structures.

[0048] Figure 3C and Figure 3B Similar, the difference lies in Figure 3C The diffusion zone 14e' located in the central area is not solid.

[0049] In some embodiments, the position, shape, area ratio, and number of diffusion regions can be adjusted to be applied to different circuits.

[0050] Reference Figures 4A to 4H , Figures 4A to 4H The figures illustrate one or more stages in a method of manufacturing a semiconductor structure according to certain embodiments of this application. At least some of these figures have been simplified to better understand the nature of this disclosure.

[0051] Reference Figure 4A The manufacturing method includes providing a substrate 10. The substrate 10 may include a semiconductor substrate doped with N-type or P-type impurities. Figures 4A to 4H The embodiments shown and the following description use an N-type silicon wafer as the substrate 10. In some embodiments, the thickness of the substrate 10 may be between about 350 µm and about 370 µm. In some embodiments, an N-type silicon wafer with a volume resistivity between about 30 and about 45 Ohm-cm may be used. The substrate 10 may have a surface 101 and a surface 102' opposite to the surface 101.

[0052] Reference Figure 4B N-type impurities are diffused from surfaces 101 and 102' of substrate 10 using a double-sided diffusion technique. The double-sided diffusion may include N-type impurity pre-deposition and N-type impurity main diffusion. For example, using phosphorus, phosphorus oxychloride (POCl3) can be used as the phosphorus source for pre-deposition. Then, main diffusion is performed on the pre-deposited substrate 10 to advance the diffusion boundary and form a deeper N+ layer. After double-sided diffusion, substrate 10 forms an N+ / N / N+ structure, including a diffusion layer 40 adjacent to surface 102', a core layer 12, and a diffusion layer 11 adjacent to surface 101. In some embodiments, the thickness (or diffusion depth) H3 of diffusion layer 40 and diffusion layer 11 may be approximately 120 µm.

[0053] If a P-type silicon wafer is used as substrate 10, P-type impurities can be diffused from surfaces 101 and 102' of substrate 10. Double-sided diffusion can include P-type impurity pre-deposition and main P-type impurity diffusion. Taking boron as an example, boron trichloride (BCl3) can be used as the boron source for pre-deposition. Then, main diffusion is performed on the pre-deposited substrate 10 to advance the diffusion boundary and form a deeper P+ layer. After double-sided diffusion, substrate 10 forms a P+ / P / P+ structure.

[0054] Reference Figure 4C The substrate 10 is ground and polished from surface 102' to remove a portion of the diffusion layer 40, reducing the thickness H4 of the diffusion layer 40 to approximately 20 µm. The ground and polished substrate 10 has a new surface 102. Then, P-type impurities are diffused from surface 102 of the substrate 10. Diffusion may include P-type impurity pre-deposition and P-type impurity main diffusion. For example, using boron, boron trichloride (BCl3) can be used as the boron source for pre-deposition. The pre-deposited substrate 10 is then subjected to main diffusion to invert the remaining diffusion layer 40 from N-type to P-type. After diffusion, the substrate 10 forms a P+ / N / N+ structure, including a diffusion layer 13 adjacent to surface 102, a core layer 12, and a diffusion layer 11 adjacent to surface 101. In some embodiments, the substrate 10 may be ground and polished from surface 102' to completely remove the diffusion layer 40, exposing the core layer 12. Then, P-type impurities are diffused from core layer 12 to invert a portion of core layer 12 from N-type to P-type.

[0055] If a P-type silicon wafer is used as substrate 10, N-type impurities can be diffused from the surface 102 of substrate 10 (where the diffusion layer 40 is partially removed) or from the core layer 12 (where the diffusion layer 40 is completely removed). Diffusion may include N-type impurity pre-deposition and N-type impurity main diffusion. Taking phosphorus as an example, phosphorus oxychloride (POCl3) can be used as the phosphorus source for pre-deposition. Then, main diffusion is performed on the pre-deposited substrate 10 to reverse the remaining diffusion layer 40 or a portion of the core layer 12 from P-type to N-type.

[0056] Reference Figure 4DA base mask (not shown) is formed on the surface 102 of the substrate 10. The base mask may have a plurality of openings to define the pattern of diffusion regions 14 (i.e., N+ regions). The base mask may define the location of the PN junction; for example, the base mask may simultaneously define the base and the emitter. Then, N-type impurities are diffused from the surface 102 of the substrate 10 to form a plurality of mutually separated diffusion regions 14 in the diffusion layer 13. For example, phosphorus oxychloride (POCl3) may be used as the phosphorus source. The base mask prevents phosphorus from diffusing into the diffusion layer 13. The base mask may be removed by etching, stripping, or other suitable processes.

[0057] If a P-type silicon wafer is used as substrate 10, boron trichloride (BCl3) can be used as a source of boron to form a plurality of P+ regions that are separated from each other in diffusion layer 13.

[0058] Reference Figure 4E A mesa mask (not shown) is formed on the surface 102 of the substrate 10. The mesa mask may have openings to define the position of the groove ring 10r, forming a raised mesa region surrounded by the groove ring 10r. A chemical etching region is formed in the substrate 10 using photolithography techniques such as resist coating, exposure, and development, and the groove ring 10r is formed by solution etching of the chemical etching region. The groove ring 10r may extend to the diffusion layer 11. In some embodiments, the thickness H2 of the groove ring 10r (e.g., the longest distance from the surface 102 to the bottom of the groove ring 10r) may be approximately 80 µm. The mesa mask may be removed by etching, stripping, or other suitable processes.

[0059] Reference Figure 4F A polysilicon layer 17 is formed in the groove ring 10r. In some embodiments, the polysilicon layer 17 can be formed by a SIPOS deposition process.

[0060] Reference Figure 4G A glass layer is formed in the groove ring 10r and on the polysilicon layer 17. In some embodiments, the glass layer may be coated onto the substrate 10. In some embodiments, a photoresist liquid may be incorporated into the molten glass to form a photoresist glass liquid, which is then coated onto the substrate 10. In some embodiments, a glass mask (not shown) is formed on the surface 102 of the substrate 10. The glass mask may have openings to define the location of the glass layer 18. A portion of the glass layer may be removed using photolithography and a firing process to form the glass layer 18. After the portion of the glass layer is removed, the polysilicon layer 17 on the surface 102 is exposed from the glass layer 18. The glass mask may be removed by etching, stripping, or other suitable processes.

[0061] Reference Figure 4H A contact mask (optionally, not shown) is formed on the polysilicon layer 17. The contact mask may have openings to define the size of the openings in the polysilicon layer 17. A portion of the polysilicon layer 17 exposed from the glass layer 18 on surface 102 can be removed using photolithography, exposing a portion of the diffusion layer 13 and diffusion region 14. The exposed portion will directly contact the conductive contact structure subsequently formed thereon, namely the electrode layer 16. In this embodiment, a portion of the polysilicon layer 17 remains on surface 102. The contact mask can be removed by etching, stripping, or other suitable processes.

[0062] In some embodiments, the opening size of the polysilicon layer 17 can be defined directly through the glass layer 18 without using a contact mask, that is, the polysilicon layer 17 exposed from the glass layer 18 on the surface 102 can be completely removed using photolithography.

[0063] Subsequently, electrode layers 15 and 16 are formed on surfaces 101 and 102 using a metal mask (not shown in the figure), short-circuiting the diffusion layer 13 (equivalent to the base) and the diffusion region 14 (equivalent to the emitter), and sandwiching the substrate 10 between electrode layers 15 and 16. In some embodiments, electrode layers 15 and 16 can be formed by sputtering, electroless plating, electroplating, printing, or other suitable processes. In some embodiments, electrode layer 16 is not deposited on polysilicon layer 17 (e.g., Figure 1 (As shown). In some embodiments, electrode layer 16 may be deposited on polysilicon layer 17 (as shown). Figure 2 (As shown). The metal mask can be removed by etching, stripping, or other suitable processes. The semiconductor structure formed by the above steps can be used with... Figure 1 or Figure 2 The semiconductor structure shown is the same as semiconductor structure 1 or semiconductor structure 2.

[0064] The semiconductor structure manufacturing method of this invention can realize NPN or PNP transistors without using existing BJT processes, and during forward conduction, the PN junction mainly provides current conduction. During turn-on and turn-off, the NPN or PNP transistors function due to current and voltage surges, reducing circuit oscillations and improving efficiency. Different circuits can be matched by adjusting the effective area ratio of N+ or P+ according to different circuits. As mentioned above, the semiconductor structure manufacturing method of this invention uses 4 or 5 types of masks, including a base mask, mesa mask, glass mask, contact mask (optionally), and metal mask. Compared to BJT manufacturing methods (which typically require at least 6 or 7 types of masks), this invention requires fewer masks, thus simplifying the process and reducing costs.

[0065] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one component or feature as shown in the accompanying drawings and one or more other components or features. In addition to the orientation depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to the other component, or there may be an intermediate component present.

[0066] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0067] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure comprising: A substrate having a core layer of a first conductivity type and having a first surface and a second surface opposite to the first surface; A first diffusion layer having a first conductivity type is disposed in the substrate and adjacent to the first surface; A first electrode layer is disposed on the first diffusion layer; A second diffusion layer having a second conductivity type is disposed in the substrate and adjacent to the second surface; A plurality of diffusion regions having a first conductivity type and disposed in the second diffusion layer; as well as A second electrode layer is disposed on the second diffusion layer, and the substrate is sandwiched between the first electrode layer and the second electrode layer. The second diffusion layer is a second conductivity type region with high impurity concentration. The second electrode layer directly contacts the second diffusion layer and the plurality of diffusion regions, so that the second diffusion layer and the plurality of diffusion regions are directly short-circuited to each other under the second electrode layer, and each of the second diffusion layer and the plurality of diffusion regions can be short-circuited to each other without the need for other circuit components.

2. The semiconductor structure according to claim 1, wherein the second diffusion layer and the plurality of diffusion regions are electrically connected to an electrical terminal of the semiconductor structure, and the first diffusion layer is electrically connected to another electrical terminal of the semiconductor structure.

3. The semiconductor structure according to claim 1, wherein the concentration of a first conductivity type impurity in the first diffusion layer is higher than the concentration of a first conductivity type impurity in other regions of the substrate.

4. The semiconductor structure according to claim 1, wherein the concentration of the first conductivity type impurity in the plurality of diffusion regions is higher than the concentration of the second conductivity type impurity in the second diffusion layer.

5. The semiconductor structure of claim 1, wherein the plurality of diffusion regions are exposed from the second surface of the substrate and covered by the second electrode layer.

6. The semiconductor structure of claim 1, wherein each of the plurality of diffusion regions has a surface coplanar with the second surface of the substrate.

7. The semiconductor structure according to claim 1, wherein the plurality of diffusion regions do not extend to the diffusion boundary of the second diffusion layer, and the shortest distance between the plurality of diffusion regions and the diffusion boundary is at least greater than 15 μm.

8. The semiconductor structure according to claim 1, wherein the plurality of diffusion regions includes a first diffusion region and a second diffusion region separated from the first diffusion region.

9. The semiconductor structure of claim 8, wherein the first diffusion region surrounds the second diffusion region.

10. The semiconductor structure according to claim 1, wherein the plurality of diffusion regions are arranged in a matrix.

11. The semiconductor structure of claim 1, further comprising a groove ring formed in the substrate.

12. The semiconductor structure of claim 11, wherein the groove ring extends downward from the second surface of the substrate beyond the diffusion boundary of the first diffusion layer, such that the bottom of the groove ring enters the first diffusion layer.

13. The semiconductor structure of claim 11, wherein the thickness of the groove ring is between 30% and 50% of the thickness of the substrate.

14. The semiconductor structure of claim 11, further comprising a glass layer disposed on the groove ring.

15. The semiconductor structure of claim 14, wherein the glass layer further covers a portion of the second surface and surrounds the second electrode.

16. The semiconductor structure of claim 14, further comprising a polycrystalline silicon layer disposed between the glass layer and the groove ring.

17. The semiconductor structure of claim 16, wherein the polysilicon layer extends toward the second electrode layer and contacts the edge of the second electrode layer.

18. The semiconductor structure of claim 17, wherein the polysilicon layer partially covers at least one of the plurality of diffusion regions.

19. A method for manufacturing a semiconductor structure, comprising: A substrate is provided having a core layer of a first conductivity type and having a first surface and a second surface opposite to the first surface; A first diffusion layer having a first conductivity type is formed by diffusion from the first surface of the substrate into the substrate. A second diffusion layer having a second conductivity type is formed by diffusion from the second surface of the substrate into the substrate. A plurality of diffusion regions are formed in the second diffusion layer, each having a first conductivity type; A first electrode layer is formed on the first diffusion layer; as well as A second electrode layer is formed on the second diffusion layer, and the substrate is sandwiched between the first electrode layer and the second electrode layer, wherein... Diffusion from the second surface of the substrate into the substrate to form the second diffusion layer further includes: A diffusion layer having a first conductivity type is formed by diffusion from the second surface of the substrate into the substrate. Remove at least a portion of the diffusion layer; and The remaining diffusion layer is reversed to a second conductivity type by diffusion to form the second diffusion layer.

20. The manufacturing method of claim 19, wherein the second electrode layer contacts the plurality of diffusion regions such that the second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer; wherein the second diffusion layer and the plurality of diffusion regions are electrically connected to one electrical terminal of the semiconductor structure, and the first diffusion layer is electrically connected to another electrical terminal of the semiconductor structure.

21. The manufacturing method according to claim 19, further comprising: A groove ring is formed in the second diffusion layer and the substrate; and A glass layer is formed in the groove ring, which covers at least a portion of the second surface of the substrate.

Images