Power semiconductor device

Abstract

The application provides a power semiconductor device, which can play a role of auxiliary depletion and reduced switching loss by adding a shield gate trench under a gate in a device medium groove. A buried layer is introduced at the bottom of the device, and a connecting area is introduced between the drain of the device and the buried layer, so that the drain potential can be introduced into the body of the device, and the current carriers can be led out from the surface of the device after passing through the channel and the drift region. In the application, integrated SGT power semiconductor structures suitable for multi-channel, voltage level expansion, anti-punch-through design and short channel design are provided for different types of SGT structures. The application provides an integrated SGT structure for the SGT device, so that the SGT device can be integrated in a planar process, and the integration degree of the chip is improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductors, specifically relating to a power semiconductor device. Background Technology

[0002] With the development of electronic power technology, power semiconductor devices are gradually being updated and replaced. Traditional power devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) have become one of the most important and irreplaceable devices in the field of power integrated circuits due to their advantages such as high input impedance, fast switching speed, and low conduction loss.

[0003] To further improve the current handling capability and reduce power loss of traditional MOSFETs, the Split Gate Trench MOSFET (SGT-MOSFET) is a successful improved structure. The SGT-MOSFET power device works by introducing a shielded gate structure beneath the trench gate structure. This reduces the gate-drain overlap area and gate-drain capacitance, thereby lowering dynamic switching losses. Furthermore, the shielded gate aids in depleting the carrier drift region, optimizing the breakdown voltage (BV) and specific on-resistance (R). on，sp ).

[0004] However, although SGT-MOSFETs offer superior power characteristics, they are currently typically vertically mounted devices, limiting their application in power integration technology. If the drain of an SGT device could be extracted from the bulk via bulk doping, planar process compatibility could be achieved. SGT devices have relatively low breakdown voltage, classifying them as low- to medium-voltage devices. When aiming for compatibility with advanced planar processes, considerations such as punch-through resistance, short-channel design, voltage level extension design, and layout design are necessary. To improve the various electrical performance characteristics of SGT-MOSFETs and integrate them with power integration technology, embodiments of this invention have emerged. Summary of the Invention

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] A power semiconductor device includes a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first conductivity type drift region 103 and a second conductivity type connection region 108 disposed above the second conductivity type buried layer 102; a second conductivity type drain region 107 disposed above the second conductivity type connection region 108; and a first conductivity type body region 104 and a trench region disposed above the first conductivity type drift region 103.

[0007] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction.

[0008] A second drift region 120 of the second conductivity type is disposed above the first drift region 103 of the second conductivity type, and the second drift region 120 of the second conductivity type is located between the body region 104 of the first conductivity type and the connection region 108 of the second conductivity type; a second gate oxide layer 112 is disposed above the body region 104 of the first conductivity type and above a portion of the second drift region 120 of the second conductivity type, and a second gate electrode 110 is disposed above the second gate oxide layer 112; a metal silicide barrier layer 116 is disposed above the second drift region 120 of the second conductivity type and above a portion of the second gate electrode 110, and a source field plate electrode 118 is disposed above the metal silicide barrier layer 116; a source electrode metal 117 is disposed above the source region 105 of the second conductivity type and the contact region 106 of the first conductivity type, and a drain electrode metal 119 is disposed above the drain region 107 of the second conductivity type.

[0009] As a preferred embodiment, a first conductivity type buried layer 121 is provided below the second drift region 120 of the second conductivity type.

[0010] The present invention provides a second type of power semiconductor device, comprising a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first conductivity type drift region 103 and a second conductivity type connection region 108 disposed above the second conductivity type buried layer 102; a second conductivity type drain region 107 disposed above the second conductivity type connection region 108; and a first conductivity type body region 104 and a trench region disposed above the first conductivity type drift region 103.

[0011] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. An insulating dielectric layer 114 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction.

[0012] A source region electrode metal 117 is disposed above the second conductivity type source region 105 and the first conductivity type contact region 106, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0013] The second drift region 120, the second gate electrode 110, the second gate oxide layer 112, the metal silicide barrier layer 116, and the source field plate electrode 118 of the second conductivity type are removed to form a single-channel structure.

[0014] For devices with extended voltage levels, the present invention provides a third type of power semiconductor device, including a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a second conductivity type first drift region 103 and a connection region 122 disposed above the second conductivity type buried layer 102, the bottom of the connection region 122 being tangent to the second conductivity type buried layer 102, and a first conductivity type body region 104, a second conductivity type second drift region 120 and a trench region disposed on the surface of the second conductivity type first drift region 103.

[0015] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first conductivity type contact region 106 and a second conductivity type source region 105 are provided above the surface of the first conductivity type body region 104, and the two are arranged alternately in the width direction. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106.

[0016] The second drift region 120 of the second conductivity type is located between the body region 104 and the connection region 122 of the first conductivity type; the drain region 107 of the second conductivity type is located on the upper right side inside the second drift region 120 of the second conductivity type, and the right surface of the drain region 107 is tangent to the drain dielectric isolation layer 123; a source electrode metal 117 is disposed above the contact region 106 of the first conductivity type and the source region 105 of the second conductivity type; a second gate oxide layer 112 is disposed above the body region 104 of the first conductivity type and the portion above the second drift region 120 of the second conductivity type. A second gate electrode 110 is disposed above the silicide layer 112; a metal silicide barrier layer 116 is disposed above the second drift region 120 of the second conductivity type and above a portion of the second gate electrode 110, and a source field plate electrode 118 is disposed above the metal silicide barrier layer 116; a drain electrode metal 119 is disposed above the drain region 107 of the second conductivity type and the connection region 122; a drain dielectric isolation layer 123 is disposed between the second drift region 120 of the second conductivity type, the first drift region 103 of the second conductivity type, the drain region 107 of the second conductivity type and the connection region 122.

[0017] As a preferred embodiment, a first conductivity type buried layer 121 is provided below the second drift region 120 of the second conductivity type.

[0018] For devices with a source-center layout structure, the present invention provides a fourth type of power semiconductor device, including a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first conductivity type drift region 103 and a second conductivity type connection region 108 located on both sides of the first conductivity type drift region 103 disposed above the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed on the surface of the second conductivity type connection region 108, and a first conductivity type body region 104 and trench regions on both sides of the first conductivity type body region 104 disposed above the second conductivity type drift region 103.

[0019] The trench region is tangent to the second conductivity type connection region 108. The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, the first conductivity type contact region 106, the second conductivity type connection region 108, and the second conductivity type drain region 107.

[0020] Above the first conductive type body region 104 are a second conductive type source region 105 and a first conductive type contact region 106, which are arranged alternately in the width direction. A drain region electrode metal 119 is provided above the second conductive type drain region 107, and a source region electrode metal 117 is provided above the second conductive type source region 105 and the first conductive type contact region 106.

[0021] For devices designed to withstand punch-through, the present invention provides a fifth type of power semiconductor device, including a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first drift region 103 and a second conductivity type connection region 108 disposed on the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed above the second conductivity type connection region 108, and a trench region disposed on the surface region of the first drift region 103 of the second conductivity type.

[0022] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0023] The power semiconductor device includes a second conductivity type source region 105. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is partially included by a first conductivity type contact region 106. The depth of the first conductivity type contact region 106 is greater than the depth of the second conductivity type source region 105, and the depth of the first conductivity type contact region 106 is consistent with the depth of the first conductivity type body region 104. A source region electrode metal 117 is disposed above a portion of the second conductivity type source region 105 and a portion of the first conductivity type contact region 106, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0024] The present invention provides a sixth type of power semiconductor device, including a first type of conductivity substrate 101, a second type of conductivity buried layer 102 disposed on the first type of conductivity substrate 101, a first type of conductivity drift region 103 and a second type of conductivity connection region 108 disposed on the second type of conductivity buried layer 102, a second type of conductivity drain region 107 disposed above the second type of conductivity connection region 108, and a trench region disposed on the surface region of the first type of conductivity drift region 103.

[0025] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0026] A source region electrode metal 117 is disposed above a portion of the second conductivity type source region 105, a portion of the first conductivity type anti-penetration structure 124, and a portion of the first conductivity type body region 104, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0027] A first conductivity type body region 104 is disposed above the first drift region 103 of the second conductivity type. A second conductivity type source region 105 and a first conductivity type contact region 106 are disposed above the first conductivity type body region 104, both of which are tangent to the side surface of the first gate oxide layer 113. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is blocked by the first conductivity type anti-penetration structure 124. The structure includes a first conductivity type anti-penetration structure 124 disposed below the second conductivity type source region 105, and the first conductivity type body region 104 is formed between the first conductivity type anti-penetration structure 124 and the first gate oxide layer 113; the first conductivity type body region 104 is formed between the side of the first conductivity type anti-penetration structure 124 near the second conductivity type connection region 108 and the first drift region 103 of the second conductivity type; and a first conductivity type anti-penetration structure 124 in contact with the first gate oxide layer 113 is disposed below the first conductivity type contact region 106.

[0028] The present invention provides a seventh type of power semiconductor device, including a first type of conductivity substrate 101, a second type of conductivity buried layer 102 disposed on the first type of conductivity substrate 101, a first type of conductivity drift region 103 and a second type of conductivity connection region 108 disposed on the second type of conductivity buried layer 102, a second type of conductivity drain region 107 disposed above the second type of conductivity connection region 108, a drain region electrode metal 119 disposed above the second type of conductivity drain region 107, and a trench region disposed on the surface region of the first type of conductivity drift region 103.

[0029] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0030] A first conductivity type body region 104 is disposed above the second conductivity type drift region 103. A second conductivity type source region 105 and a first conductivity type contact region 106 are disposed above the first conductivity type body region 104, and the two are arranged alternately in the width direction. A first conductivity type auxiliary depletion body region 125 is disposed on the side of the first conductivity type body region 104 away from the first gate oxide layer 113. The depth of the first conductivity type auxiliary depletion body region 125 is deeper than that of the first conductivity type body region 104, and the doping concentration is the same as that of the first conductivity type body region 104. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is partially contained by the first conductivity type auxiliary depletion body region 125. On the side away from the first gate oxide layer 113, the first conductivity type contact region 106 is partially contained by the first conductivity type auxiliary depletion body region 125. A source region electrode metal 117 is disposed above the second conductivity type source region 105 and the first conductivity type contact region 106.

[0031] As a preferred embodiment, the potential of the shielded gate electrode is connected to zero, or is provided by a bias circuit.

[0032] The beneficial effects of this invention are as follows: This invention is based on SGT technology, specifically involving integrated SGT power semiconductor devices. Unlike discrete SGT devices, the series of power semiconductor devices provided by this invention, except for the ground signal which is on the other side of the substrate, have all other signals exposed through the surface, improving the integrability of traditional SGT devices. Based on advanced power semiconductor processes, this invention employs mesh technology to further reduce the cell size of the device, thereby increasing the integration density of the power semiconductor device cells and further reducing the specific on-resistance of the device. Using integrated SGT technology, the shielding gate is placed within the dielectric trench, below the gate electrode, which helps reduce the gate charge and switching losses. Simultaneously, by controlling the potential of the shielding gate electrode, auxiliary depletion of the drift region can be achieved.

[0033] The key technology of this invention lies in the integration of punch-through SGT devices. Compared with traditional SGT devices, the SGT device provided by this invention also has a vertically distributed channel, unlike the lateral channel of LDMOS. After the charge carriers exit the channel, they enter the drift region and drift to the high-concentration drain extension region under the action of the electric field. The extension of the drain is achieved through a high-concentration buried layer and interconnection region. Attached Figure Description

[0034] Figure 1 This is a layout structure of a power semiconductor device provided in Embodiment 1 of the present invention.

[0035] Figure 2(a) shows the A-A' cross-section corresponding to a power semiconductor device structure provided in Embodiment 1 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the second conductivity type source region 105;

[0036] Figure 2(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 1 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the first conductivity type contact region 106.

[0037] Figure 3 This is a layout structure of a power semiconductor device provided in Embodiment 2 of the present invention.

[0038] Figure 4(a) shows the A-A' cross-section of a power semiconductor device structure provided in Embodiment 2 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the drain region 107 of the second conductivity type and passing through the source region 105 of the second conductivity type.

[0039] Figure 4(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 2 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the first conductivity type contact region 106.

[0040] Figure 5(a) shows the A-A' cross-section corresponding to a power semiconductor device structure provided in Embodiment 3 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the second conductivity type source region 105;

[0041] Figure 5(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 3 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the first conductivity type contact region 106.

[0042] Figure 6 This is a layout structure of a power semiconductor device provided in Embodiment 4 of the present invention.

[0043] Figure 7(a) shows the A-A' cross-section of a power semiconductor device structure provided in Embodiment 4 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the connection region 122 and passing through the source region 105 of the second conductivity type.

[0044] Figure 7(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 4 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the connection region 122 and passing through the first conductivity type contact region 106;

[0045] Figure 8(a) shows the A-A' cross-section of a power semiconductor device structure provided in Embodiment 5 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the connection region 122 and passing through the source region 105 of the second conductivity type.

[0046] Figure 8(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 5 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the connection region 122 and passing through the first conductivity type contact region 106;

[0047] Figure 9 This is a layout structure of a power semiconductor device provided in Embodiment 6 of the present invention.

[0048] Figure 10 The A-A' cross-section corresponds to a power semiconductor device structure provided in Embodiment 6 of the present invention. The A-A' cross-section is a cross-section extending from the left side of the second conductivity type source region 105 (which serves as the source center) to the right side of the second conductivity type drain region 107, and passing through the second conductivity type source region 105.

[0049] Figure 11 This is a layout structure of a power semiconductor device provided in Embodiment 7 of the present invention.

[0050] Figure 12 The A-A' cross-section corresponds to a power semiconductor device structure provided in Embodiment 7 of the present invention. The A-A' cross-section is a cross-section extending from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the second conductivity type source region 105.

[0051] Figure 13 This is a layout structure of a power semiconductor device provided in Embodiment 8 of the present invention.

[0052] Figure 14(a) shows the A-A' cross-section corresponding to a power semiconductor device structure provided in Embodiment 8 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the second conductivity type source region 105;

[0053] Figure 14(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 8 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the first conductivity type contact region 106.

[0054] Figure 15 This is a layout structure of a power semiconductor device provided in Embodiment 9 of the present invention.

[0055] Figure 16(a) shows the A-A' cross-section corresponding to a power semiconductor device structure provided in Embodiment 9 of the present invention. The A-A' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the second conductivity type source region 105;

[0056] Figure 16(b) shows a B-B' cross-section corresponding to a power semiconductor device structure provided in Embodiment 9 of the present invention. The B-B' cross-section is the cross-section from the first gate electrode 109 to the second conductivity type drain region 107 and passing through the first conductivity type contact region 106.

[0057] Wherein, 101 is a substrate of the first conductivity type, 102 is a buried layer of the second conductivity type, 103 is a first drift region of the second conductivity type, 104 is a body region of the first conductivity type, 105 is a source region of the second conductivity type, 106 is a contact region of the first conductivity type, 107 is a drain region of the second conductivity type, 108 is a connection region of the second conductivity type, 109 is a first gate electrode, 110 is a second gate electrode, 111 is a shielding gate electrode, 112 is a second gate oxide layer, 113 is a first gate oxide layer, 114 is an insulating dielectric layer, 115 is a field oxide layer, 116 is a metal silicide barrier layer, 117 is a source electrode metal, 118 is a source-field plate electrode, 119 is a drain electrode metal, 120 is a second drift region of the second conductivity type, 121 is a buried layer of the first conductivity type, 122 is a connection region, 123 is a drain dielectric isolation layer, 124 is a punch-through structure of the first conductivity type, and 125 is an auxiliary depletion body region of the first conductivity type. Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Traditional SGT-MOSFET power devices are vertical devices. This invention, based on the traditional structure, adds a buried carrier layer on the substrate. Current can reach the lateral drain region through this buried layer, thus transforming the device into a lateral device, facilitating integration with lateral integration technology. The dual-channel structure design significantly reduces on-resistance and conduction losses. Furthermore, to further increase the device's breakdown voltage, a field plate structure is placed above the drift region, a buried layer structure is added within the drift region, and the length of the drift region is increased; all these measures can improve the device's breakdown voltage capability.

[0060] In the following embodiments, the oxide layer material can be a gate oxide layer or a high dielectric constant material.

[0061] The first gate electrode can be either metal or polycrystalline silicon.

[0062] The second gate electrode can be either metal or polycrystalline silicon.

[0063] The shielding gate electrode can be metal or polycrystalline silicon.

[0064] The potential of the shielded gate electrode is the same as that of the source electrode, or it is provided by a bias circuit.

[0065] The drain dielectric isolation layer can be silicon dioxide or other types of insulating materials. When the connection region is polycrystalline or heavily doped monocrystalline silicon, the drain dielectric isolation layer can be removed; when the connection region is metal, the drain dielectric isolation layer is necessary to isolate the metal from the monocrystalline silicon.

[0066] The first conductivity type is P-type doping, and the second conductivity type is N-type doping; or the first conductivity type is N-type doping, and the second conductivity type is P-type doping. The following embodiments are described with the first conductivity type being P-type doping and the second conductivity type being N-type doping.

[0067] Example 1

[0068] like Figure 1 As shown in Figures 2(a) and 2(b), this embodiment provides a lateral dual-channel SGT-MOSFET structure. Figure 1This is its layout structure. The structure of this embodiment is implemented on a first conductivity type substrate 101, including the first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first drift region 103 and a second conductivity type connection region 108 disposed above the second conductivity type buried layer 102; a second conductivity type drain region 107 disposed above the second conductivity type connection region 108; a first conductivity type body region 104 and a trench region disposed above the first drift region 103 of the second conductivity type.

[0069] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction.

[0070] A second drift region 120 of the second conductivity type is disposed above the first drift region 103 of the second conductivity type, and the second drift region 120 of the second conductivity type is located between the body region 104 of the first conductivity type and the connection region 108 of the second conductivity type; a second gate oxide layer 112 is disposed above the body region 104 of the first conductivity type and above a portion of the second drift region 120 of the second conductivity type, and a second gate electrode 110 is disposed above the second gate oxide layer 112; a metal silicide barrier layer 116 is disposed above the second drift region 120 of the second conductivity type and above a portion of the second gate electrode 110, and a source field plate electrode 118 is disposed above the metal silicide barrier layer 116; a source electrode metal 117 is disposed above the source region 105 of the second conductivity type and the contact region 106 of the first conductivity type, and a drain electrode metal 119 is disposed above the drain region 107 of the second conductivity type.

[0071] The map uses a square cellular structure design, such as... Figure 1 As shown, the second conductivity type source region 105 and the first conductivity type contact region 106 are designed to be arranged in an alternating pattern, which can achieve a smaller cell volume under advanced processes.

[0072] This embodiment achieves the integrability of the SGT-MOSFET device by setting a second conductivity type buried layer 102 and a second conductivity type connection region 108. Two channels are introduced by setting a first gate electrode 109 and a second gate electrode 110. This dual-channel structure can bring a larger on-state current and further reduce the on-resistance of the device. A shielded gate electrode 111 is set to reduce the gate drain capacitance while assisting in the depletion of the first drift region 103 of the second conductivity type, increasing the doping concentration of the first drift region 103 of the second conductivity type and reducing the specific on-resistance. Simultaneously, the source field plate electrode 118 above the metal silicide barrier layer 116 is connected to the source region electrode metal 117, acting as a field plate and reducing the gate drain capacitance, while further reducing the specific on-resistance of the device.

[0073] Example 2

[0074] Figure 3 This is a layout of the structure in this embodiment, and the cross-section of the structure is shown in Figures 4(a) and 4(b). The difference between this embodiment and embodiment 1 is that the structure of embodiment 2 does not have a second drift region 120 of the second conductivity type, nor does it have a second gate electrode 110, a second gate oxide layer 112, a metal silicide barrier layer 116, or a source field plate electrode 118.

[0075] The system includes a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first conductivity type drift region 103 and a second conductivity type connection region 108 disposed above the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed above the second conductivity type connection region 108, and a first conductivity type body region 104 and a trench region disposed above the first conductivity type drift region 103.

[0076] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. An insulating dielectric layer 114 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction.

[0077] A source region electrode metal 117 is disposed above the second conductivity type source region 105 and the first conductivity type contact region 106, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0078] In this embodiment, a single-channel structure design is adopted, so the distance between the first conductivity type body region 104 and the second conductivity type connection region 108 is small; at the same time, under advanced process, the second conductivity type source region 105 and the first conductivity type contact region 106 are designed to be arranged in an intermittent manner in the width direction, which further reduces the cell size of the device.

[0079] Example 3

[0080] The layout of this embodiment is the same as that of embodiment 1. Figure 1 Like Figure 1 As shown, its cross-section is shown in Figures 5(a) and 5(b). The difference from Embodiment 1 is that a first conductivity type buried layer 121 is provided below the second drift region 120 of the second conductivity type.

[0081] In this embodiment, the first conductivity type buried layer 121 and the second conductivity type second drift region 120 mutually deplete each other, thereby transforming the one-dimensional depletion of the electric field in the second drift region 120 of the second conductivity type into two-dimensional depletion, and increasing the doping concentration of the second drift region 120 of the second conductivity type to further reduce the specific on-resistance.

[0082] Example 4

[0083] The cross-sections are shown in Figures 7(a) and 7(b). Figure 6 It is its layout structure, which is a high voltage structure, including a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a second conductivity type first drift region 103 and a connection region 122 disposed above the second conductivity type buried layer 102, the bottom of the connection region 122 being tangent to the second conductivity type buried layer 102, and a first conductivity type body region 104, a second conductivity type second drift region 120 and a trench region disposed on the surface of the second conductivity type first drift region 103;

[0084] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first conductivity type contact region 106 and a second conductivity type source region 105 are provided above the surface of the first conductivity type body region 104, and the two are arranged alternately in the width direction. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, and the first conductivity type contact region 106.

[0085] The second drift region 120 of the second conductivity type is located between the body region 104 and the connection region 122 of the first conductivity type; the drain region 107 of the second conductivity type is located on the upper right side inside the second drift region 120 of the second conductivity type, and the right surface of the drain region 107 is tangent to the drain dielectric isolation layer 123; a source electrode metal 117 is disposed above the contact region 106 of the first conductivity type and the source region 105 of the second conductivity type; a second gate oxide layer 112 is disposed above the body region 104 of the first conductivity type and the portion above the second drift region 120 of the second conductivity type. A second gate electrode 110 is disposed above the silicide layer 112; a metal silicide barrier layer 116 is disposed above the second drift region 120 of the second conductivity type and above a portion of the second gate electrode 110, and a source field plate electrode 118 is disposed above the metal silicide barrier layer 116; a drain electrode metal 119 is disposed above the drain region 107 of the second conductivity type and the connection region 122; a drain dielectric isolation layer 123 is disposed between the second drift region 120 of the second conductivity type, the first drift region 103 of the second conductivity type, the drain region 107 of the second conductivity type and the connection region 122.

[0086] This invention addresses the high-voltage extension of lateral devices. The device's withstand voltage is divided into depletion between the lateral first conductivity type body region 104 and the second conductivity type second drift region 120, and depletion between the longitudinal first conductivity type body region 104 and the second conductivity type first drift region 103. Increasing the length of the drift region longitudinally while simultaneously increasing the depth of the shielding gate electrode 111 provides auxiliary depletion. The potential of the shielding gate electrode 111 can be the same as the source region electrode metal 117 or provided by other power supply biases. This enhances the withstand voltage capability of the second conductivity type first drift region 103, helping to reduce the overall device's specific on-resistance. The high voltage rating of this device primarily depends on the length of the second conductivity type second drift region 120 and the trench depth. Furthermore, the connection region 122 can be polysilicon, metal, or heavily doped silicon of the second conductivity type.

[0087] Example 5

[0088] The layout of this embodiment and the layout of embodiment 4 Figure 1 Like Figure 6As shown in Figures 8(a) and 8(b), the cross-section of this embodiment differs from that of Embodiment 4 in that a first conductivity type buried layer 121 is disposed below the second drift region 120 of the second conductivity type. The first conductivity type buried layer 121 and the second drift region 120 of the second conductivity type mutually deplete each other, which helps to increase the doping concentration of the second drift region 120 of the second conductivity type and reduce the specific on-resistance. At the same time, the first conductivity type buried layer 121 can also participate in the depletion of the first drift region 103 of the second conductivity type, avoiding premature breakdown caused by the uneven electric field distribution between the first drift region 103 of the second conductivity type and the first conductivity type body region 104.

[0089] Example 6

[0090] This embodiment is a source-region-centric structure designed for device architecture. Figure 9 It is its layout structure, the cross-section of the device, such as Figure 10 As shown. It includes a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first conductivity type drift region 103 and a second conductivity type connection region 108 located on both sides of the first conductivity type drift region 103 disposed above the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed on the surface of the second conductivity type connection region 108, a first conductivity type body region 104 and trench regions on both sides of the first conductivity type body region 104 disposed above the second conductivity type drift region 103;

[0091] The trench region is tangent to the second conductivity type connection region 108. The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the first conductivity type body region 104, the second conductivity type source region 105, the first conductivity type contact region 106, the second conductivity type connection region 108, and the second conductivity type drain region 107.

[0092] Above the first conductive type body region 104 are a second conductive type source region 105 and a first conductive type contact region 106, which are arranged alternately in the width direction. A drain region electrode metal 119 is provided above the second conductive type drain region 107, and a source region electrode metal 117 is provided above the second conductive type source region 105 and the first conductive type contact region 106.

[0093] For grid cell design, in a source-centric design, the second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction. Compared to the drain-centric layout, this source-centric design avoids the breakdown effect caused by current accumulation in the drain region, and the dual-channel design effectively reduces the on-resistance of the device. In this technical solution, the second conductivity type connection region 108 and the first gate oxide layer 113 can be tangent, or, depending on the voltage expansion requirements, a first drift region 103 of the second conductivity type can be added between them to bear the withstand voltage.

[0094] Example 7

[0095] This embodiment is an SGT-MOSFET short-channel structure, and its layout structure is as follows: Figure 11 As shown, its cross-section is as follows Figure 12 As shown, it includes a first conductivity type substrate 101, a second conductivity type buried layer 102 is disposed on the first conductivity type substrate 101, a first drift region 103 and a second conductivity type connection region 108 of the second conductivity type are disposed on the second conductivity type buried layer 102, a second conductivity type drain region 107 is disposed above the second conductivity type connection region 108, and a trench region is disposed on the surface area of ​​the first drift region 103 of the second conductivity type.

[0096] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0097] The power semiconductor device includes a second conductivity type source region 105. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is partially included by a first conductivity type contact region 106. The depth of the first conductivity type contact region 106 is greater than the depth of the second conductivity type source region 105, and the depth of the first conductivity type contact region 106 is consistent with the depth of the first conductivity type body region 104. A source region electrode metal 117 is disposed above a portion of the second conductivity type source region 105 and a portion of the first conductivity type contact region 106, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0098] The first conductivity type body region 104 is a continuous region, so the channel formed when the device is turned on is also continuous. Due to the presence of the control gate 109 and the first conductivity type contact region 106, a local JFET region is formed. When the device is turned on, the channel in the first conductivity type body region 104 is protected by this local JFET. The parasitic JFET region improves the channel's punch-through resistance and is beneficial for reducing the channel length.

[0099] Example 8

[0100] The device layout structure of this embodiment is as follows: Figure 13 As shown, the cross-sections are shown in Figures 14(a) and 14(b).

[0101] It includes a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first drift region 103 and a second conductivity type connection region 108 of the second conductivity type disposed on the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed above the second conductivity type connection region 108, and a trench region disposed on the surface area of ​​the first drift region 103 of the second conductivity type.

[0102] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0103] A source region electrode metal 117 is disposed above a portion of the second conductivity type source region 105, a portion of the first conductivity type anti-penetration structure 124, and a portion of the first conductivity type body region 104, and a drain region electrode metal 119 is disposed above the second conductivity type drain region 107.

[0104] A first conductivity type body region 104 is disposed above the first drift region 103 of the second conductivity type. A second conductivity type source region 105 and a first conductivity type contact region 106 are disposed above the first conductivity type body region 104, both of which are tangent to the side surface of the first gate oxide layer 113. The second conductivity type source region 105 and the first conductivity type contact region 106 are alternately distributed in the width direction. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is blocked by the first conductivity type anti-penetration structure 124. The structure includes a first conductivity type anti-penetration structure 124 disposed below the second conductivity type source region 105, and the first conductivity type body region 104 is formed between the first conductivity type anti-penetration structure 124 and the first gate oxide layer 113; the first conductivity type body region 104 is formed between the side of the first conductivity type anti-penetration structure 124 near the second conductivity type connection region 108 and the first drift region 103 of the second conductivity type; and a first conductivity type anti-penetration structure 124 in contact with the first gate oxide layer 113 is disposed below the first conductivity type contact region 106.

[0105] The first conductivity type punch-through structure 124 is disposed around the channel, so the channel in this embodiment is discontinuous in the width direction. Due to the presence of the first conductivity type punch-through structure 124, local JFET regions are introduced in the width direction, including JFET structures parallel to the first gate oxide layer 113 and JFET structures perpendicular to the gate oxide layer. When the device is turned on, the potential near the channel is fixed, improving the punch-through capability of the device channel, which is beneficial for further reducing the channel length and improving the device's SOA.

[0106] Example 9

[0107] The layout structure of this embodiment is as follows: Figure 15 As shown in Figures 16(a) and 16(b), the cross-sections are shown. The system includes a first conductivity type substrate 101, a second conductivity type buried layer 102 disposed on the first conductivity type substrate 101, a first drift region 103 and a second conductivity type connection region 108 disposed on the second conductivity type buried layer 102, a second conductivity type drain region 107 disposed above the second conductivity type connection region 108, a drain region electrode metal 119 disposed above the second conductivity type drain region 107, and a trench region disposed on the surface region of the first drift region 103 of the second conductivity type.

[0108] The trench region is provided with a shielding gate electrode 111 and a first gate electrode 109 from bottom to top. A field oxide layer 115 is provided between the shielding gate electrode 111 and the first drift region 103 of the second conductivity type. The shielding gate electrode 111 and the first gate electrode 109 are separated by an insulating dielectric layer 114. A first gate oxide layer 113 is provided between the first gate electrode 109 and the second conductivity type source region 105 and the first conductivity type body region 104. The second conductivity type source region 105 is located on the surface of the first conductivity type body region 104, and the side of the second conductivity type source region 105 is tangent to the first gate oxide layer 113.

[0109] A first conductivity type body region 104 is disposed above the second conductivity type drift region 103. A second conductivity type source region 105 and a first conductivity type contact region 106 are disposed above the first conductivity type body region 104, and the two are arranged alternately in the width direction. A first conductivity type auxiliary depletion body region 125 is disposed on the side of the first conductivity type body region 104 away from the first gate oxide layer 113. The depth of the first conductivity type auxiliary depletion body region 125 is deeper than that of the first conductivity type body region 104, and the doping concentration is the same as that of the first conductivity type body region 104. On the side of the second conductivity type source region 105 away from the first gate oxide layer 113, the second conductivity type source region 105 is partially contained by the first conductivity type auxiliary depletion body region 125. On the side away from the first gate oxide layer 113, the first conductivity type contact region 106 is partially contained by the first conductivity type auxiliary depletion body region 125. A source region electrode metal 117 is disposed above the second conductivity type source region 105 and the first conductivity type contact region 106.

[0110] In this technical solution, when the device is turned on, current flows through the surface of the first conductivity type body region 104 near the first gate oxide layer 113 and enters the first drift region 103 of the second conductivity type. However, as the channel size decreases and the drain voltage increases, the effective channel length of the device is modulated, exhibiting a short-channel effect. By providing an auxiliary depletion body region 125 of the first conductivity type at the channel outlet to assist in depletion, and by providing doped impurities of the opposite conductivity type to assist in depletion of the first drift region 103 of the second conductivity type, the depletion of the first conductivity type body region 104 is reduced, thereby improving the short-channel effect.

[0111] As a preferred approach, the potential of the shielded gate electrode can be connected to zero or provided by a bias circuit.

[0112] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power semiconductor device, characterized in that: The system includes a first conductivity type substrate (101), a second conductivity type buried layer (102) disposed on the first conductivity type substrate (101), a first drift region (103) of the second conductivity type and a second conductivity type connection region (108) disposed above the second conductivity type buried layer (102); a second conductivity type drain region (107) disposed above the second conductivity type connection region (108); and a first conductivity type body region (104) and a trench region disposed above the first drift region (103) of the second conductivity type. The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first gate oxide layer (113) is provided between the first gate electrode (109) and the first conductivity type body region (104), the second conductivity type source region (105), and the first conductivity type contact region (106). The second conductivity type source region (105) and the first conductivity type contact region (106) are alternately distributed in the width direction. A second drift region (120) of the second conductivity type is disposed above the first drift region (103) of the second conductivity type. The second drift region (120) of the second conductivity type is located between the body region (104) of the first conductivity type and the connection region (108) of the second conductivity type. A second gate oxide layer (112) is disposed above the body region (104) of the first conductivity type and above a portion of the second drift region (120) of the second conductivity type. A second gate electrode (110) is disposed above the second gate oxide layer (112). A metal silicide barrier layer (116) is disposed above the second drift region (120) of the second conductivity type and above a portion of the second gate electrode (110). A source field plate electrode (118) is disposed above the metal silicide barrier layer (116). A source electrode metal (117) is disposed above the source region (105) of the second conductivity type and the contact region (106) of the first conductivity type. A drain electrode metal (119) is disposed above the drain region (107) of the second conductivity type.

2. The power semiconductor device according to claim 1, characterized in that: A first conductivity type buried layer (121) is provided below the second drift region (120) of the second conductivity type.

3. A power semiconductor device, characterized in that: The system includes a first conductivity type substrate (101), a second conductivity type buried layer (102) disposed on the first conductivity type substrate (101), a first drift region (103) of the second conductivity type and a second conductivity type connection region (108) disposed above the second conductivity type buried layer (102); a second conductivity type drain region (107) disposed above the second conductivity type connection region (108); and a first conductivity type body region (104) and a trench region disposed above the first drift region (103) of the second conductivity type. The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). An insulating dielectric layer (114) is provided between the first gate electrode (109) and the first conductivity type body region (104), the second conductivity type source region (105), and the first conductivity type contact region (106). The second conductivity type source region (105) and the first conductivity type contact region (106) are alternately distributed in the width direction. A source region electrode metal (117) is disposed above the second conductivity type source region (105) and the first conductivity type contact region (106), and a drain region electrode metal (119) is disposed above the second conductivity type drain region (107).

4. A power semiconductor device, characterized in that: The substrate includes a first conductivity type substrate (101), a second conductivity type buried layer (102) is disposed on the first conductivity type substrate (101), a second conductivity type first drift region (103) and a connection region (122) are disposed above the second conductivity type buried layer (102), the bottom of the connection region (122) is tangent to the second conductivity type buried layer (102), and a first conductivity type body region (104), a second conductivity type second drift region (120) and a trench region are disposed on the surface of the second conductivity type first drift region (103); The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first conductivity type contact region (106) and a second conductivity type source region (105) are provided above the surface of the first conductivity type body region (104), and the two are arranged alternately in the width direction. A first gate oxide layer (113) is provided between the first gate electrode (109) and the first conductivity type body region (104), the second conductivity type source region (105), and the first conductivity type contact region (106). The second drift region (120) of the second conductivity type is located between the body region (104) and the connection region (122) of the first conductivity type; the drain region (107) of the second conductivity type is located on the upper right side inside the second drift region (120) of the second conductivity type, and the right surface of the drain region (107) of the second conductivity type is tangent to the drain dielectric isolation layer (123); a source electrode metal (117) is provided above the contact region (106) of the first conductivity type and the source region (105) of the second conductivity type; a second gate oxide layer (112) is provided above the body region (104) of the first conductivity type and the portion above the second drift region (120) of the second conductivity type. A second gate electrode (110) is provided above (112); a metal silicide barrier layer (116) is provided above the second drift region (120) of the second conductivity type and above the second gate electrode (110); a source field plate electrode (118) is provided above the metal silicide barrier layer (116); a drain electrode metal (119) is provided above the drain region (107) and the connection region (122) of the second conductivity type; a drain dielectric isolation layer (123) is provided between the second drift region (120), the first drift region (103), and the drain region (107) of the second conductivity type and the connection region (122).

5. The power semiconductor device according to claim 4, characterized in that: A first conductivity type buried layer (121) is provided below the second drift region (120) of the second conductivity type.

6. A power semiconductor device, characterized in that: The substrate includes a first conductivity type substrate (101), a second conductivity type buried layer (102) is disposed on the first conductivity type substrate (101), a first drift region (103) of the second conductivity type and a second conductivity type connection region (108) located on both sides of the first drift region (103) of the second conductivity type are disposed above the second conductivity type buried layer (102), a second conductivity type drain region (107) is disposed on the surface of the second conductivity type connection region (108), and a first conductivity type body region (104) and trench regions on both sides of the first conductivity type body region (104) are disposed above the second conductivity type drift region (103). The trench region is tangent to the second conductivity type connection region (108). The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first gate oxide layer (113) is provided between the first gate electrode (109) and the first conductivity type body region (104), the second conductivity type source region (105), the first conductivity type contact region (106), the second conductivity type connection region (108), and the second conductivity type drain region (107). Above the first conductive type body region (104) are a second conductive type source region (105) and a first conductive type contact region (106), which are arranged alternately in the width direction. Above the second conductive type drain region (107) is a drain region electrode metal (119), and above the second conductive type source region (105) and the first conductive type contact region (106) is a source region electrode metal (117).

7. A power semiconductor device, characterized in that: The substrate includes a first conductivity type substrate (101), a second conductivity type buried layer (102) is disposed on the first conductivity type substrate (101), a first drift region (103) and a second conductivity type connection region (108) of the second conductivity type are disposed on the second conductivity type buried layer (102), a second conductivity type drain region (107) is disposed above the second conductivity type connection region (108), and a trench region is disposed on the surface area of ​​the first drift region (103) of the second conductivity type. The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first gate oxide layer (113) is provided between the first gate electrode (109) and the second conductivity type source region (105) and the first conductivity type body region (104). The second conductivity type source region (105) is located on the surface of the first conductivity type body region (104), and the side of the second conductivity type source region (105) is tangent to the first gate oxide layer (113). The power semiconductor device includes a second conductivity type source region (105). On the side of the second conductivity type source region (105) away from the first gate oxide layer (113), the second conductivity type source region (105) is partially included by a first conductivity type contact region (106). The depth of the first conductivity type contact region (106) is greater than the depth of the second conductivity type source region (105), and the depth of the first conductivity type contact region (106) is consistent with the depth of the first conductivity type body region (104). A source region electrode metal (117) is disposed above a portion of the second conductivity type source region (105) and a portion of the first conductivity type contact region (106), and a drain region electrode metal (119) is disposed above the second conductivity type drain region (107).

8. A power semiconductor device, characterized in that: The substrate includes a first conductivity type substrate (101), a second conductivity type buried layer (102) is disposed on the first conductivity type substrate (101), a first drift region (103) and a second conductivity type connection region (108) of the second conductivity type are disposed on the second conductivity type buried layer (102), a second conductivity type drain region (107) is disposed above the second conductivity type connection region (108), and a trench region is disposed on the surface area of ​​the first drift region (103) of the second conductivity type. The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first gate oxide layer (113) is provided between the first gate electrode (109) and the second conductivity type source region (105) and the first conductivity type body region (104). The second conductivity type source region (105) is located on the surface of the first conductivity type body region (104), and the side of the second conductivity type source region (105) is tangent to the first gate oxide layer (113). A source region electrode metal (117) is provided above a portion of the second conductivity type source region (105), a portion of the first conductivity type anti-penetration structure (124), and a portion of the first conductivity type body region (104), and a drain region electrode metal (119) is provided above the second conductivity type drain region (107); A first conductivity type body region (104) is disposed above the first drift region (103) of the second conductivity type. A second conductivity type source region (105) and a first conductivity type contact region (106) are disposed above the first conductivity type body region (104). Both are tangent to the side of the first gate oxide layer (113), and the second conductivity type source region (105) and the first conductivity type contact region (106) are alternately distributed in the width direction. On the side of the second conductivity type source region (105) away from the first gate oxide layer (113), the second conductivity type source region (105) is blocked by the first conductivity type anti-penetration structure 124. The structure includes a first conductivity type anti-penetration structure (124) disposed below the second conductivity type source region (105), and the first conductivity type body region (104) is located between the first conductivity type anti-penetration structure (124) and the first gate oxide layer (113); the first conductivity type body region (104) is located between the side of the first conductivity type anti-penetration structure (124) near the second conductivity type connection region (108) and the first drift region (103) of the second conductivity type; and a first conductivity type anti-penetration structure (124) in contact with the first gate oxide layer (113) is disposed below the first conductivity type contact region (106).

9. A power semiconductor device, characterized in that: The substrate includes a first conductivity type substrate (101), a second conductivity type buried layer (102) is disposed on the first conductivity type substrate (101), a first drift region (103) and a second conductivity type connection region (108) of the second conductivity type are disposed on the second conductivity type buried layer (102), a second conductivity type drain region (107) is disposed above the second conductivity type connection region (108), a drain region electrode metal (119) is disposed above the second conductivity type drain region (107), and a trench region is disposed on the surface region of the first drift region (103) of the second conductivity type. The trench region is provided with a shielding gate electrode (111) and a first gate electrode (109) from bottom to top. A field oxide layer (115) is provided between the shielding gate electrode (111) and the first drift region (103) of the second conductivity type. The shielding gate electrode (111) and the first gate electrode (109) are separated by an insulating dielectric layer (114). A first gate oxide layer (113) is provided between the first gate electrode (109) and the second conductivity type source region (105) and the first conductivity type body region (104). The second conductivity type source region (105) is located on the surface of the first conductivity type body region (104), and the side of the second conductivity type source region (105) is tangent to the first gate oxide layer (113). A first conductivity type body region (104) is disposed above the second conductivity type drift region (103). A second conductivity type source region (105) and a first conductivity type contact region (106) are disposed above the first conductivity type body region (104), which are arranged alternately in the width direction. A first conductivity type auxiliary depletion body region (125) is disposed on the side of the first conductivity type body region (104) away from the gate first oxide layer (113). The depth of the first conductivity type auxiliary depletion body region (125) is deeper than that of the first conductivity type body region (104), and the doping concentration is higher. Similar to the first conductivity type body region (104); on the side of the second conductivity type source region (105) away from the first gate oxide layer (113), the second conductivity type source region (105) is partially included by the first conductivity type auxiliary depletion body region (125), and on the side away from the first gate oxide layer (113), the first conductivity type contact region (106) is partially included by the first conductivity type auxiliary depletion body region (125), and a source region electrode metal (117) is disposed above the second conductivity type source region (105) and the first conductivity type contact region (106).

10. The power semiconductor device according to any one of claims 1-9, characterized in that: The potential of the shielded gate electrode is connected to zero, or is provided by a bias circuit.

Images