Switched capacitor circuit and electronic device

Abstract

The embodiment of the application provides a kind of switched capacitor circuit SC and electronic equipment, it is related to electronic technical field, can freely switch multiple step-down ratio.The SC, the first end of first switch circuit is connected with power supply end, the first end of third capacitor is connected with the second end, the first end of first switch circuit is connected with the first end of second switch circuit and first capacitor, the first end of fourth capacitor is connected with the fourth end of first switch circuit, the first end of third switch circuit and the first end of fourth switch circuit;The second end of third capacitor is connected with the second end of second switch circuit, the third end of second switch circuit is connected with ground;The second end of second capacitor is connected with the second end of third switch circuit, the third end of third switch circuit is connected with ground, the second end of first capacitor is connected with the second end of fourth switch circuit, the third end of fourth switch circuit is connected with ground, the second end of fourth capacitor is connected with ground.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a switched capacitor circuit SC and an electronic device. Background Technology

[0002] Wired or wireless fast charging for mobile phones, watches, tablets, and other terminal devices involves the power adapter or wireless charging circuit outputting a voltage two (or four) times the battery voltage. This high voltage is then reduced to half (or a quarter) of the original voltage by a switched capacitor converter (SC) within the device to charge the battery. This high voltage reduces transmission current and line loss while maintaining the same power output. Furthermore, the SC's open-loop efficiency, combined with voltage or current regulation by the charging protocol control adapter or wireless charging circuit, makes the entire charging system highly efficient, reducing heat dissipation and achieving super-fast charging.

[0003] Typically, in the initial stage of fast charging, the charging protocol controls the adapter or wireless charging circuit to quickly charge the battery at a high charging power (e.g., 60W). At this time, the charging protocol controls the adapter or wireless charger to output a high voltage (e.g., 20V) to the charging station (SC). The SC operates in a 4:1 buck ratio, converting the 20V to 5V to charge the battery. When the battery voltage or capacity rises to a certain level, or when heat dissipation becomes excessive and the charging power drops, the adapter or wireless charger needs to switch to a lower charging power (e.g., 40W). The voltage output by the adapter or wireless charger to the SC will drop to around 10V. To maintain the original charging current and continue fast charging, the charging protocol controls the SC to use a 2:1 buck ratio to reduce the input 10V to around 5V to continue charging the battery. Of course, when the charging protocol controls the adapter or wireless charger to further reduce the voltage, it needs to control the SC to further switch to buck mode to ensure that the output voltage remains around 5V, thus ensuring the fast charging effect. Therefore, a corresponding SC that can freely switch between multiple buck ratios is needed. Summary of the Invention

[0004] Embodiments of this application provide a switched capacitor circuit (SC) and an electronic device capable of freely switching between multiple buck ratios.

[0005] In a first aspect, a switched capacitor circuit SC is provided, comprising: a first switching circuit, a second switching circuit, a third switching circuit, a fourth switching circuit, and a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; wherein, a first terminal of the first switching circuit is connected to a power supply terminal; a second terminal of the first switching circuit is connected to a first terminal of the third capacitor; a third terminal of the first switching circuit is connected to a first terminal of the second switching circuit and a first terminal of the first capacitor; a fourth terminal of the first switching circuit is connected to a first terminal of the second capacitor; and a fifth terminal of the first switching circuit is connected to a first terminal of the third switching circuit, a first terminal of the fourth switching circuit, and a first terminal of the fourth capacitor; the second terminal of the third capacitor is connected to... The second terminal of the second switching circuit is connected to ground; the second terminal of the second capacitor is connected to the second terminal of the third switching circuit, the third terminal of the third switching circuit is connected to ground; the second terminal of the first capacitor is connected to the second terminal of the fourth switching circuit, the third terminal of the fourth switching circuit is connected to ground; the second terminal of the fourth capacitor is connected to ground; in the first buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the third capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to the first terminal of the first capacitor; the third switching circuit is... The configuration is such that the second terminal of the second capacitor is connected to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the third capacitor to the first terminal of the second capacitor, and the first terminal of the first capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to ground; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground; in the second buck mode, the first switching circuit is configured... To connect the power supply terminal to the first terminal of the first capacitor, the first terminal of the second capacitor is connected to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the second capacitor to the power supply terminal, and the first terminal of the first capacitor is connected to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground.In the third buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the fourth capacitor.

[0006] In achieving the 4:1 buck conversion mode, during the first time interval of a time cycle, the first switching circuit connects the power supply terminal to the first terminal of the third capacitor Cfly3, and the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the second switching circuit connects the second terminal of the third capacitor Cfly3 to the first terminal of the first capacitor Cfly1; the second terminal of the second capacitor Cfly2 is connected to ground GND; and the fourth switching circuit connects the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. The third capacitor Cfly3, the first capacitor Cfly1, and the fourth capacitor Co form a series connection, with their two ends connected to the power supply terminal and the ground terminal GND, respectively. The second capacitor Cfly2 and the fourth capacitor Co are connected in parallel. Thus, when the system is stable: Vin = Vcfly3 + Vcfly1 + Vo, Vcfly2 = Vo; where Vcfly3 is the voltage across the third capacitor Cfly3, Vcfly1 is the voltage across the first capacitor Cfly1, and V0 is the voltage across the fourth capacitor Co. In the second time period of one cycle, the first switching circuit 31 connects the first terminal of the third capacitor Cfly3 to the first terminal of the second capacitor Cfly2, and connects the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. The second switching circuit 32 connects the second terminal of the third capacitor Cfly3 to ground GND. The third switching circuit 33 connects the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co. The fourth switching circuit connects the second terminal of the first capacitor Cfly1 to ground GND. The first capacitor Cfly1 and the fourth capacitor Co are connected in parallel, and the series connection of the second capacitor Cfly2 and the third capacitor Cfly3 is connected in parallel with the fourth capacitor Co. Thus, when the system is stable: Vcfly3 = Vcfly2 + Vo, where Vcfly2 is the voltage across the second capacitor Cfly2. In summary, Vin = 4Vo, Vcfly3 = 2Vo, Vcfly2 = Vo, and Vcfly1 = Vo, thereby achieving a 4:1 voltage ratio conversion.

[0007] In implementing the 2:1 buck mode, during the first time period of one cycle, the first switching circuit 31 connects the power supply terminal to the first terminal of the first capacitor Cfly1, and connects the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the third switching circuit connects the second terminal of the second capacitor Cfly2 to ground GND; and the fourth switching circuit 34 connects the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. The first capacitor Cfly1 and the fourth capacitor Co are connected in series between the power supply terminal and ground GND, and the second capacitor Cfly2 and the fourth capacitor Co are connected in parallel. Thus, when the system is stable: Vin = Vcfly1 + Vo, Vo = Cfly2. During the second time period of one cycle, the first switching circuit connects the power supply terminal to the first terminal of the second capacitor Cfly2, and connects the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co; the third switching circuit connects the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; and the fourth switching circuit connects the second terminal of the first capacitor Cfly1 to ground GND. In this system, the second capacitor Cfly2 and the fourth capacitor Co are connected in series between the power supply terminal and ground (GND), while the first capacitor Cfly1 and the fourth capacitor Co are connected in parallel. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly1 + Vo, Vo = Cfly2. In summary, we can obtain Vin = 2Vo, Vcfly2 = Vo, and Vcfly1 = Vo, thereby achieving a 2:1 voltage ratio conversion.

[0008] In the 1:1 buck conversion mode, the first switching circuit 31 connects the power supply terminal to the first terminal of the fourth capacitor Co, which is connected in series between the power supply terminal and ground GND. Thus, when the system is stable, Vin = Vo. This achieves a 1:1 voltage ratio conversion.

[0009] In summary, when the SC circuit operates in different buck modes, it achieves the output voltage across the fourth capacitor Co in ratios of 4:1, 2:1, and 1:1, respectively, thus enabling the switching of multiple buck ratios.

[0010] In one possible implementation, the first switching circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, a first terminal of the first switch is connected to a first terminal of the first switching circuit, a second terminal of the first switch is connected to a second terminal of the first switching circuit, a first terminal of the second switch is connected to a second terminal of the first switching circuit, a second terminal of the second switch is connected to a fourth terminal of the first switching circuit, a first terminal of the fourth switch is connected to a second terminal of the first switching circuit, a second terminal of the third switch is connected to a fourth terminal of the first switching circuit, a first terminal of the fifth switch is connected to a third terminal of the first switching circuit, and a second terminal of the fifth switch is connected to a fifth terminal of the first switching circuit. In the first buck mode, during a first time period within a cycle, the first and third switches are in the ON state, while the second and fifth switches are in the OFF state; during a second time period within a cycle, the first and third switches are in the OFF state, while the second and fifth switches are in the ON state; and during a cycle, the fourth switch is in the OFF state. In the second buck mode, during a first time period within a cycle, the third and fourth switches are in the ON state, while the second and fifth switches are in the OFF state; during a second time period within a cycle, the third and fourth switches are in the OFF state, while the second and fifth switches are in the ON state; during a cycle, the fourth switch is in the OFF state; and during a cycle, the first switch is in the ON state. In the third buck mode, the first, second, third, fourth, and fifth switches are all in the ON state.

[0011] In one possible implementation, the second switching circuit includes a sixth switch and a seventh switch; wherein a first terminal of the sixth switch is connected to a first terminal of the second switching circuit, a second terminal of the sixth switch is connected to a second terminal of the second switching circuit, a first terminal of the seventh switch is connected to a second terminal of the second switching circuit, and a second terminal of the seventh switch is connected to a third terminal of the second switching circuit; in a first buck mode, during a first time period within a cycle, the sixth switch is in a conducting state and the seventh switch is in a disconnected state; during a second time period within a cycle, the sixth switch is in a disconnected state and the seventh switch is in a conducting state; in a second buck mode, during a cycle, both the sixth and seventh switches are in a disconnected state; and in a third buck mode, both the sixth and seventh switches are in a disconnected state.

[0012] In one possible implementation, the third switching circuit includes an eighth switch and a ninth switch; wherein a first terminal of the eighth switch is connected to a first terminal of the third switching circuit, a second terminal of the eighth switch is connected to a second terminal of the third switching circuit, a first terminal of the ninth switch is connected to a second terminal of the third switching circuit, and a second terminal of the ninth switch is connected to a third terminal of the third switching circuit; in a first buck mode, during a first time period within a cycle, the ninth switch is in a conducting state and the eighth switch is in a de-energized state; during a second time period within a cycle, the ninth switch is in a de-energized state and the eighth switch is in a conducting state; in a second buck mode, during a first time period within a cycle, the ninth switch is in a conducting state and the eighth switch is in a de-energized state; during a second time period within a cycle, the ninth switch is in a de-energized state and the eighth switch is in a conducting state; in a third buck mode, both the eighth and ninth switches are in a de-energized state.

[0013] In one possible implementation, the fourth switching circuit includes a tenth switch and an eleventh switch, wherein a first terminal of the tenth switch is connected to a first terminal of the fourth switching circuit, a second terminal of the tenth switch is connected to a second terminal of the fourth switching circuit, a first terminal of the eleventh switch is connected to the second terminal of the fourth switching circuit, and a second terminal of the eleventh switch is connected to a third terminal of the fourth switching circuit. In a first buck mode, during a first time period within a cycle, the tenth switch is in a conducting state and the eleventh switch is in a disconnected state; during a second time period within a cycle, the tenth switch is in a disconnected state and the eleventh switch is in a conducting state; in a second buck mode, during the first time period within a cycle, the tenth switch is in a conducting state and the eleventh switch is in a disconnected state; during the second time period within a cycle, the tenth switch is in a disconnected state and the eleventh switch is in a conducting state; in a third buck mode, both the tenth and eleventh switches are in a disconnected state.

[0014] In the 4:1 buck mode, during the first time period of a cycle, switches 1, 6, and 10 are on, connecting capacitors 3, 1, and 4 in series to form one current path. Switches 3 and 9 are on, connecting capacitors 2 and 4 in series to form another current path, while the other switches are off. During the second time period of a cycle, switches 2, 7, and 8 are on, connecting capacitors 3, 2, and 4 in series to form one current path. Switches 5 and 9 are on, connecting capacitors 1 and 4 in series to form another current path, while the other switches are off. Thus, two current paths are formed in both time periods, ensuring that each on switch has only one current path. This results in a more even distribution of current loss across the switches, effectively improving the overall system efficiency of the SC.

[0015] In the 2:1 buck mode, during the first time period of a cycle, the first, fourth, and tenth switches are in the ON state, connecting the first and fourth capacitors in series to form one current path. The third and ninth switches are in the ON state, connecting the second and fourth capacitors in series to form another current path, while the other switches are OFF. During the second time period of the same cycle, the first, second, and eighth switches are in the ON state, connecting the second and fourth capacitors in series to form one current path. The fifth and eleventh switches are in the ON state, connecting the first and fourth capacitors in parallel to form another current path, while the other switches are OFF. Thus, two current paths are formed in both time periods, ensuring that each ON switch has only one current path. This results in a more even distribution of current loss across the switches, effectively improving the overall system efficiency of the SC. Furthermore, in the 2:1 buck mode, the first and fourth capacitors are connected in series in the first time period, and in the second time period, the first and second capacitors are connected in series, forming an interleaved parallel structure. This provides more current paths to the power supply, effectively reducing power consumption.

[0016] In the 1:1 buck mode, the first, second, and third switches are in the ON state, directly connecting the fourth capacitor to the power supply to form one current path; the first, fourth, and fifth switches are in the ON state, directly connecting the fourth capacitor to the power supply to form another current path. Since the current paths formed by the first, second, and third switches are connected in parallel with the current paths formed by the first, fourth, and fifth switches, the resistance on the charging path of the fourth circuit is reduced, which can effectively reduce power consumption and improve the efficiency of the SC.

[0017] In one possible implementation, each switch includes a single switching transistor, or each switch includes two or more switching transistors connected in parallel. The use of two or more switching transistors in parallel for each switch can reduce the resistance when the switch is on, thereby improving system efficiency.

[0018] Secondly, a chip is provided, comprising: a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit; wherein, a first terminal of the first switching circuit is connected to a power supply terminal; a second terminal of the first switching circuit is used to connect to a first terminal of a third capacitor; a third terminal of the first switching circuit is connected to a first terminal of the second switching circuit; a third terminal of the first switching circuit is also used to connect to a first terminal of the first capacitor; a fourth terminal of the first switching circuit is used to connect to a first terminal of the second capacitor; a fifth terminal of the first switching circuit is connected to the first terminals of the third and fourth switching circuits; and a fifth terminal of the first switching circuit is also used to connect to a first terminal of the fourth capacitor; the second terminal of the second switching circuit is used to connect to... The second terminal of the third capacitor is connected to ground; the second terminal of the third switching circuit is used to connect to the second terminal of the second capacitor, and the third terminal of the third switching circuit is connected to ground; the second terminal of the fourth switching circuit is used to connect to the second terminal of the first capacitor, and the third terminal of the fourth switching circuit is connected to ground; the second terminal of the fourth capacitor is connected to ground; in the first buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the third capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to the first terminal of the first capacitor; the third switching circuit is... The configuration is such that the second terminal of the second capacitor is connected to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the third capacitor to the first terminal of the second capacitor, and the first terminal of the first capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to ground; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground; in the second buck mode, the first switching circuit is configured... To connect the power supply terminal to the first terminal of the first capacitor, the first terminal of the second capacitor is connected to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the second capacitor to the power supply terminal, and the first terminal of the first capacitor is connected to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground.In the third buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the fourth capacitor.

[0019] In one possible implementation, the first switching circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, a first terminal of the first switch is connected to a first terminal of the first switching circuit, a second terminal of the first switch is connected to a second terminal of the first switching circuit, a first terminal of the second switch is connected to a second terminal of the first switching circuit, a second terminal of the second switch is connected to a fourth terminal of the first switching circuit, a first terminal of the fourth switch is connected to a second terminal of the first switching circuit, a second terminal of the fourth switch is connected to a third terminal of the first switching circuit, a first terminal of the third switch is connected to a fourth terminal of the first switching circuit, a second terminal of the third switch is connected to a fifth terminal of the first switching circuit, and a first terminal of the fifth switch is connected to a third terminal of the first switching circuit, and a second terminal of the fifth switch is connected to a fifth terminal of the first switching circuit; wherein, in the first buck mode, in one cycle In the first time period of a cycle, the first and third switches are in the ON state, and the second and fifth switches are in the OFF state; in the second time period of a cycle, the first and third switches are in the OFF state, and the second and fifth switches are in the ON state; in a cycle, the fourth switch is in the OFF state; in the second buck mode, in the first time period of a cycle, the third and fourth switches are in the ON state, and the second and fifth switches are in the OFF state; in the second time period of a cycle, the third and fourth switches are in the OFF state, and the second and fifth switches are in the ON state; in a cycle, the fourth switch is in the OFF state; in a cycle, the first switch is in the ON state; in the third buck mode, the first, second, third, fourth, and fifth switches are in the ON state.

[0020] In one possible implementation, the second switching circuit includes a sixth switch and a seventh switch; wherein a first terminal of the sixth switch is connected to a first terminal of the second switching circuit, a second terminal of the sixth switch is connected to a second terminal of the second switching circuit, a first terminal of the seventh switch is connected to a second terminal of the second switching circuit, and a second terminal of the seventh switch is connected to a third terminal of the second switching circuit; in a first buck mode, during a first time period within a cycle, the sixth switch is in a conducting state and the seventh switch is in a disconnected state; during a second time period within a cycle, the sixth switch is in a disconnected state and the seventh switch is in a conducting state; in a second buck mode, both the sixth and seventh switches are in a disconnected state; and in a third buck mode, both the sixth and seventh switches are in a disconnected state.

[0021] In one possible implementation, the third switching circuit includes an eighth switch and a ninth switch; wherein a first terminal of the eighth switch is connected to a first terminal of the third switching circuit, a second terminal of the eighth switch is connected to a second terminal of the third switching circuit, a first terminal of the ninth switch is connected to a second terminal of the third switching circuit, and a second terminal of the ninth switch is connected to a third terminal of the third switching circuit; in a first buck mode, during a first time period within a cycle, the ninth switch is in a conducting state and the eighth switch is in a de-energized state; during a second time period within a cycle, the ninth switch is in a de-energized state and the eighth switch is in a conducting state; in a second buck mode, during a first time period within a cycle, the ninth switch is in a conducting state and the eighth switch is in a de-energized state; during a second time period within a cycle, the ninth switch is in a de-energized state and the eighth switch is in a conducting state; in a third buck mode, both the eighth and ninth switches are in a de-energized state.

[0022] In one possible implementation, the fourth switching circuit includes a tenth switch and an eleventh switch, wherein a first terminal of the tenth switch is connected to a first terminal of the fourth switching circuit, a second terminal of the tenth switch is connected to a second terminal of the fourth switching circuit, a first terminal of the eleventh switch is connected to a second terminal of the fourth switching circuit, and a second terminal of the eleventh switch is connected to a third terminal of the fourth switching circuit; in a first buck mode, during a first time period within a cycle, the tenth switch is in a conducting state and the eleventh switch is in a disconnected state; during a second time period within a cycle, the tenth switch is in a disconnected state and the eleventh switch is in a conducting state; in a second buck mode, during a first time period within a cycle, the tenth switch is in a conducting state and the eleventh switch is in a disconnected state; during a second time period within a cycle, the tenth switch is in a disconnected state and the eleventh switch is in a conducting state; in a third buck mode, both the tenth and eleventh switches are in a disconnected state.

[0023] In one possible implementation, each switch includes a single switching transistor, or each switch includes two or more switching transistors connected in parallel.

[0024] The technical effects achieved in the second aspect can be referred to the description in the first aspect or any possible implementation method, and will not be repeated here.

[0025] Thirdly, an electronic device is provided, comprising an SC as described in the first aspect or any possible implementation thereof, or comprising a chip as described in the second aspect or any possible implementation thereof.

[0026] The technical effects achieved by the third aspect can be referred to the description in the first aspect or any possible implementation method, and will not be repeated here.

[0027] In one possible implementation, a wireless charging coil, a receiving circuit, and a battery are also included; the wireless charging coil is connected to the receiving circuit, the receiving circuit is connected to the power supply terminal of the SC or the chip, and the battery is connected in parallel with the fourth capacitor. This achieves a wireless charging method.

[0028] In one possible implementation, a USB interface and a battery are also included; the USB interface is connected to the power supply terminal of the SC or the chip, and the battery is connected in parallel with the fourth capacitor. This achieves a wired charging method.

[0029] In one possible implementation, an overvoltage protection circuit is further provided between the USB interface and the power supply terminal of the SC or the chip. This overvoltage protection circuit is used to disconnect the power supply terminal of the SC or the chip from the USB interface when it detects that the voltage connected to the USB interface exceeds a threshold voltage. This prevents damage to the SC circuit, the chip, or the battery caused by excessively high voltage received by the USB interface. Attached Figure Description

[0030] Figure 1 A schematic diagram of the structure of an electronic device provided for an embodiment of this application; Figure 2 A schematic diagram of the connection relationship of an SC provided for an embodiment of this application; Figure 3 A schematic diagram of the structure of an SC provided for an embodiment of this application; Figure 4 An equivalent circuit of an SC is provided for an embodiment of this application; Figure 5 An equivalent circuit 2 for an SC provided for an embodiment of this application; Figure 6 An equivalent circuit three for an SC provided for embodiments of this application; Figure 7 An equivalent circuit four for an SC provided for embodiments of this application; Figure 8 An equivalent circuit five for an SC provided for embodiments of this application; Figure 9 A schematic diagram of the structure of an SC is provided for another embodiment of this application; Figure 10 A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 1 : Figure 11 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 1 ; Figure 12 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 2 ; Figure 13 A schematic diagram of the structure of an SC is provided for another embodiment of this application; Figure 14 A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 2 : Figure 15 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 3 ; Figure 16 An equivalent circuit of an SC is provided for embodiments of this application; Figure 17 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 4 ; Figure 18 An equivalent circuit seven for an SC is provided for embodiments of this application; Figure 19 A schematic diagram of the structure of an SC provided for yet another embodiment of this application; Figure 20 A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 3 : Figure 21 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 5 ; Figure 22 An equivalent circuit of an SC is provided for embodiments of this application; Figure 23 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 6 ; Figure 24 An equivalent circuit nine for an SC provided for embodiments of this application; Figure 25 A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 4 : Figure 26 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 7 ; Figure 27 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 8 ; Figure 28 A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 5 : Figure 29 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 9 ; Figure 30 An equivalent circuit of an SC is provided for embodiments of this application; Figure 31 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 ; Figure 32 An equivalent circuit eleven for an embodiment of this application of the SC; Figure 33A schematic diagram of control signals for various switches of an SC provided for embodiments of this application. Figure 6 : Figure 34 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 one; Figure 35 An equivalent circuit twelve for an SC is provided for embodiments of this application; Figure 36 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 two; Figure 37 An equivalent circuit thirteen for an embodiment of this application is provided; Figure 38 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 three; Figure 39 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 Four; Figure 40 A schematic diagram of the current flow of an SC provided for an embodiment of this application. Figure 10 five; Figure 41 This is a schematic diagram of a chip structure provided for an embodiment of this application. Detailed Implementation

[0031] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "multiple" means two or more. Furthermore, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0034] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0035] The SC provided in this application embodiment can be applied to electronic devices such as mobile phones, tablets, laptops, ultra-mobile personal computers (UMPCs), handheld computers, netbooks, personal digital assistants (PDAs), wearable electronic devices, and virtual reality devices. This application embodiment does not impose any limitations on this.

[0036] For example, Figure 1 A schematic diagram of the structure of the electronic device 100 is shown.

[0037] Electronic device 100 may include processor 110, external memory interface 120, internal memory 121, universal serial bus (USB) interface 130, charging management module 140, power management module 141, battery 142, antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, sensor module 180, camera 193, and display screen 194, etc.

[0038] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0039] Processor 110 may include one or more processing units, such as application processors (APs), modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.

[0040] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0041] In some embodiments, the processor 110 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0042] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger (or adapter). In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141. Specifically, refer to... Figure 2 As shown, the charging management module 140 can be connected to the USB interface 130 via an overvoltage protection (OVP) circuit 131. When the OVP circuit 131 detects that the voltage connected to the USB interface 130 is too high (exceeding the threshold voltage), it can actively disconnect the charging management module 140 from the USB interface 130. For example, refer to... Figure 2 As shown, the charging management module 140 is specifically connected to the wireless charging coil 132 via a receive integrated circuit (Rx IC) 133. Furthermore, to achieve normal or fast charging of the battery, refer to... Figure 2As shown, the charging management module 140 may include a SC (Supercharger) for fast charging the battery and a buck converter circuit (e.g., BUCK) for normal charging. The SC and BUCK are connected to the USB interface 130 via an OVP (Over-Power Protection) circuit 131 and to the wireless charging coil 132 via an Rx IC 133. The processor 110 or the charging management module 140 can detect the BUCK or SC to charge the battery according to the charging protocol. Typically, the SC and BUCK are buck converter circuits with a fixed buck ratio. For example, if the voltage on the input side of the SC and BUCK is detected to be 5V according to the charging protocol, the BUCK is controlled to convert the 5V voltage to a voltage slightly higher than the battery voltage (2V) to charge the battery. Alternatively, if the voltage on the input side of the SC and BUCK is detected to be 20V according to the charging protocol, it is determined that this is a fast charging scenario, and the SC is controlled to convert the 20V voltage to a voltage near the battery voltage to charge the battery. Of course, when the battery voltage or capacity rises to a certain level, or when the heat dissipation is too high and the charging power is too strong, the adapter or wireless charger needs to switch to a lower charging power (e.g., 40W). The voltage output by the adapter or wireless charger to the SC will drop to around 10V. At this time, in order to maintain the original charging current and keep fast charging going, the charging protocol will control the SC to use a 2:1 buck mode to reduce the input 10V voltage to around 5V to continue charging the battery. Of course, when the charging protocol controls the adapter or wireless charger to further reduce the voltage, it needs to control the SC to switch to a buck mode further to ensure that the output voltage is maintained at around 5V, thereby ensuring the fast charging effect. The following example mainly describes the specific structure of the SC.

[0043] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, providing power to the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. The power management module 141 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.

[0044] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.

[0045] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be multiplexed to improve antenna utilization. For example, antenna 1 can be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas can be used in conjunction with tuning switches.

[0046] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 150 may include one or more filters, switches, power amplifiers, low-noise amplifiers (LNAs), etc. The mobile communication module 150 can receive electromagnetic waves via the antenna 1, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via the antenna 1. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be housed in the same device.

[0047] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs sound signals through an audio device (not limited to speaker 170A, receiver 170B, etc.) or displays images or videos through the display screen 194. In some embodiments, the modem processor may be a separate device. In other embodiments, the modem processor may be independent of the processor 110 and may be housed in the same device as the mobile communication module 150 or other functional modules.

[0048] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating one or more communication processing modules. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.

[0049] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, enabling electronic device 100 to communicate with networks and other devices via wireless communication technology. The wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Time Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. The GNSS may include the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Navigation Satellite System (BDS), the Quasi-Zenith Satellite System (QZSS), and / or satellite-based augmentation systems (SBAS).

[0050] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0051] Display screen 194 is used to display images, videos, etc. Display screen 194 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, electronic device 100 may include one or N displays 194, where N is a positive integer greater than 1.

[0052] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.

[0053] The ISP (Image Signal Processor) is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization of image noise, brightness, and skin tone. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.

[0054] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0055] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.

[0056] Internal memory 121 can be used to store one or more computer programs, which include instructions. Processor 110 can execute the instructions stored in internal memory 121, thereby causing electronic device 100 to perform the methods provided in some embodiments of this application, as well as various functional applications and data processing. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system; it may also store one or more applications (such as a gallery, contacts, etc.). The data storage area may store data created during the use of electronic device 101 (such as photos, contacts, etc.). Furthermore, internal memory 121 may include high-speed random access memory and non-volatile memory, such as one or more disk storage devices, flash memory devices, universal flash storage (UFS), etc. In other embodiments, processor 110 executes instructions stored in internal memory 121 and / or instructions stored in memory disposed within the processor, causing electronic device 100 to perform the methods provided in embodiments of this application, as well as various functional applications and data processing.

[0057] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.

[0058] The audio module 170 is used to convert digital audio information into analog audio signals for output, and also to convert analog audio input into digital audio signals. The audio module 170 can also be used for encoding and decoding audio signals. In some embodiments, the audio module 170 may be located in the processor 110, or some functional modules of the audio module 170 may be located in the processor 110.

[0059] The speaker 170A, also known as a "loudspeaker," is used to convert audio electrical signals into sound signals. The electronic device 100 can listen to music or make hands-free calls through the speaker 170A.

[0060] The receiver 170B, also known as the "earpiece," is used to convert audio electrical signals into sound signals. When the electronic device 100 answers a telephone call or voice message, the receiver 170B can be brought close to the ear to listen to the voice.

[0061] Microphone 170C, also known as a "microphone" or "voice transducer," is used to convert sound signals into electrical signals. When making a phone call or sending a voice message, the user can speak by bringing their mouth close to microphone 170C, inputting the sound signal into microphone 170C. Electronic device 100 may have one or more microphones 170C. In some embodiments, electronic device 100 may have two microphones 170C, which, in addition to collecting sound signals, can also perform noise reduction. In other embodiments, electronic device 100 may have three, four, or more microphones 170C, which can collect sound signals, reduce noise, identify the sound source, and perform directional recording, etc.

[0062] The 170D headphone jack is used to connect wired headphones. The 170D headphone jack can be a USB 130 interface or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, a CTIA (Cellular Telecommunications Industry Association of the USA) standard interface.

[0063] The sensor module 180 may include pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.

[0064] In addition, the above-mentioned electronic device may also include one or more components such as button 190, motor 191, indicator 192 and subscriber identification module (SIM) card interface 195, and this application embodiment does not impose any restrictions on this.

[0065] Based on the above-described electronic device, embodiments of this application provide an SC, with reference to... Figure 3As shown, it includes: a first switch circuit 31, a second switch circuit 32, a third switch circuit 33, a fourth switch circuit 34, and a first capacitor Cfly1, a second capacitor Cfly2, a third capacitor Cfly3, and a fourth capacitor Co. The first terminal of the first switching circuit 31 is connected to the power supply terminal, which is connected to a power adapter via a USB interface or to a wireless charging circuit to provide input voltage Vin to the Sc. The second terminal of the first switching circuit 31 is connected to the first terminal of the third capacitor Cfly3. The third terminal of the first switching circuit 31 is connected to the first terminal of the second switching circuit 32 and the first terminal of the first capacitor fly1. The fourth terminal of the first switching circuit 31 is connected to the first terminal of the second capacitor Cfly. The fifth terminal of the first switching circuit 31 is connected to the first terminal of the third switching circuit 33, the first terminal of the fourth switching circuit 33, and the first terminal of the fourth capacitor Co. The second terminal of the third capacitor Cfly3 is connected to the second terminal of the second switching circuit 32, and the third terminal of the second switching circuit 32 is connected to ground GND. The second terminal of the second capacitor Cfly2 is connected to the second terminal of the third switching circuit 33, and the third terminal of the third switching circuit 33 is connected to ground GND. The second terminal of the first capacitor Cfly1 is connected to the second terminal of the fourth switching circuit 34, and the third terminal of the fourth switching circuit 34 is connected to ground GND. The second terminal of the fourth capacitor Co is connected to ground GND. In this scheme, the first capacitor Cfly1, the second capacitor Cfly2, and the third capacitor Cfly3 are flying capacitors, and the fourth capacitor Co serves as the output capacitor. The voltage across its terminals provides a stable power supply voltage to the load RL (in the mobile phone scenario, the load refers to the battery).

[0066] In the first buck mode, the first switching circuit 31 is configured to connect the power supply terminal to the first terminal of the third capacitor Cfly3 and the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the second switching circuit 32 is configured to connect the second terminal of the third capacitor Cfly3 to the first terminal of the first capacitor Cfly1; the third switching circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to ground GND; and the fourth switching circuit 34 is configured to connect the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. Alternatively, the first switching circuit 31 is configured to connect the first terminal of the third capacitor Cfly3 to the first terminal of the second capacitor Cfly2, and connect the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co; the second switching circuit 32 is configured to connect the second terminal of the third capacitor Cfly3 to ground GND; the third switching circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; and the fourth switching circuit 34 is configured to connect the second terminal of the first capacitor Cfly1 to ground GND.

[0067] In the second buck mode, the first switching circuit 31 is configured to connect the power supply terminal to the first terminal of the first capacitor Cfly1, and the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the third switching circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to ground GND; and the fourth switching circuit 34 is configured to connect the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. Alternatively, the first switching circuit 31 is configured to connect the first terminal of the second capacitor Cfly2 to the power supply terminal, and the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co; the third switching circuit 33 is configured to connect the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; and the fourth switching circuit 34 is configured to connect the second terminal of the first capacitor Cfly1 to ground GND.

[0068] In the third buck mode, the first switching circuit 31 is configured to connect the power supply terminal to the first terminal of the fourth capacitor Co.

[0069] In this 4:1 buck mode, during the first time period of a time cycle, the first switching circuit 31 connects the power supply terminal to the first terminal of the third capacitor Cfly3, and connects the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the second switching circuit 32 connects the second terminal of the third capacitor Cfly3 to the first terminal of the first capacitor Cfly1; the third switching circuit 33 connects the second terminal of the second capacitor Cfly2 to ground GND; and the fourth switching circuit 34 connects the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co, thereby connecting the capacitors as follows: Figure 4 The equivalent circuit shown has the third capacitor Cfly3, the first capacitor Cfly1, and the fourth capacitor Co forming a series connection, with their ends connected to the power supply and ground GND, respectively. The second capacitor Cfly2 is connected in parallel with the fourth capacitor Co, and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly3 + Vcfly1 + Vo, Vcfly2 = Vo; where Vcfly3 is the voltage across the third capacitor Cfly3, Vcfly1 is the voltage across the first capacitor Cfly1, and V0 is the voltage across the fourth capacitor Co. In the second time period of one cycle, the first switching circuit 31 connects the first terminal of the third capacitor Cfly3 to the first terminal of the second capacitor Cfly2, and connects the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. The second switching circuit 32 connects the second terminal of the third capacitor Cfly3 to ground GND. The third switching circuit 33 connects the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co. The fourth switching circuit connects the second terminal of the first capacitor Cfly1 to ground GND, thereby connecting the capacitors as follows: Figure 5The equivalent circuit shown has the first capacitor Cfly1 connected in parallel with the fourth capacitor Co, and the series connection of the second capacitor Cfly2 and the third capacitor Cfly3 connected in parallel with the fourth capacitor Co. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vcfly3 = Vcfly2 + Vo, where Vcfly2 is the voltage across the second capacitor Cfly2. In summary, Vin = 4Vo, Vcfly3 = 2Vo, Vcfly2 = Vo, and Vcfly1 = Vo, thereby achieving a 4:1 voltage ratio transformation.

[0070] In implementing the 2:1 buck mode, during the first time period of one cycle, the first switching circuit 31 connects the power supply terminal to the first terminal of the first capacitor Cfly1, and connects the first terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; the third switching circuit 33 connects the second terminal of the second capacitor Cfly2 to ground GND; and the fourth switching circuit 34 connects the second terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co. This connects the capacitors as follows: Figure 6 The equivalent circuit shown has the following configuration: the first capacitor Cfly1 and the fourth capacitor Co are connected in series between the power supply terminal and ground GND; the second capacitor Cfly2 and the fourth capacitor Co are connected in parallel; and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly1 + Vo, Vo = Cfly2. During the second time interval of one cycle, the first switching circuit 31 connects the power supply terminal to the first terminal of the second capacitor Cfly2, and connects the first terminal of the first capacitor Cfly1 to the first terminal of the fourth capacitor Co; the third switching circuit 33 connects the second terminal of the second capacitor Cfly2 to the first terminal of the fourth capacitor Co; and the fourth switching circuit 34 connects the second terminal of the first capacitor Cfly1 to ground GND. This connects the capacitors as shown in the figure. Figure 7 The equivalent circuit shown has the second capacitor Cfly2 and the fourth capacitor Co connected in series between the power supply terminal and ground GND, and the first capacitor Cfly1 and the fourth capacitor Co connected in parallel. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly2 + Vo, Vo = Cfly1. In summary, we can obtain Vin = 2Vo, Vcfly2 = Vo, Vcfly1 = Vo, thereby achieving a 2:1 voltage ratio transformation.

[0071] In the 1:1 buck mode, the first switching circuit 31 connects the power supply terminal to the first terminal of the fourth capacitor Co, thereby connecting the capacitors as follows: Figure 8 The equivalent circuit shown has a fourth capacitor Co connected in series between the power supply terminal and ground GND, with the current flowing in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vo. This allows for a 1:1 voltage ratio conversion.

[0072] In summary, when the SC circuit operates in different buck modes, it achieves the output voltage across the fourth capacitor Co in ratios of 4:1, 2:1, and 1:1, respectively, thus enabling the switching of multiple buck ratios.

[0073] Combination Figure 9 As shown, the first switching circuit 31 includes switches Q1, Q2, Q3, Qadd, and Q8; wherein, the first end of switch Q1 is connected to the first end of the first switching circuit 31, the second end of switch Q1 is connected to the second end of the first switching circuit 31, the first end of switch Q2 is connected to the second end of the first switching circuit 31, the second end of switch Q2 is connected to the fourth end of the first switching circuit 31, the first end of switch Qadd is connected to the second end of the first switching circuit 31, the second end of switch Qadd is connected to the third end of the first switching circuit 31, the first end of switch Q3 is connected to the fourth end of the first switching circuit 31, the second end of switch Q3 is connected to the fifth end of the first switching circuit 31, and the first end of switch Q8 is connected to the third end of the first switching circuit 31, and the second end of switch Q8 is connected to the fifth end of the first switching circuit 31.

[0074] The second switching circuit 32 includes switches Q6 and Q7, wherein the first end of switch Q6 is connected to the first end of the second switching circuit 32, the second end of switch Q6 is connected to the second end of the second switching circuit 32, the first end of switch Q7 is connected to the second end of the second switching circuit 32, and the second end of switch Q7 is connected to the third end of the second switching circuit 32.

[0075] The third switching circuit 33 includes switches Q4 and Q5, wherein the first end of switch Q4 is connected to the first end of the third switching circuit 33, the second end of switch Q4 is connected to the second end of the third switching circuit 33, the first end of switch Q5 is connected to the second end of the third switching circuit 33, and the second end of switch Q5 is connected to the third end of the third switching circuit 33.

[0076] The fourth switching circuit 34 includes switches Q9 and Q10, wherein the first end of switch Q9 is connected to the first end of the fourth switching circuit 34, the second end of switch Q9 is connected to the second end of the fourth switching circuit 34, the first end of switch Q10 is connected to the second end of the fourth switching circuit 34, and the second end of switch Q10 is connected to the third end of the fourth switching circuit 34.

[0077] Among them, switches Q1-Q10 and Qadd all include control terminals. Under the control of these control terminals, the switches can switch their two ends between on and off states. Typically, the switches can be switching transistors (or simply switching tubes or transistors). In the embodiments of this application, the switching transistors can be metal-oxide-semiconductor field-effect transistors (MOSFETs). Furthermore, in... Figure 9 In the illustrated example, each switch is implemented using a single switching transistor. It can be understood that to reduce the resistance when the switch is on, each switch may also use two or more switching transistors connected in parallel. In the embodiments of this application, the switching transistors are divided into two types: N-type (negative) transistors and P-type (positive) transistors. A switching transistor includes a source, a drain, and a gate. The switching transistor can be turned on (opened) or off (closed, cut off, open circuit) by controlling the level of the gate input. When the switching transistor is on, the source and drain conduct, generating an on-state current. Furthermore, the magnitude of the on-state current generated between the source and drain varies depending on the gate level. When the switching transistor is off, the source and drain do not conduct, and no current is generated. In the embodiments of this application, the gate of the switching transistor is also referred to as the control terminal, the source as the first terminal, and the drain as the second terminal; or, the gate is referred to as the control terminal, the drain as the first terminal, and the source as the second terminal. Furthermore, an N-type transistor turns on when the control terminal is high, with both terminals conducting and generating an on-state current. When the control terminal is low, the N-type transistor turns off, with neither terminal conducting and no current flowing between them. A P-type transistor turns on when the control terminal is low, with both terminals conducting and generating an on-state current. When the control terminal is high, the P-type transistor turns off, with neither terminal conducting and no current flowing between them. The switching transistors used in the following schemes can all be referenced to the description here.

[0078] also, Figure 10 In 4:1 buck mode, within one time period T, Figure 9 The timing diagram shows the control signals for each switch. Taking the example where each switch is on when high and off when low, switch Qadd (under the control of S3) is off throughout the entire time period T. In the first time interval t1 of time period T, refer to... Figure 11 As shown, switches Q1, Q3, Q5, Q6, and Q9 are in the ON state under the control of S1, while switches Q2, Q4, Q7, Q8, and Q10 are in the OFF state under the control of S2, connecting the capacitors to form... Figure 4 The equivalent circuit shown; the second time period t2, refer to... Figure 12 As shown, switches Q1, Q3, Q5, Q6, and Q9 are in the open state under the control of S1, while switches Q2, Q4, Q7, Q8, and Q10 are in the closed state under the control of S2, connecting the capacitors to form... Figure 5 The equivalent circuit shown demonstrates a 4:1 voltage ratio conversion. In the various embodiments of this application, the circuit is described with the control signal at a logic high level (H) in an on state and at a logic low level (L) in an off state.

[0079] Reference Figure 13 As shown, a typical SC based on the Dickson architecture is also provided, which includes Q1-Q8, eight switches, and four capacitors Cfly1, Cfly2, Cfly3, and Co. Switches Q1, Q2, Q3, Q4, and capacitor Co are connected in series between the power supply terminal (providing the supply voltage Vin) and ground GND. The series connection of switches Q5 and Q6 is connected in parallel with capacitor Co; the series connection of switches Q8 and Q7 is connected in parallel with capacitor Co; the series connection of switches Q2, Q3, Q4, and Q5 is connected in parallel with capacitor Cfly3; the series connection of switches Q4 and Q5 is connected in parallel with capacitor Cfly1; the series connection of switches Q3, Q4, and Q8 is connected in parallel with capacitor Cfly2; and the voltage output across capacitor Co supplies power to the load RL.

[0080] also, Figure 14 In 4:1 buck mode, within one time period T, Figure 13 The timing diagram of the control signals for each switch is shown. Taking the example that each switch is turned on when high and off when low, the timing diagram is as follows: In the first time interval t1 of a time period T, refer to... Figure 15 As shown, switches Q1, Q3, Q5, and Q7 are in the ON state under the control of S1, while switches Q2, Q4, Q6, and Q8 are in the OFF state under the control of S2, connecting the capacitors to form... Figure 16 The equivalent circuit shown; wherein, the third capacitor Cfly3 and the fourth capacitor Co form a series structure, and the two ends of this series structure are connected to the power supply terminal and the ground terminal GND respectively; the series structure formed by the first capacitor Cfly1 and the fourth capacitor Co is connected in parallel with the second capacitor Cfly2, and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly3 + Vo, Vcfly2 = Vcfly1 + Vo. The second time period t2, refer to... Figure 17 As shown, switches Q1, Q3, Q5, and Q7 are in the open state under the control of S1, while switches Q2, Q4, Q7, and Q8 are in the closed state under the control of S2, connecting the capacitors to form a... Figure 18 The equivalent circuit shown is as follows: The first capacitor Cfly1 and the fourth capacitor CO form a series connection; the second capacitor Cfly2 and the fourth capacitor CO form a series connection, which is then connected in parallel with the third capacitor Cfly3. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vcfly3 = Vcfly2 + Vo, Vcfly1 = Vo; therefore, Vin = 4Vo, Vcfly3 = 3Vo, Vcfly2 = 2Vo, and Vcfly1 = Vo, thereby achieving a 4:1 voltage ratio conversion.

[0081] Among them, combined Figures 10-12 China Figure 9 The provided circuit analysis of the SC in 4:1 buck mode, and Figures 14-18 right Figure 13 The circuit analysis of the provided SC in 4:1 buck mode shows that, in 4:1 buck mode, due to... Figure 13 All current supplied by SC must pass through switch Q5 during time period t1 (refer to...). Figure 15 As shown), and all current paths during time period t2 must pass through switch Q6 (refer to...). Figure 17 As shown in the diagram, this results in Q5 and Q6 having greater current losses, especially generating a large amount of heat in high-current scenarios, leading to low efficiency. Figure 9 In the provided SC, each switch follows only one current path, therefore the current loss is evenly distributed across all switches, relative to... Figure 13 The provided SC effectively improves overall system efficiency. Furthermore, Figure 13 The provided SC, in 4:1 buck mode, requires Cfly3 to have a withstand voltage of Vcfly3=3Vo, while Figure 9 The supplied capacitor requires a voltage rating of Vcfly3 = 2Vo for Cfly3. A higher voltage rating for Cfly3 results in a lower energy density per unit volume, thus reducing the power density of the capacitor.

[0082] Reference Figure 19As shown, another typical SC based on the Dickson architecture is also provided, which includes Q1-Q10, ten switches, and four capacitors Cfly1, Cfly2, Cfly3, and Co. Switches Q1, Q2, Q3, and capacitor Co are connected in series between the power supply terminal (providing the supply voltage Vin) and ground GND. The series structure of switches Q4 and Q5 is connected in parallel with capacitor Co; the series structure of switches Q8, Q6, and Q7 is connected in parallel with capacitor Co; the series structure of switches Q9 and Q10 is connected in parallel with capacitor Co; the series structure of switches Q2, Q3, Q8, and Q6 is connected in parallel with capacitor Cfly3; the series structure of switches Q3 and Q4 is connected in parallel with capacitor Cfly2; the series structure of switches Q8 and Q9 is connected in parallel with capacitor Cfly1; and the voltage output from capacitor Co supplies power to the load RL.

[0083] also, Figure 20 In 4:1 buck mode, within one time period T, Figure 19 The timing diagram of the control signals for each switch is shown. Taking the example that each switch is turned on when high and off when low, the timing diagram is as follows: In the first time interval t1 of a time period T, refer to... Figure 21 As shown, switches Q1, Q3, Q5, Q6, and Q9 are in the ON state under the control of S1, while switches Q2, Q4, Q7, Q8, and Q10 are in the OFF state under the control of S2, connecting the capacitors to form... Figure 22 The equivalent circuit shown; wherein, the third capacitor Cfly3, the first capacitor Cfly1, and the fourth capacitor Co form a series structure, and the two ends of this series structure are connected to the power supply terminal and the ground terminal GND, respectively; the second capacitor Cfly2 and the fourth capacitor Co are connected in parallel, and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly3 + Vcfly1 + Vo, Vcfly2 = Vo; in the second time period t2, refer to Figure 23 As shown, switches Q1, Q3, Q5, Q6, and Q9 are in the open state under the control of S1, while switches Q2, Q4, Q7, Q8, and Q10 are in the closed state under the control of S2, connecting the capacitors to form... Figure 24 The equivalent circuit shown is as follows: the first capacitor Cfly1 is connected in parallel with the fourth capacitor Co, and the series connection of the second capacitor Cfly2 and the third capacitor Cfly3 is connected in parallel with the fourth capacitor Co. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vcfly3 = Vcfly2 + Vo, where Vcfly2 is the voltage across capacitor Cfly2. In summary, we can obtain Vin = 4Vo, Vcfly3 = 2Vo, Vcfly2 = Vo, and Vcfly1 = Vo, thereby achieving a 4:1 voltage ratio transformation.

[0084] Among them, combined Figures 10-12 China Figure 9 The provided circuit analysis of the SC in 4:1 buck mode, and Figures 20-24 right Figure 19 The circuit analysis of the provided SC in 4:1 buck mode shows that in the embodiments of this application... Figure 9 The provided SC, in 4:1 buck mode, can achieve at least the equivalent of Figure 19 The effect of the provided SC.

[0085] Figure 25 Provided in 2:1 buck mode, within one time period T, Figure 9 The timing diagram shows the control signals for each switch. Taking the example where each switch is on when high and off when low, switches Q6 and Q7 (under the control of S3) are off throughout the entire time period T, while Q1 (under the control of S4) is on throughout the entire time period T. In the first time interval t1 of a time period T, refer to... Figure 26 As shown, switches Qadd, Q3, Q5, and Q9 are in the ON state under the control of S1, while switches Q2, Q4, Q8, and Q10 are in the OFF state under the control of S2, connecting the capacitors to form... Figure 6 The equivalent circuit shown; the second time period t2, refer to... Figure 27 As shown, switches Qadd, Q3, Q5, and Q9 are in the open state under the control of S1, while switches Q2, Q4, Q8, and Q10 are in the closed state under the control of S2, connecting the capacitors to form a... Figure 7 The equivalent circuit shown can be used to achieve a 2:1 voltage ratio conversion.

[0086] also, Figure 28 Provided in 2:1 buck mode, within one time period T, Figure 13 The timing diagram shows the control signals for each switch. Taking the example where each switch is on when high and off when low, switches Q2 and Q3 (under the control of S3) are on throughout the entire time period T. In the first time interval t1 of the time period T, refer to... Figure 29 As shown, switches Q1, Q5, and Q8 are in the ON state under the control of S1, while switches Q4, Q6, and Q7 are in the OFF state under the control of S2, connecting the capacitors to form... Figure 30The equivalent circuit shown is as follows: The third capacitor Cfly3 and the fourth capacitor Co form a series connection, with their ends connected to the power supply and ground (GND), respectively; the second capacitor Cfly2 and the fourth capacitor Co form a series connection, with their ends connected to the power supply and ground (GND), respectively; the first capacitor Cfly1 and the fourth capacitor Co form a series connection, with their ends connected to the power supply and ground (GND), respectively. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly1 + Vo, Vcfly1 = Vcfly2 = Vcfly3. For the second time period t2, refer to... Figure 31 As shown, switches Q1, Q5, and Q8 are in the open state under the control of S1, while switches Q4, Q6, and Q7 are in the closed state under the control of S2, connecting the capacitors to form a... Figure 32 The equivalent circuit shown is illustrated in the figure. In this circuit, the first capacitor Cfly1, the second capacitor Cfly2, and the third capacitor Cfly3 are all connected in parallel with the fourth capacitor Co, and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vcfly3 = Vcfly2 = cfly1 = Vo; therefore, Vin = 2Vo, Vcfly3 = Vo, Vcfly2 = Vo, and Vcfly1 = Vo, thereby achieving a 2:1 voltage ratio conversion.

[0087] Among them, combined Figures 25-27 China Figure 9 The provided circuit analysis of the SC in 2:1 buck mode, and Figures 28-32 right Figure 13 The circuit analysis of the provided SC in 2:1 buck mode shows that, in 2:1 buck mode, due to... Figure 13 All current supplied by SC must pass through switch Q5 during time period t1 (refer to...). Figure 29 As shown), and all current paths during time period t2 must pass through switch Q6 (refer to...). Figure 31 As shown in the diagram, this results in Q5 and Q6 having greater current losses, especially generating a large amount of heat in high-current scenarios, leading to low efficiency. Figure 9 In the provided SC, each switch follows only one current path, therefore the current loss is evenly distributed across all switches, relative to... Figure 13 The provided SC effectively improves the overall system efficiency.

[0088] also, Figure 33 Provided in 2:1 buck mode, within one time period T, Figure 19The timing diagram shows the control signals for each switch. Taking the example where each switch is on when high and off when low, Q6-Q10 (under the control of S3) are off throughout the entire time period T, while Q1 (under the control of S4) is on throughout the entire time period T. In the first time interval t1 of a time period T, refer to... Figure 34 As shown, switches Q2 and Q4 are in the ON state under the control of S1, while switches Q3 and Q5 are in the OFF state under the control of S2, connecting the capacitors to form a... Figure 35 The equivalent circuit shown is as follows: The third capacitor Cfly3 and the first capacitor Cfly1 are disconnected from the circuit; the second capacitor Cfly2 and the fourth capacitor Co form a series connection, with their ends connected to the power supply and ground GND respectively. The current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vin = Vcfly2 + Vo; In the second time period t2, refer to... Figure 36 As shown, switches Q2 and Q4 are in the open state under the control of S1, while switches Q3 and Q5 are in the closed state under the control of S2, connecting the capacitors to form a circuit. Figure 37 The equivalent circuit shown is as follows: the third capacitor Cfly3 and the first capacitor Cfly1 are disconnected from the circuit; the second capacitor Cfly2 and the fourth capacitor Co are connected in parallel, and the current flows in the direction indicated by the dashed arrow in the figure. Thus, when the system is stable: Vcfly2=Vo. In summary, Vin=2Vo and Vcfly2=Vo, thereby achieving a 2:1 voltage ratio transformation.

[0089] Among them, combined Figures 25-27 China Figure 9 The provided circuit analysis of the SC in 2:1 buck mode, and Figures 33-37 right Figure 19 The provided circuit analysis of the SC in 2:1 buck mode. Figure 19 The provided SC uses only one flying capacitor Cfly2 in 2:1 buck mode. In this structure, all current supplied by the power supply has only one current path; while... Figure 9 In 2:1 buck mode, the provided SC, by adding a switch Qadd, can utilize more flying capacitors (Cfly1 and Cfly2). During time period t1, capacitor Cfly1 is connected in series with capacitor Co, and during time period t2, capacitor Cfly1 is connected in parallel with capacitor Co, forming an interleaved parallel structure. This provides more current paths to the power supply, thus... Figure 19 The proposed solution can effectively reduce power consumption.

[0090] In 1:1 buck mode, for Figure 9In the illustrated SC, switches Q1, Q2, Q3, Qadd and Q8 are controlled to be turned on, and other switches Q4-Q7, Q9 and Q10 are controlled to be turned off throughout the entire time period, as Figure 38 shown; in this way, each capacitor is connected to form Figure 8 the equivalent circuit shown; thus a voltage proportional conversion of 1:1 can be achieved. For the Figure 13 illustrated SC, switches Q1, Q2, Q3 and Q4 are controlled to be turned on, and other switches Q5-Q8 are controlled to be turned off throughout the entire time period, as Figure 39 shown; in this way, each capacitor can be connected to form Figure 8 the equivalent circuit shown; thus a voltage proportional conversion of 1:1 can be achieved. For the Figure 19 illustrated SC, switches Q1, Q2 and Q3 are controlled to be turned on, and other switches Q4-Q10 and Qadd are controlled to be turned off throughout the entire time period, as Figure 40 shown; in this way, each capacitor can be connected to form Figure 8 the equivalent circuit shown; thus a voltage proportional conversion of 1:1 can be achieved. Although the equivalent circuits of capacitor connection formed by the SC provided in the above Figure 9 , Figure 13 and Figure 19 in the 1:1 step-down mode are the same, it can be seen with reference to Figures 38-40 that in Figure 38 , due to the addition of Qadd, when Q2, Q3, Qadd and Q8 are turned on, the series structure of Q2 and Q3 and the series structure of Qadd and Q8 are connected in parallel to reduce the resistance on the current path; while Figure 39 has switches Q1, Q2, Q3 and Q4 directly connected in series with the output capacitor Co on the current path, Figure 40 has switches Q1, Q2 and Q3 directly connected in series with the output capacitor Co on the current path, so there is a larger resistance. Therefore, the Figure 9 provided SC has higher efficiency.

[0091] In summary, Figure 9 the provided SC can achieve multiple step-down modes of 4:1, 2:1 and 1:1, and has higher efficiency compared with the two existing SCs based on the Dickson architecture (the SCs provided by Figure 13 and Figure 19 ).

[0092] In addition, in combination with what is shown in Figure 41 , a chip 30 is provided, wherein the chip 30 comprises: a first switch circuit 31, a second switch circuit 32, a third switch circuit 33, and a fourth switch circuit 34. Different from the SC circuit provided in Figure 3 , since capacitors need to be implemented by large-sized plates, which is not conducive to integration on a chip. Therefore, Figure 3 The provided SC can be accessed through Figure 41 The provided chip 30 and capacitors disposed on the PCB surrounding the chip 30 are connected together. For details, refer to... Figure 41 The provided chip 30 package structure includes: a first switch circuit 31, a second switch circuit 32, a third switch circuit 33, and a fourth switch circuit 34. The chip 30 also includes 10 pins (P1-P10). The first terminal of the first switch circuit 31 is connected to the power supply terminal Vin via P1; the second terminal of the first switch circuit 31 is used to connect to the first terminal of the third capacitor Cfly3 via P2; the third terminal of the first switch circuit 31 is connected to the first terminal of the second switch circuit 31; the third terminal of the first switch circuit 31 is also used to connect to the first terminal of the first capacitor Cfly1 via P7; the fourth terminal of the first switch circuit 31 is used to connect to the first terminal of the second capacitor Cfly2 via P5; and the fifth terminal of the first switch circuit 31 is connected to the first terminals of the third switch circuit 33 and the first terminals of the fourth switch circuit 34. The fifth terminal of the first switch circuit 31 is also used for… The first terminal of the fourth capacitor Co is connected via P9; the second terminal of the second switching circuit 32 is connected via P3 to the second terminal of the third capacitor Cfly3, and the third terminal of the second switching circuit 32 is connected to ground GND via P10; the second terminal of the third switching circuit 33 is connected via P6 to the second terminal of the second capacitor Cfly2, and the third terminal of the third switching circuit 33 is connected to ground GND via P10; the second terminal of the fourth switching circuit 34 is connected via P8 to the second terminal of the first capacitor Cfly1, and the third terminal of the fourth switching circuit 34 is connected to ground GND via P10; the second terminal of the fourth capacitor Co is connected to ground GND. Furthermore, the internal structure and working principle of the first switching circuit 31, second switching circuit 32, third switching circuit 33, and fourth switching circuit 34 in this chip can be referred to the detailed descriptions in the above embodiments, and will not be repeated here.

[0093] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce a good effect.

[0094] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A switched capacitor circuit SC, characterized in that, include: The circuit includes a first switching circuit, a second switching circuit, a third switching circuit, a fourth switching circuit, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. Wherein, the first terminal of the first switching circuit is connected to the power supply terminal; the second terminal of the first switching circuit is connected to the first terminal of the third capacitor; the third terminal of the first switching circuit is connected to the first terminal of the second switching circuit and the first terminal of the first capacitor; the fourth terminal of the first switching circuit is connected to the first terminal of the second capacitor; the fifth terminal of the first switching circuit is connected to the first terminal of the third switching circuit, the first terminal of the fourth switching circuit, and the first terminal of the fourth capacitor; the second terminal of the third capacitor is connected to the second terminal of the second switching circuit, and the third terminal of the second switching circuit is connected to ground; the second terminal of the second capacitor is connected to the second terminal of the third switching circuit, and the third terminal of the third switching circuit is connected to ground; the second terminal of the first capacitor is connected to the second terminal of the fourth switching circuit, and the third terminal of the fourth switching circuit is connected to ground; the second terminal of the fourth capacitor is connected to ground. In the first buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the third capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to the first terminal of the first capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the third capacitor to the first terminal of the second capacitor, and connect the first terminal of the first capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to ground; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground. In the second buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the first capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the second capacitor to the power supply terminal, and connect the first terminal of the first capacitor to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground. In the third buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the fourth capacitor.

2. The switched capacitor circuit SC according to claim 1, characterized in that, The first switching circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, the first end of the first switch is connected to the first end of the first switching circuit, the second end of the first switch is connected to the second end of the first switching circuit, the first end of the second switch is connected to the second end of the first switching circuit, the second end of the second switch is connected to the fourth end of the first switching circuit, the first end of the fourth switch is connected to the second end of the first switching circuit, the second end of the third switch is connected to the fourth end of the first switching circuit, the second end of the third switch is connected to the fifth end of the first switching circuit, and the first end of the fifth switch is connected to the third end of the first switching circuit, and the second end of the fifth switch is connected to the fifth end of the first switching circuit. In the first step-down mode, during the first time period of a cycle, the first switch and the third switch are in the on state, and the second switch and the fifth switch are in the off state; during the second time period of a cycle, the first switch and the third switch are in the off state, and the second switch and the fifth switch are in the on state; during the cycle, the fourth switch is in the off state. In the second step-down mode, during the first time period within a cycle, the third and fourth switches are in the ON state, and the second and fifth switches are in the OFF state; during the second time period within a cycle, the third and fourth switches are in the OFF state, and the second and fifth switches are in the ON state; during one cycle, the fourth switch is in the OFF state; and during one cycle, the first switch is in the ON state. In the third step-down mode, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are in the ON state.

3. The switched capacitor circuit SC according to claim 1, characterized in that, The second switching circuit includes a sixth switch and a seventh switch; wherein, the first end of the sixth switch is connected to the first end of the second switching circuit, the second end of the sixth switch is connected to the second end of the second switching circuit, the first end of the seventh switch is connected to the second end of the second switching circuit, and the second end of the seventh switch is connected to the third end of the second switching circuit. In the first buck mode, during the first time period within a cycle, the sixth switch is in the on state and the seventh switch is in the off state; during the second time period within a cycle, the sixth switch is in the off state and the seventh switch is in the on state. In the second step-down mode, the sixth switch and the seventh switch are in the off state; In the third step-down mode, the sixth switch and the seventh switch are in the off state.

4. The switched capacitor circuit SC according to claim 1, characterized in that, The third switching circuit includes: an eighth switch and a ninth switch; Wherein, the first end of the eighth switch is connected to the first end of the third switch circuit, the second end of the eighth switch is connected to the second end of the third switch circuit, the first end of the ninth switch is connected to the second end of the third switch circuit, and the second end of the ninth switch is connected to the third end of the third switch circuit. In the first buck mode, during the first time period within a cycle, the ninth switch is in the on state and the eighth switch is in the off state; during the second time period within a cycle, the ninth switch is in the off state and the eighth switch is in the on state. In the second buck mode, during the first time period within a cycle, the ninth switch is in the on state and the eighth switch is in the off state; during the second time period within a cycle, the ninth switch is in the off state and the eighth switch is in the on state. In the third step-down mode, the eighth switch and the ninth switch are in the off state.

5. The switched capacitor circuit SC according to claim 1, characterized in that, The fourth switching circuit includes a tenth switch and an eleventh switch, wherein the first end of the tenth switch is connected to the first end of the fourth switching circuit, the second end of the tenth switch is connected to the second end of the fourth switching circuit, the first end of the eleventh switch is connected to the second end of the fourth switching circuit, and the second end of the eleventh switch is connected to the third end of the fourth switching circuit. In the first buck mode, during the first time period within a cycle, the tenth switch is in the on state and the eleventh switch is in the off state; during the second time period within a cycle, the tenth switch is in the off state and the eleventh switch is in the on state. In the second buck mode, during the first time period within a cycle, the tenth switch is in the on state and the eleventh switch is in the off state; during the second time period within a cycle, the tenth switch is in the off state and the eleventh switch is in the on state. In the third step-down mode, the tenth switch and the eleventh switch are in the off state.

6. The switched capacitor circuit SC according to any one of claims 2-5, characterized in that, Each switch includes a switching transistor, or each switch includes two or more switching transistors connected in parallel.

7. A chip, characterized in that, include: First switching circuit, second switching circuit, third switching circuit, fourth switching circuit; Wherein, the first terminal of the first switching circuit is connected to the power supply terminal; the second terminal of the first switching circuit is used to connect to the first terminal of the third capacitor, the third terminal of the first switching circuit is connected to the first terminal of the second switching circuit, the third terminal of the first switching circuit is also used to connect to the first terminal of the first capacitor, the fourth terminal of the first switching circuit is used to connect to the first terminal of the second capacitor, the fifth terminal of the first switching circuit is connected to the first terminal of the third switching circuit and the first terminal of the fourth switching circuit, the fifth terminal of the first switching circuit is also used to connect to the first terminal of the fourth capacitor; the second terminal of the second switching circuit is used to connect to the second terminal of the third capacitor, and the third terminal of the second switching circuit is connected to ground; the second terminal of the third switching circuit is used to connect to the second terminal of the second capacitor, and the third terminal of the third switching circuit is connected to ground; the second terminal of the fourth switching circuit is used to connect to the second terminal of the first capacitor, the third terminal of the fourth switching circuit is connected to ground, and the second terminal of the fourth capacitor is connected to ground. In the first buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the third capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to the first terminal of the first capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the third capacitor to the first terminal of the second capacitor, and connect the first terminal of the first capacitor to the first terminal of the fourth capacitor; the second switching circuit is configured to connect the second terminal of the third capacitor to ground; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground. In the second buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the first capacitor, and connect the first terminal of the second capacitor to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to ground; the fourth switching circuit is configured to connect the second terminal of the first capacitor to the first terminal of the fourth capacitor; or, the first switching circuit is configured to connect the first terminal of the second capacitor to the power supply terminal, and connect the first terminal of the first capacitor to the first terminal of the fourth capacitor; the third switching circuit is configured to connect the second terminal of the second capacitor to the first terminal of the fourth capacitor; the fourth switching circuit is configured to connect the second terminal of the first capacitor to ground. In the third buck mode, the first switching circuit is configured to connect the power supply terminal to the first terminal of the fourth capacitor.

8. The chip according to claim 7, characterized in that, The first switching circuit includes: a first switch, a second switch, a third switch, a fourth switch, and a fifth switch; wherein, the first end of the first switch is connected to the first end of the first switching circuit, the second end of the first switch is connected to the second end of the first switching circuit, the first end of the second switch is connected to the second end of the first switching circuit, the second end of the second switch is connected to the fourth end of the first switching circuit, the first end of the fourth switch is connected to the second end of the first switching circuit, the second end of the third switch is connected to the fourth end of the first switching circuit, the second end of the third switch is connected to the fifth end of the first switching circuit, and the first end of the fifth switch is connected to the third end of the first switching circuit, and the second end of the fifth switch is connected to the fifth end of the first switching circuit. In the first step-down mode, during the first time period of a cycle, the first switch and the third switch are in the on state, and the second switch and the fifth switch are in the off state; during the second time period of a cycle, the first switch and the third switch are in the off state, and the second switch and the fifth switch are in the on state; during the cycle, the fourth switch is in the off state. In the second step-down mode, during the first time period within a cycle, the third and fourth switches are in the ON state, and the second and fifth switches are in the OFF state; during the second time period within a cycle, the third and fourth switches are in the OFF state, and the second and fifth switches are in the ON state; during one cycle, the fourth switch is in the OFF state; and during one cycle, the first switch is in the ON state. In the third step-down mode, the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are in the ON state.

9. The chip according to claim 7, characterized in that, The second switching circuit includes a sixth switch and a seventh switch; wherein, the first end of the sixth switch is connected to the first end of the second switching circuit, the second end of the sixth switch is connected to the second end of the second switching circuit, the first end of the seventh switch is connected to the second end of the second switching circuit, and the second end of the seventh switch is connected to the third end of the second switching circuit. In the first buck mode, during the first time period within a cycle, the sixth switch is in the on state and the seventh switch is in the off state; during the second time period within a cycle, the sixth switch is in the off state and the seventh switch is in the on state. In the second step-down mode, the sixth switch and the seventh switch are in the off state; In the third step-down mode, the sixth switch and the seventh switch are in the off state.

10. The chip according to claim 7, characterized in that, The third switching circuit includes: an eighth switch and a ninth switch; Wherein, the first end of the eighth switch is connected to the first end of the third switch circuit, the second end of the eighth switch is connected to the second end of the third switch circuit, the first end of the ninth switch is connected to the second end of the third switch circuit, and the second end of the ninth switch is connected to the third end of the third switch circuit. In the first buck mode, during the first time period within a cycle, the ninth switch is in the on state and the eighth switch is in the off state; during the second time period within a cycle, the ninth switch is in the off state and the eighth switch is in the on state. In the second buck mode, during the first time period within a cycle, the ninth switch is in the on state and the eighth switch is in the off state; during the second time period within a cycle, the ninth switch is in the off state and the eighth switch is in the on state. In the third step-down mode, the eighth switch and the ninth switch are in the off state.

11. The chip according to claim 7, characterized in that, The fourth switching circuit includes a tenth switch and an eleventh switch, wherein the first end of the tenth switch is connected to the first end of the fourth switching circuit, the second end of the tenth switch is connected to the second end of the fourth switching circuit, the first end of the eleventh switch is connected to the second end of the fourth switching circuit, and the second end of the eleventh switch is connected to the third end of the fourth switching circuit. In the first buck mode, during the first time period within a cycle, the tenth switch is in the on state and the eleventh switch is in the off state; during the second time period within a cycle, the tenth switch is in the off state and the eleventh switch is in the on state. In the second buck mode, during the first time period within a cycle, the tenth switch is in the on state and the eleventh switch is in the off state; during the second time period within a cycle, the tenth switch is in the off state and the eleventh switch is in the on state. In the third step-down mode, the tenth switch and the eleventh switch are in the off state.

12. The chip according to any one of claims 7-11, characterized in that, Each switch includes a switching transistor, or each switch includes two or more switching transistors connected in parallel.

13. An electronic device, characterized in that, Includes the switched capacitor circuit SC as described in any one of claims 1-6 or the chip as described in any one of claims 7-12.

14. The electronic device according to claim 13, characterized in that, It also includes a wireless charging coil, a receiving circuit, and a battery; the wireless charging coil is connected to the receiving circuit, the receiving circuit is connected to the switched capacitor circuit SC or the power supply terminal of the chip, and the battery is connected in parallel with the fourth capacitor.

15. The electronic device according to claim 13, characterized in that, It also includes a USB interface and a battery; the USB interface is connected to the power supply terminal of the switched capacitor circuit SC or the chip, and the battery is connected in parallel with the fourth capacitor.

16. The electronic device according to claim 15, characterized in that, An overvoltage protection circuit is also provided between the USB interface and the power supply terminal of the switched capacitor circuit SC or the chip. The overvoltage protection circuit is used to disconnect the connection between the power supply terminal of the switched capacitor circuit SC or the chip and the USB interface when it detects that the voltage connected to the USB interface exceeds the threshold voltage.

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