Modular Multilevel Converter Submodule Switching Frequency Reduction Optimization Method and System

Abstract

This invention proposes a method for optimizing the switching frequency reduction of submodules in a modular multilevel converter (MMC). The method includes the following steps: establishing a MMC system; determining the number of submodules in the upper and lower arms based on a reference modulation voltage; calculating the duration of each level; and, based on the expression for the average switching frequency of the submodules, considering switching losses and steady-state voltage deviation, determining the relationship between the construction of the full-rank switching state matrix and its self-balancing control effect at different time scales; and, within the time scale ensuring self-balancing of the submodule capacitor voltage, constructing a switching state matrix that reduces the switching frequency of the submodules based on the number of submodules in the upper and lower arms, thereby reducing the switching states of the switching vector and lowering the switching frequency of the devices. This reduces the switching losses of the system during self-balancing control, extending the lifespan of the switching devices, even with the potential loss of some voltage deviation.

Description

Technical Field

[0001] This invention belongs to the technical field of voltage self-balancing control switch loss reduction in power system converters, specifically involving a method for optimizing the switching frequency reduction of modular multilevel converter submodules. Background Technology

[0002] Current flexible direct current (HVDC) transmission systems widely employ half-bridge modular multilevel converters (HB-MMC), with DC-side capacitor voltages distributed across hundreds of cascaded sub-modules. In engineering practice, closed-loop control-based sorting algorithms are often used to achieve capacitor voltage balancing across these sub-modules. However, when the number of sub-modules is large, the sorting and calculation time complexity is high, real-time sampling and monitoring data is complex, and system switching losses are significant.

[0003] To address the aforementioned issues, there are two main types of self-balancing control strategies for MMC submodule capacitor voltages: The first type utilizes a hardware-based self-equalizing MMC topology, offering good voltage equalization and strong DC fault suppression capabilities. However, the added components increase hardware costs and circuit complexity, and raise safety concerns regarding the withstand voltage and insulation of external circuits. The second type is based on control algorithms, proposing switching rules for submodules from the perspective of the switching state matrix. This eliminates the need for real-time sampling and sorting of submodule capacitor voltages and does not alter the MMC topology. However, it does not deeply consider the balance between control effectiveness and switching losses; numerous different switching state matrix row vectors may lead to excessively frequent submodule switching and high device switching losses.

[0004] Existing switching loss reduction strategies mainly focus on the analysis and research of loss calculation methods for traditional sorting and equalizing MMC-HVDC. They primarily optimize the switching frequency reduction of submodule capacitor voltage balance control from three aspects: optimizing the sorting algorithm, modulation loss reduction technology, and special hardware structure. However, due to problems such as inconsistent capacitor voltage sampling requirements, mismatched modulation strategies, and different factors affecting submodule switching, the above-mentioned switching frequency reduction optimization strategies cannot be directly applied to self-balancing control. Summary of the Invention

[0005] The purpose of this invention is to address the limitations of existing submodule capacitor voltage balance control and switching loss reduction techniques in MMC systems by providing a modular multilevel converter submodule switching frequency reduction optimization method. Based on achieving submodule capacitor voltage self-balancing using a switching state matrix, this method reduces the submodule switching frequency and the number of switching vector switching states. Even with the possibility of some voltage deviation loss, it reduces the system's switching losses during self-balancing control and extends the service life of switching devices.

[0006] To achieve the above objectives, this invention proposes a method for optimizing the switching and frequency reduction of a modular multilevel converter submodule, which includes the following steps:

[0007] Step 1: Establish the MMC system, use Nearest Level Approximation Modulation (NLM) to generate a reference modulation voltage waveform, and determine the number of sub-modules to be engaged in the upper and lower bridge arms based on the reference modulation voltage;

[0008] Step 2: Based on the MMC system and self-balancing control characteristics established in Step 1, obtain the expression for the average switching frequency of the sub-module;

[0009] Step 3: Calculate the duration of each level. Based on the submodule average switching frequency expression in Step 2, obtain the number of row vectors for each level, and thus construct the full-rank switching state matrix S at different time scales. N Determine the self-balancing control effect of submodule capacitor voltage under different row vector compositions and sequences;

[0010] Step 4: Based on Step 3, while ensuring the self-balancing of the submodule capacitor voltage on the given time scale, construct an S′ that can reduce the submodule switching frequency according to the number of submodules engaged in the upper and lower bridge arms. N This achieves a balance between the number of switching operations for each submodule and the effectiveness of self-balancing control, minimizing the different switching states in the switching state matrix and reducing the switching losses of the system during self-balancing control.

[0011] Furthermore, in step 1, for the (N+1) level MMC system, at any given time, the total number of submodules engaged in the upper and lower arms of each phase satisfies dynamic balance, and the sum of the capacitor voltages of the submodules equals the DC side voltage, that is:

[0012]

[0013] In the formula, n pj ,n nj (j = a, b, c) represent the number of sub-modules required for the upper and lower bridge arms, respectively. Crj_i,ref This represents the theoretical steady-state value of the capacitor voltage in the submodule.

[0014] Furthermore, in step 1, for the (N+1) level MMC system, NLM modulation is used. Based on the theoretical steady-state values ​​of the AC side output voltage and the submodule capacitor voltage, the number of submodules n required to be deployed in the upper bridge arm can be calculated. pj :

[0015]

[0016] In the formula, u sj This is the AC side output voltage.

[0017] Furthermore, the expression for the average switching frequency of the submodule is derived in step 2 as follows:

[0018]

[0019] Where: f sw is the average switching frequency, f c is the control frequency, n si is the number of times the sub-module state switches within a unit control period, T0 is the power frequency period, and N is the total number of sub-modules in the bridge arm.

[0020] Furthermore, the end time of each level in step 3 (i.e., the start time of the next level) t x (x = 0, 1, 2, …, N - 1) is:

[0021]

[0022] Substituting the system parameters into the above formula can calculate t x , from which the duration Δt of each level can be calculated x (x = 0, 1, 2, …, N - 1). The duration of each row vector is 1 / f c , from which the number of row vectors at each level can be calculated.

[0023] Preferably, in step 3, based on the power frequency control period, a full-rank S is constructed at different time scales within one power frequency control period N ;

[0024] Preferably, the full-rank S in step 3 N satisfies: rank(S N ) = 2N

[0025] Preferably, in step 4, S N is divided into (N + 1) sub-matrices, and calculations and constructions are performed respectively for the sub-matrices at different levels, and then combined to obtain S′ that can reduce the sub-module switching frequency N :

[0026] ​​​​​​​​​​​​​​​​​​​​​​​​ The matrix formed by the last (N - 1) rows, the matrix is calculated and formed according to the following rules:

[0032]

[0033] In the formula, A1, A2, and A3 are all N×N triangular matrices.

[0034] 4) When 0 < i < N and i is even: Select any row in the row vectors of the original switching state matrix that meets the number of switching on the upper and lower bridge arms, and replace all the original row vectors for self - balancing control, that is All the row vectors in are the same.

[0035] Preferably, in step 4, S′ is carried out mainly for the purpose of reducing the switching frequency <000002​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​

[0044] This invention provides a method for optimizing the switching and frequency reduction of modular multilevel converter submodules, which is applied in current mainstream HB-MMC systems, such as... Figure 1 As shown. The upper and lower arms of each phase are connected by the arm reactor L. arm Bridge arm resistance R arm It is composed of N submodules (SM) connected in series. Ignoring the voltage drop of the bridge arm reactors, u sm Superimposed to form U dc i sm By charging and discharging the capacitor, the capacitor voltage is changed, thus forming the output level. Based on Figure 1 We obtain the relationship expression between the total number of submodules connected to the upper and lower bridge arms, the sum of the capacitor voltages of the submodules, and the DC side voltage.

[0045] based on Figure 1 The j-phase equivalent circuit is obtained, such as Figure 2 As shown. u sj i sj These represent the AC side output voltage and current, respectively, L j R j These are the bridge arm inductance and resistance, respectively, L Tj R Tj These are the transformer equivalent inductance and resistance referred to the transformer valve side, i pj i nj u pj u nj These represent the upper and lower bridge arm currents and the submodule capacitor voltage, respectively. sj This is the grid voltage referred to the transformer valve side. Based on Figure 2 This yields the expression for the number of submodules required for the upper and lower bridge arms.

[0046] based on Figure 1 and Figure 2 Derivation of the submodule switching state S rj_i The number of bridge arm sub-modules N, and the sub-module capacitor voltage U Crj_i and DC voltage U dc The matrix relationship expression between them is used to construct the switching state matrix S that enables self-balancing control of the capacitor voltage of the submodule. N S is constructed for different time scales. N The self-balancing of the capacitor voltage in the submodule is achieved through the cyclic input of matrix row vectors, such as... Figure 3a As shown in -c; at the same time, while ensuring the self-balancing of the capacitor voltage of the submodule, the switching frequency of the submodule is reduced as much as possible by designing the composition and order of the matrix row vectors.

[0047] The improvements made in this embodiment to the submodule capacitor voltage balance control and switching loss reduction technology in the existing MMC system are mainly as follows: no additional hardware circuitry is added, it is not affected by the number of submodules, it is decoupled from other control loops, effectively reducing the consumption of computing resources, and it is supported by previous theoretical research; at the same time, through S at different time scales N The selection, construction, and optimization of the system aim to minimize the different switching states in the switching state vector and reduce the number of switching operations for each submodule, thereby reducing the switching losses of the system during the self-balancing control process, while ensuring the self-balancing of the capacitor voltage of the submodule.

[0048] This example demonstrates the switching and frequency reduction of submodule capacitor voltage self-balancing control in an MMC system, including the following steps:

[0049] Step 1: Establish as follows Figure 1 The three-phase half-bridge submodule MMC (HB-MMC) system shown, for an (N+1) level MMC system, at any given time, the total number of submodules connected in the upper and lower bridge arms of each phase satisfies dynamic balance, and the sum of the capacitor voltages of the submodules equals the DC side voltage, that is:

[0050]

[0051] In the formula, n pj ,n nj (j = a, b, c) represent the number of sub-modules required for the upper and lower bridge arms, respectively. Crj_i,ref This represents the theoretical steady-state value of the capacitor voltage in the submodule.

[0052] The reference modulation voltage waveform is generated using nearest-level approximation modulation (NLM). Based on the theoretical steady-state values ​​of the AC side output voltage and the submodule capacitor voltage, the number of submodules n required to be engaged in the upper bridge arm can be calculated. pj By combining equation (1), we can obtain the number of sub-modules n deployed in the lower bridge arm. nj :

[0053]

[0054] In the formula, u sj This is the AC side output voltage.

[0055] Introducing submodule switching state S rj_i =1 / 0(r=p,n;j=a,b,c;i=1,2,...,N), equation (1) can be written as:

[0056]

[0057] In the formula, U Crj_i This represents the capacitor voltage of the submodule.

[0058] Transform all the equations that satisfy the conditions into matrix form:

[0059] S N ·U C =U dc (4)

[0060] In the formula, S N Each row represents the switching state vector of all sub-modules in the upper and lower arms of phase j [S]. pj_1 … S pj_N S nj_1 … S nj_N ];U C Let U be a column vector representing the capacitor voltages [U] of all submodules in phase j. Cpj_1 … U Cpj_N U Cnj_1 …U Cnj_N ] T U dc It is a column vector, and all elements are U. dc .

[0061] Step 2: In self-balancing control, the additional control losses in traditional voltage sorting and balancing control are ignored. The submodule switching frequency can be expressed as the average number of submodule state switching times within a cycle:

[0062]

[0063] In the formula: f sw f is the average switching frequency. c To control the frequency, n si The number of submodule state transitions within a unit control cycle, where T0 is the power frequency cycle and N is the total number of bridge arm submodules. To ensure f... sw If f is as small as possible, then c and n si It should be as small as possible.

[0064] Step 3: End time of each level (i.e., start time of the next level) t x (x = 0, 1, 2, ..., N-1) is:

[0065]

[0066] Substituting the system parameters into the above formula, t can be calculated. x The duration Δt of each level can be calculated. x (x = 0, 1, 2, ..., N-1). The duration of each row vector is 1 / f. c This allows us to calculate the number of row vectors at each level. We then construct the full-rank switching state matrix S at different time scales. N The self-balancing control effect of submodule capacitor voltage under different row vector compositions and sequences is determined, and the time-scale-based S is obtained.N The relationship between and self-balancing control effects;

[0067] The parameters of the 5-level MMC system in this implementation example are shown in Table 1.

[0068] Table 1 Parameters of 5-Level MMC System

[0069]

[0070] The duration of each row vector is 1 / f c =0.0002s, then the number of row vectors at each level is shown in Table 2 (0.5 row vectors indicate that the duration of the row vector is 1 / 2f). c ).

[0071] Table 2. Time parameters for each level of the 5-level MMC system

[0072]

[0073] Take any m (m = 2, 3, 4, 5) adjacent levels when the S level is at full rank N The self-balancing control effect at full rank was compared at different time scales. The calculated m and the time scale for achieving full rank satisfy the correspondence shown in Table 3.

[0074] Table 3 Timescale for achieving full rank conditions

[0075]

[0076] Figure 4a -b is a comparison of the control effects of the loss reduction optimization strategy based on the switching state matrix of the modular multilevel converter submodule capacitor voltage self-balancing control. To reduce the number of submodule switching operations, the above groups of S... N Optimize the system to arrange the same row vectors at each level as adjacent as possible, and count the total number of submodule switching times and steady-state voltage fluctuation rate within 1 second. Figure 4a The scatter points on the left correspond to the optimized case, while the scatter points on the right correspond to the unoptimized case. Figure 4b Groups 1-4, 5-7, 8-10, and 11-13 correspond to full rank within any time interval of 6.5ms, 10ms, 13.5ms, and 15.6ms, respectively.

[0077] The simulation results show that S N When the submodule capacitor voltage reaches full rank on a relatively long timescale (m=3,4,5), the steady-state fluctuation rate is large, but compared to the S condition when full rank is reached in a short time (m=2), the steady-state fluctuation rate is relatively large. N The number of different row vectors and sub-module switching states required is reduced, that is, the number of sub-module switching operations is reduced, thus reducing switching losses.

[0078] It can be seen from the simulation results that for S N after the row vectors are optimized, the total number of sub-module switching operations is reduced, and the switching frequency and losses are decreased; and when the row vectors satisfy full rank (m = 2) within any 6.5 ms and are optimized, the voltage equalization effect of its self-balancing control is better and the number of switching operations is less.

[0079] Step 4: Based on Step 3, on the time scale (m = 2) that ensures the self-balancing of the sub-module capacitor voltages and has a good control effect, construct a new S′ N that can reduce the sub-module switching frequency according to the number of sub-modules inserted in the upper and lower arms, so as to achieve a balance between the number of switching operations of each sub-module and the self-balancing control effect. Divide S′ N into (N + 1) sub-matrices:

[0080]

[0081] 1) When i = 0:

[0082] 2) When i = N:

[0083] 3) When 0 < i < N and i is odd:

[0084]

[0085] In the formula, is an N×N 0 / 1 matrix, whose row vectors represent the switching states when i sub-modules are conducting, and the sum of the elements in each row is equal to i. is the matrix composed of the first (N - 1) rows, is the matrix composed of the last (N - 1) rows of The matrix

[0086]

[0087] is calculated and formed according to the following rule: In the formula, A1, A2 and A3 are all N×N triangular matrices.

[0088] 4) When 0 < i < N and i is even: Select any row from the row vectors of the original switching state matrix that meets the switching numbers of the upper and lower arms, and replace all the original row vectors for self-balancing control, that is, all the row vectors in are the same.

[0089] The method for optimizing the sub-module switching frequency reduction of the modular multilevel converter proposed in this embodiment, through the full-rank S NThe selection, construction, and optimization of the system aim to minimize the different switching states in the switching state vector and reduce the number of switching operations for each submodule, thereby reducing the switching losses of the system during the self-balancing control process, while ensuring the self-balancing of the capacitor voltage of the submodule.

[0090] Example 2

[0091] The present invention also provides a system comprising:

[0092] The first module is configured to generate a reference modulation voltage waveform, determine the number of sub-modules to be engaged in the upper and lower bridge arms based on the reference modulation voltage waveform, and build the MMC system.

[0093] The second module is configured to obtain the average switching frequency of the sub-modules based on the constructed MMC system and self-balancing control characteristics.

[0094] The third module is configured to calculate the duration of each level, obtain the number of row vectors for each level based on the average switching frequency of the submodules, and construct a full-rank switching state matrix S at different time scales. N Determine the self-balancing control effect of submodule capacitor voltage under different row vector compositions and sequences;

[0095] The fourth module is configured to construct a switching state matrix S′ that reduces the switching frequency of submodules, based on the number of submodules engaged in the upper and lower bridge arms, while ensuring self-balancing of the submodule capacitor voltages on a timescale. N .

[0096] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0097] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0098] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0099] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0100] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0101] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for optimizing the switching and frequency reduction of a modular multilevel converter submodule, characterized in that, It includes the following steps: Generate a reference modulation voltage waveform, determine the number of sub-modules to be engaged in the upper and lower bridge arms based on the reference modulation voltage waveform, and construct the MMC system; Based on the constructed MMC system and its self-balancing control characteristics, the average switching frequency of the sub-modules is obtained; Calculate the duration of each level, obtain the number of row vectors for each level based on the average switching frequency of the submodule, and construct a full-rank switching state matrix at different time scales. Determine the self-balancing control effect of submodule capacitor voltage under different row vector compositions and sequences; While ensuring the self-balancing of the submodule capacitor voltage on the given time scale, a switching state matrix that can reduce the switching frequency of submodules is constructed based on the number of submodules engaged in the upper and lower bridge arms. ; The average switching frequency of the derivation submodule is obtained according to the following formula: In the formula: The average switching frequency, To control the frequency, The number of submodule state transitions within a unit control cycle. For power frequency cycle, This represents the total number of bridge arm sub-modules. The end time of each level is the start time of the next level. for: Substituting the system parameters into the above formula allows for calculation. This allows us to calculate the duration of each level. The duration of each row vector is This allows us to calculate the number of row vectors at each level; Will Divided into Each sub-matrix is ​​calculated and constructed for different voltage levels, and then combined to obtain a result that reduces the switching frequency of the sub-modules. : , This represents the submatrix corresponding to each level.

2. The modular multilevel converter submodule switching frequency reduction optimization method according to claim 1, characterized in that, against In a level-controlled MMC system, at any given moment, the total number of submodules engaged in the upper and lower arms of each phase satisfies dynamic balance, and the sum of the capacitor voltages of the submodules equals the DC-side voltage, i.e.: In the formula, These represent the number of sub-modules required for the upper and lower bridge arms, respectively. This represents the theoretical steady-state value of the capacitor voltage in the submodule. , This represents the total number of bridge arm sub-modules. This is the DC side voltage.

3. The modular multilevel converter submodule switching frequency reduction optimization method according to claim 2, characterized in that, against The level-controlled MMC system uses Nearest Level Approximation Modulation (NLM) for modulation. The number of submodules required for the upper bridge arm is calculated based on the theoretical steady-state values ​​of the AC output voltage and the submodule capacitor voltage. : In the formula, This is the AC side output voltage.

4. The modular multilevel converter submodule switching frequency reduction optimization method according to claim 1, characterized in that, In step 3, using the power frequency control cycle as a reference, full-rank parameters at different time scales are constructed within one power frequency control cycle. .

5. The modular multilevel converter submodule switching frequency reduction optimization method according to claim 1, characterized in that, When the term of office is completed: .

6. The modular multilevel converter submodule switching frequency reduction optimization method according to claim 1, characterized in that, For the switching state matrix , 1) When : 2) When : 3) When and Odd number: In the formula, for A 0 / 1 matrix, whose row vectors represent When each submodule is activated, the switching state is such that the sum of the elements in each row equals... , for forward A matrix composed of rows, for After A matrix composed of rows, a matrix Calculated and composed according to the following rules: In the formula, , and All are A triangular matrix; 4) When and If the number is even: Choose any row from the original row vectors of the switching state matrix that matches the number of upper and lower arm switches, and replace all existing row vectors for self-balancing control. All row vectors are identical.

7. A system, characterized in that, include The first module is configured to generate a reference modulation voltage waveform, determine the number of sub-modules to be engaged in the upper and lower bridge arms based on the reference modulation voltage waveform, and build the MMC system. The second module is configured to obtain the average switching frequency of the sub-modules based on the constructed MMC system and self-balancing control characteristics. The third module is configured to calculate the duration of each level, obtain the number of row vectors for each level based on the average switching frequency of the submodules, and construct a full-rank switching state matrix at different time scales. Determine the self-balancing control effect of submodule capacitor voltage under different row vector compositions and sequences; The fourth module is configured to construct a switching state matrix that reduces the switching frequency of submodules, based on the number of submodules engaged in the upper and lower bridge arms, while ensuring self-balancing of the submodule capacitor voltages over a timescale. ; The average switching frequency of the derivation submodule is obtained according to the following formula: In the formula: The average switching frequency, To control the frequency, The number of submodule state transitions within a unit control cycle. For power frequency cycle, This represents the total number of bridge arm sub-modules. The end time of each level is the start time of the next level. for: Substituting the system parameters into the above formula allows for calculation. This allows us to calculate the duration of each level. The duration of each row vector is This allows us to calculate the number of row vectors at each level; Will Divided into Each sub-matrix is ​​calculated and constructed for different voltage levels, and then combined to obtain a result that reduces the switching frequency of the sub-modules. : , This represents the submatrix corresponding to each level.

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