A level shifting method and apparatus

Abstract

The application discloses a level conversion method and device. An enable control module is arranged, so that when the power supply voltage is not too high and the target voltage is too low, the level conversion module can be controlled to perform level conversion, and when the power supply voltage is too high, the level conversion module can be controlled to stop performing level conversion. In this way, on the one hand, the risk of the target voltage being too high after conversion can be avoided; on the other hand, when the target voltage is too low, the level conversion device can be prevented from being locked, so that the level conversion module can continue to perform level conversion, thereby improving the target voltage.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and more particularly to a level conversion method and apparatus. Background Technology

[0002] When devices or chips are switched on and off, a high input voltage often appears at the input terminal. This instantaneous operational overvoltage is called a surge voltage, which is a type of transient interference. If this surge voltage is input into a device or chip, it can cause performance degradation or even damage to the device or chip. Summary of the Invention

[0003] This invention provides a level conversion method and apparatus that can stop the level conversion process when the power supply voltage is too high, thereby preventing the converted voltage from being too high and damaging subsequent circuits. Thus, while achieving level conversion, it can also prevent the output voltage from being too high, reducing risks.

[0004] In a first aspect, embodiments of the present invention provide a level conversion device, including: a level conversion module, a reference voltage module, and an enable control module;

[0005] The reference voltage module is used for:

[0006] Based on the target voltage output by the level conversion module, a first reference signal is output to both the level conversion module and the enable control module.

[0007] The enabling control module is used for:

[0008] Based on the first reference signal, a second reference signal is output to the level conversion module; when it is determined that the power supply voltage provided by the power supply terminal meets the first preset condition, a first enable signal is output to the level conversion module; when it is determined that the target voltage meets the second preset condition, a second enable signal is output to the level conversion module; wherein, the first preset condition includes: the power supply voltage does not exceed the first preset value, and / or the rise rate of the power supply voltage when the level conversion device is started does not exceed the preset rate; the second preset condition includes: the target voltage is less than the second preset value;

[0009] The level conversion module is used for:

[0010] Under the control of the first enable signal or the second enable signal, the power supply voltage is converted into the target voltage according to the first reference signal and / or the second reference signal.

[0011] Secondly, embodiments of the present invention provide a level conversion method, including:

[0012] The enable control module outputs a second reference signal to the level conversion module based on a first reference signal; when it determines that the power supply voltage provided by the power supply terminal meets a first preset condition, it outputs a first enable signal to the level conversion module; when it determines that the target voltage meets a second preset condition, it outputs a second enable signal to the level conversion module; wherein, the first preset condition includes: the power supply voltage does not exceed a first preset value, and / or the rise rate of the power supply voltage when the level conversion device is started does not exceed a preset rate; the second preset condition includes: the target voltage is less than a second preset value;

[0013] Under the control of the first enable signal or the second enable signal, the level conversion module converts the power supply voltage into the target voltage according to the first reference signal and / or the second reference signal.

[0014] The reference voltage module outputs the first reference signal to the level conversion module and the enable control module respectively, based on the target voltage.

[0015] The beneficial effects of this invention are as follows:

[0016] The present invention provides a level conversion method and apparatus. By setting an enable control module, the level conversion module can be controlled to perform level conversion when the power supply voltage is not too high and the target voltage is too low. When the power supply voltage is too high, the level conversion module can be controlled to stop performing level conversion. In this way, on the one hand, the target voltage after conversion can be avoided from being too high, reducing the risk; on the other hand, when the target voltage is too low, the level conversion device can be prevented from locking up, allowing the level conversion module to continue performing level conversion to increase the target voltage. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a level conversion device in the prior art;

[0018] Figure 2 This is a schematic diagram of the structure of a level conversion device provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of another level conversion device provided in an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the structure of another level conversion device provided in an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the structure of a rising edge comparator subunit provided in an embodiment of the present invention;

[0022] Figure 6This is a schematic diagram of another level conversion device provided in an embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of the structure of a voltage comparator subunit provided in an embodiment of the present invention;

[0024] Figure 8 This is a schematic diagram of another level conversion device provided in an embodiment of the present invention;

[0025] Figure 9 This is a schematic diagram of the structure of a first subunit provided in an embodiment of the present invention;

[0026] Figure 10 This is a schematic diagram of the structure of a second subunit provided in an embodiment of the present invention;

[0027] Figure 11 This is a schematic diagram of the structure of a level conversion module provided in an embodiment of the present invention;

[0028] Figure 12 This is a flowchart of a level conversion method provided in an embodiment of the present invention. Detailed Implementation

[0029] The specific implementation of a level conversion method and apparatus provided by the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0030] The inventors discovered during their research that, for example Figure 1 As shown, the current level conversion device m1 includes: a reference voltage module 10 and a level conversion module 20; wherein, the reference voltage module 10 is electrically connected to the power supply terminal VIN and the level conversion module 20 respectively, and the reference voltage module 10 is used to: output a reference signal S0 to the level conversion module 20 according to the power supply voltage provided by the power supply terminal VIN; the level conversion module 20 is also electrically connected to the power supply terminal VIN and the electrical device m2 respectively, and the level conversion module 20 is used to: convert the power supply voltage into a target voltage SVCC according to the reference signal S0, and output the target voltage SVCC to the electrical device m2.

[0031] If the power supply voltage is too high for some reason, the following problems may occur:

[0032] 1. The reference voltage module is unstable due to excessively high power supply voltage, causing it to malfunction.

[0033] 2. The target voltage output by the level conversion module may be too high, causing the electrical equipment to receive an excessively high target voltage, which may damage the electrical equipment.

[0034] Based on this, embodiments of the present invention provide a level conversion device to avoid excessively high output target voltage.

[0035] Specifically, the level conversion device m1 provided in the embodiments of the present invention, such as Figure 2 As shown, it may include: a level conversion module 20, a reference voltage module 10, and an enable control module 30;

[0036] The reference voltage module 10 is used for:

[0037] Based on the target voltage (e.g., SVCC) output by the level conversion module 20, a first reference signal (e.g., S1) is output to both the level conversion module 20 and the enable control module 30.

[0038] The enabling control module 30 is used for:

[0039] Based on the first reference signal S1, a second reference signal (e.g., S2) is output to the level conversion module 20; when it is determined that the power supply voltage (also represented by VIN) provided by the power supply terminal (e.g., VIN) meets the first preset condition, a first enable signal (e.g., EN1) is output to the level conversion module 20; when it is determined that the target voltage (e.g., SVCC) meets the second preset condition, a second enable signal (e.g., EN2) is output to the level conversion module 20; wherein, the first preset condition includes: the power supply voltage VIN does not exceed the first preset value, and / or the rise rate of the power supply voltage VIN does not exceed the preset rate when the level conversion device m1 is started; the second preset condition includes: the target voltage SVCC is less than the second preset value;

[0040] The level conversion module 20 is used for:

[0041] Under the control of the first enable signal EN1 or the second enable signal EN2, the power supply voltage VIN is converted into the target voltage SVCC according to the first reference signal S1 and / or the second reference signal S2.

[0042] The second preset value can be used to determine whether the target voltage is too low. That is, if the target voltage is less than the second preset value, it means that the target voltage is too low. The first preset value can be used to determine whether the power supply voltage is too high. That is, if the power supply voltage exceeds the first preset value, it means that the power supply voltage is too high. Furthermore, a further determination that the target voltage is too low is that the second preset value is less than the first preset value. The first and second preset values ​​can be set according to actual needs and are not limited here.

[0043] By setting an enable control module, the level conversion module can be controlled to perform level conversion when the power supply voltage is not too high or the target voltage is too low. Conversely, when the power supply voltage is too high, the level conversion module can be controlled to stop performing level conversion. In this way, on the one hand, the target voltage after conversion can be avoided from being too high, reducing the risk; on the other hand, when the target voltage is too low (the reasons for this may include: the load (which can also be regarded as electrical equipment) connected to the level conversion device experiencing large fluctuations or short circuits, etc.), the level conversion device can be prevented from locking up, allowing the level conversion module to continue performing level conversion to increase the target voltage.

[0044] I. The following section introduces the specific structure of the enable control module.

[0045] Optionally, in embodiments of the present invention, such as Figure 3 As shown, the enable control module 30 includes: an enable unit 32 and a comparison unit 31;

[0046] The comparison unit 31 is electrically connected to the power supply terminal VIN and the enable unit 32 respectively, and the comparison unit 31 is used for:

[0047] When it is determined that the power supply voltage VIN meets the first preset condition, an indication signal is output to the enable unit 32.

[0048] The enabling unit 32 is also electrically connected to the reference voltage module 10 and the level conversion module 20, respectively, and the enabling unit 32 is used for:

[0049] When it is determined that the target voltage SVCC meets the second preset condition, the second enable signal EN2 is output to the level conversion module 20; when it is determined that the target voltage SVCC does not meet the second preset condition and the indication signal is received, the first enable signal EN1 is output to the level conversion module 20; and the second reference signal S2 is output to the level conversion module 20 according to the first reference signal S1.

[0050] Among them, combined Figure 3 As shown, k can be understood as: a signal consisting of high and low levels sent by the comparison unit 31 to the enable unit 32;

[0051] If k is low, it indicates that an output indicator signal is being output; if k is high, it indicates that no indicator signal is being output.

[0052] Alternatively, it can be set such that if k is high, it indicates that an output indicator signal is being output; if k is low, it indicates that no indicator signal is being output.

[0053] The specific form of the indicator signal can be set according to actual needs and is not limited here.

[0054] Thus, the comparison unit can determine whether the power supply voltage meets the first preset condition. When the first preset condition is met (i.e., the power supply voltage is not too high and / or the rise rate is not too fast), an indication signal is output to the enable unit. This allows the enable unit to output a first enable signal when it determines that the target voltage does not meet the second preset condition and receives the indication signal. At the same time, the enable unit outputs a second enable signal when it determines that the target voltage meets the second preset condition (i.e., the target voltage is too low during or after startup).

[0055] 1.1 The specific structure of the comparison unit will be introduced below.

[0056] In specific implementation, in the embodiments of the present invention, the specific structure of the comparison unit may include the following configuration methods:

[0057] Method 1: The comparison unit only includes the rising edge comparison sub-unit.

[0058] Optionally, in embodiments of the present invention, such as Figure 4 As shown, the first preset condition includes: when the level conversion device is started, the rise rate of the power supply voltage does not exceed the preset rate, and the comparison unit 31 includes a rising edge comparison subunit 31a;

[0059] The rising edge comparison subunit 31a is electrically connected to the enable unit 32 and the power supply terminal VIN, respectively. The rising edge comparison subunit 31a is used for:

[0060] When the rise rate of the power supply voltage VIN does not exceed the preset rate when the level conversion device is started, the indicator signal is output to the enable unit 32.

[0061] In this way, the rising edge comparison sub-unit can be used to determine whether the rising rate of the power supply voltage exceeds the preset rate, and then determine whether the rising rate of the power supply voltage is too fast, thereby determining when to output an indication signal and when not to output an indication signal.

[0062] It is important to emphasize that since the rising edge comparator determines the rise rate of the power supply voltage, it can achieve a fast response and detect that the power supply voltage is too high as early as possible, avoiding the target voltage from being too high due to slow response speed, thereby improving the speed of determining whether the target voltage is too high.

[0063] Optionally, in embodiments of the present invention, such as Figure 5 As shown, the rising edge comparison subunit includes: a delay circuit a1, a difference setting circuit a2, and a first comparator a3;

[0064] The first input terminal of the first comparator a3 is electrically connected to the output terminal of the delay circuit a1, the second input terminal is electrically connected to the output terminal of the difference setting circuit a2, and the output terminal is electrically connected to the enable unit 32.

[0065] The input terminal of the delay circuit a1 is electrically connected to the power supply terminal VIN;

[0066] The input terminal of the differential setting circuit a2 is electrically connected to the power supply terminal VIN.

[0067] The delay circuit can generate a certain voltage drop (denoted as voltage drop 1), and the differential setting circuit also has a certain voltage drop (denoted as voltage drop 2). By judging the relationship between voltage drop 1 and voltage drop 2 by the first comparator, it can be determined whether the current power supply voltage rise rate is too fast, so that the first comparator can determine whether to output an indication signal based on the judgment result.

[0068] Optionally, in embodiments of the present invention, such as Figure 5 As shown, the delay circuit a1 may include a first resistor R1 and a first capacitor C1 connected in series between the power supply terminal VIN and the ground terminal GND.

[0069] The specific structure of the delay circuit is not limited to Figure 5 As shown, other structures that can implement the delay circuit function can also be used, and are not limited here.

[0070] like Figure 5 As shown, the differential setting circuit a2 may include: a first transistor MP1, a second transistor MP2, and a third transistor MP3; wherein the connection relationship between the first transistor MP1 and the third transistor MP3 can be as follows: Figure 5 As shown, it will not be elaborated further here;

[0071] Furthermore, the first transistor MP1 to the third transistor MP3 can all be P-type transistors, or they can all be N-type transistors. The specific configuration can be set according to actual needs and is not limited here.

[0072] Furthermore, the specific structure of the differential setting circuit is not limited to... Figure 5 As shown, other structures that can achieve the function of differential setting circuits can also be used, and are not limited here.

[0073] like Figure 5As shown, the first comparator a3 may include: a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MP6, a seventh transistor MP7, an eighth transistor MN8, a ninth transistor MN9, a tenth transistor MN10, and an eleventh transistor MN11; wherein the connection relationship between the fourth transistor MP4 and the eleventh transistor MN11 can be as follows: Figure 5 As shown, it will not be elaborated further here.

[0074] Furthermore, the fourth transistor MP4 to the seventh transistor MP7 can all be P-type transistors, and the eighth transistor MN8 to the eleventh transistor MN11 can all be N-type transistors; or, the fourth transistor MP4 to the seventh transistor MP7 can all be N-type transistors, and the eighth transistor MN8 to the eleventh transistor MN11 can all be P-type transistors; the specific configuration can be set according to actual needs and is not limited here.

[0075] Furthermore, the specific structure of the first comparator is not limited to... Figure 5 As shown, other structures that can implement the function of the first comparator can also be used, and are not limited here.

[0076] It should be noted that, optionally, in combination Figure 5 As shown in the structure, if the rise rate of the power supply voltage VIN exceeds the preset rate, the voltage drop of the delay circuit a1 is less than the difference between the power supply voltage VIN and the voltage drop of the differential setting circuit a2, and no indication signal will be output at this time.

[0077] The voltage drop of the differential setting circuit can be expressed as: Vgs MP1 +Vgs MP2 +Vgs MP3 Among them, Vgs MP1 Vgs represents the difference between the gate and source of the first transistor MP1. MP2 Vgs represents the difference between the gate and source of the second transistor MP2. MP3 This represents the difference between the gate and source of the third transistor MP3.

[0078] It should be noted that, in combination Figure 5 As shown, the first bias voltage VB1 can be understood as a bias voltage with nanoampere-level driving capability. This allows the branch containing the sixth transistor MP6 and the seventh transistor MP7 to have only nanoampere-level power consumption, thus enabling the rising edge comparator subunit to also achieve low power consumption.

[0079] Method 2: The comparison unit only includes a voltage comparison subunit.

[0080] Optionally, in this embodiment of the invention, the first preset condition includes: the power supply voltage does not exceed the first preset value, and the comparison unit includes a voltage comparison subunit;

[0081] The voltage comparison subunit is electrically connected to the enable unit, the power supply terminal, and the reference voltage module, respectively. The voltage comparison subunit is used for:

[0082] Based on the power supply voltage and the first reference signal, when it is determined that the power supply voltage does not exceed the first preset value, the indicator signal is output to the enabling unit.

[0083] In this way, the voltage comparison subunit can determine whether the power supply voltage exceeds the first preset value, that is, whether the power supply voltage is too high, thereby determining when to output an indication signal and when not to output an indication signal.

[0084] Optionally, in embodiments of the present invention, such as Figure 7 As shown, the voltage comparison subunit 31b includes: a low-power comparison circuit b1, a precise comparison circuit b2, and a logic circuit b3;

[0085] The low-power comparator circuit b1 is electrically connected to the power supply terminal VIN, the logic circuit b3, and the reference voltage module, respectively. The low-power comparator circuit b1 is used for:

[0086] When it is determined, based on the power supply voltage VIN and the first reference signal S1, that the power supply voltage VIN has not exceeded the first preset value, a first indication signal is output to the logic circuit b3.

[0087] The precise comparison circuit b2 is electrically connected to the power supply terminal VIN, the reference voltage terminal Vref, and the logic circuit b3, respectively. The precise comparison circuit b2 is used for:

[0088] When it is determined, based on the power supply voltage VIN and the reference voltage provided by the reference voltage terminal Vref, that the power supply voltage VIN has not exceeded the first preset value, a second indication signal is output to the logic circuit b3.

[0089] The logic circuit b3 is used for:

[0090] Upon receiving the first indication signal and the second indication signal, the indication signal is output.

[0091] In method 2, for Figure 7 The relationship between k and the indicator signal shown in the figure can be found in the description of k and the indicator signal above, and will not be elaborated here.

[0092] To clarify, k21 can also be understood as: the signal output by the low-power comparator circuit b1 to the logic circuit b3, consisting of low and high levels; similarly, k22 can also be understood as: the signal output by the precise comparator circuit b2 to the logic circuit b3, consisting of low and high levels.

[0093] Wherein, when k21 is low, it can indicate that the first indicator signal is output; when k21 is high, it can indicate that no first indicator signal is output. Alternatively, when k21 is high, it can indicate that the first indicator signal is output; when k21 is low, it can indicate that no first indicator signal is output.

[0094] When k22 is low, it indicates that the first indicator signal is output; when k22 is high, it indicates that there is no first indicator signal output. Alternatively, when k22 is high, it indicates that the first indicator signal is output; when k22 is low, it indicates that there is no first indicator signal output.

[0095] The specific settings for the first and second indicator signals can be configured according to actual needs and are not limited here.

[0096] Furthermore, the reference voltage terminal can be a signal provided by the reference voltage module, or it can be provided by other devices in the system including the level conversion device, which is not limited here.

[0097] In this way, by setting up low-power comparator circuits and precise comparator circuits, it is possible to avoid excessively high output target voltage while maintaining low power consumption. At the same time, it is also possible to improve the accuracy of judging whether the target voltage is too high, thereby achieving precise control and reducing the probability of false alarms.

[0098] Optionally, in embodiments of the present invention, such as Figure 7 As shown, the low-power comparison circuit b1 includes a second comparator Q2, and the precise comparison circuit b2 includes a third comparator Q3;

[0099] The first input terminal of the second comparator Q2 is electrically connected to the power supply terminal VIN, the second input terminal is electrically connected to the reference voltage module, and the output terminal is electrically connected to the logic circuit b3.

[0100] The first input terminal of the third comparator Q3 is electrically connected to the power supply terminal VIN, the second input terminal is electrically connected to the reference voltage terminal Vref, and the output terminal is electrically connected to the logic circuit b3.

[0101] The logic circuit b3 includes a logic OR Q1.

[0102] The specific structural settings of the second and third comparators can be configured according to actual needs, as long as they can achieve the functions of the second and third comparators, and are not limited here.

[0103] Thus, with a simple structural setup, the functions of low-power comparator circuits, precise comparator circuits, and logic circuits can be achieved. While avoiding excessively high target voltages, this also helps to reduce the manufacturing cost of level conversion devices.

[0104] Of course, it should be noted that, in addition to being directly connected to the power supply, the first input terminal of the third comparator can also be configured as follows:

[0105] The first input terminal of the third comparator can be electrically connected to the power supply terminal through a voltage divider circuit, so that the signal received by the first input terminal of the third comparator is a voltage divider signal of the power supply signal.

[0106] The voltage divider circuit may include voltage divider resistors.

[0107] The connection method between the first input terminal and the power supply terminal of the third comparator can be set according to actual needs and is not limited here.

[0108] Method 3: The comparison unit includes a rising edge comparison subunit and a voltage comparison subunit.

[0109] Optionally, in embodiments of the present invention, such as Figure 6 As shown, when the first preset conditions include: the power supply voltage does not exceed the first preset value and the rise rate of the power supply voltage does not exceed the preset rate when the level conversion device is started, the comparison unit 31 includes: rising edge comparison subunit 31a and voltage comparison subunit 31b.

[0110] The connection relationships and specific structures of the rising edge comparator subunit and the voltage comparator subunit with other structures are similar to those in the aforementioned methods 1 and 2. For details, please refer to the aforementioned content, which will not be elaborated here.

[0111] It should be noted that in this method 3, in order to facilitate the distinction between the indicator signals output by the two sub-units, the indicator signal output by the rising edge comparison sub-unit can be defined as indicator signal 1, and the indicator signal output by the voltage comparison sub-unit can be defined as indicator signal 2.

[0112] At this point, for the enabling unit:

[0113] When it is determined that the target voltage SVCC does not meet the second preset condition, and both indication signal 1 and indication signal 2 are received simultaneously, the first enable signal is output to the level conversion module.

[0114] Among them, such as Figure 6 As shown, k1 can be understood as a signal consisting of low and high levels sent by the rising edge comparison unit 31a to the enable unit 32; wherein, when k1 is low, it can represent output indicator signal 1, and when k1 is high, it can represent no indicator signal 1 output; or, when k1 is high, it can represent output indicator signal 1, and when k1 is low, it can represent no indicator signal 1 output.

[0115] Similarly, k2 can be understood as a signal consisting of low and high levels sent by the voltage comparison subunit 31b to the enable unit 32; where, when k2 is low, it can indicate the output of indicator signal 2, and when k2 is high, it can indicate that no indicator signal 2 is output; or, when k2 is high, it can indicate the output of indicator signal 2, and when k2 is low, it can indicate that no indicator signal 2 is output.

[0116] The specific settings for indicator signal 1 and indicator signal 2 can be configured according to actual needs and are not limited here.

[0117] In summary, the specific structure of the comparison unit can be configured according to the actual application scenario, such as, but not limited to:

[0118] If the application scenario is a low-power scenario, it can be set as follows: the comparison unit includes a rising edge comparison subunit and a voltage comparison subunit;

[0119] Alternatively, if the application scenario is a fast response scenario, it can be set as follows: the comparison unit includes a rising edge comparison subunit;

[0120] Alternatively, if the application scenario is a precise control scenario, it can be set as follows: the comparison unit includes a voltage comparison subunit.

[0121] 1.2 The specific structure of the enabling unit will be described below.

[0122] Optionally, in embodiments of the present invention, such as Figure 8 As shown, the enabling unit 32 includes: a first subunit 32c and a second subunit 32d;

[0123] The first subunit 32c is electrically connected to the reference voltage module 10, the level conversion module 20, and the second subunit 32d, respectively. The first subunit 32c is used for:

[0124] Based on the first reference signal S1, the second reference signal S2 is output to the level conversion module 20, and a reset signal Reset is output to the second subunit 32d;

[0125] The second subunit 32d is also electrically connected to the comparison unit 31 and the level conversion module 20, respectively. The second subunit 32d is used for:

[0126] When it is determined that the target voltage SVCC does not meet the second preset condition and the indication signal is received, the first enable signal EN1 is output; when it is determined that the target voltage SVCC meets the second preset condition and the reset signal Reset is received, the second enable signal EN2 is output.

[0127] In this way, the function of the enable unit can be realized through the cooperation of the first subunit and the second subunit. When the power supply voltage is too high and may cause the target voltage to be too high, the level conversion module can be controlled to stop the level conversion process to avoid damage to the downstream electrical equipment. At the same time, when the target voltage is too low, the level conversion module can be guaranteed to work normally to avoid lock-up.

[0128] Optionally, in embodiments of the present invention, such as Figure 9 As shown, the first sub-unit includes: a reference signal generation circuit c1 and a reset signal generation circuit c2;

[0129] The reference signal generation circuit c1 is electrically connected to the reference voltage module and the level conversion module, respectively.

[0130] The reset signal generation circuit c2 is electrically connected to the reference signal generation circuit c1 and the second sub-unit, respectively.

[0131] Among them, such as Figure 9 As shown, the first reference signal can be represented by LPVR, and the reset signal can be represented by Reset;

[0132] The second reference signal may include an anti-lock-up reference voltage VRS and a first bias voltage VB1. Of course, the setting of the second reference signal is not limited to including the anti-lock-up reference voltage VRS and the first bias voltage VB1. It can also be set to other forms according to actual needs. This is just an example of the second reference signal including the anti-lock-up reference voltage VRS and the first bias voltage VB1. It is not limited here.

[0133] Thus, the reference signal generation circuit can output a second reference signal based on the first reference signal, and the reset signal generation circuit can output a reset signal based on the signal output by the reference signal generation circuit.

[0134] Specifically, in embodiments of the present invention, such as Figure 9As shown, the reference signal generation circuit c1 may include: twelfth transistor MP12, thirteenth transistor MP13, fourteenth transistor MP14, fifteenth transistor MN15, sixteenth transistor MP16, seventeenth transistor MN17, eighteenth transistor MN18, nineteenth transistor MP19, twentieth transistor MP20, twenty-first transistor MP21, and twenty-second transistor MN22; wherein, the connection relationship of the twelfth transistor MP12 to the twenty-second transistor MP22 can be as follows: Figure 9 As shown, it will not be elaborated further here.

[0135] Furthermore, transistors MP12 through MP14, MP16, MP19 through MP21 can all be P-type transistors, while transistors MN15, MN17, MN18, and MN22 can all be N-type transistors; or, transistors MP12 through MP14, MP16, MP19, MP21 can all be N-type transistors, while transistors MN15, MN17, MN18, and MN22 can all be P-type transistors. The specific configuration can be determined according to actual needs and is not limited here.

[0136] Furthermore, the specific structure of the reference signal generation circuit is not limited to... Figure 9 As shown, other structures that can realize the function of reference signal generation circuits can also be used, and are not limited here.

[0137] Specifically, in embodiments of the present invention, such as Figure 9 As shown, the reset signal generation circuit c2 may include: the twenty-third transistor MP23, the twenty-fourth transistor MN24, the twenty-fifth transistor MN25, and the twenty-sixth transistor MN26; wherein, the connection relationship between the twenty-third transistor MP23 and the twenty-sixth transistor MN26 can be as follows: Figure 9 As shown, it will not be elaborated further here.

[0138] Furthermore, the twenty-third transistor MP23 can be a P-type transistor, and the twenty-fourth transistor MN24 to the twenty-sixth transistor MN26 can all be N-type transistors; or, the twenty-third transistor MP23 can be an N-type transistor, and the twenty-fourth transistor MN24 to the twenty-sixth transistor MN26 can all be P-type transistors; the specific settings can be configured according to actual needs and are not limited here.

[0139] Furthermore, the specific structure of the reset signal generation circuit is not limited to... Figure 9As shown, other structures that can realize the function of the reset signal generation circuit can also be used, and are not limited here.

[0140] Optionally, in embodiments of the present invention, such as Figure 10 As shown, the second subunit includes: an enable signal output circuit d1, a reset signal control circuit d2, and an indicator signal control circuit d3;

[0141] The enable signal output circuit d1 is electrically connected to the reset signal control circuit d2, the indicator signal control circuit d3, and the level conversion module, respectively.

[0142] The reset signal control circuit d2 is electrically connected to the first sub-unit;

[0143] The indicator signal control circuit d3 is electrically connected to both the comparison unit and the level conversion module.

[0144] Among them, the reset signal control circuit can be controlled by the reset signal, so that when the indicator signal control circuit fails to work due to the target voltage being too low, the reset signal control circuit can output a control signal to the enable signal output circuit, so that the enable signal output circuit can output the second enable signal normally, thereby ensuring that the level conversion module can perform the level conversion process.

[0145] The indicator signal control circuit can be controlled by an indicator signal (when the comparison unit only includes a rising edge comparison subunit, the indicator signal is the indicator signal output by the rising edge comparison subunit; when the comparison unit only includes a voltage comparison subunit, the indicator signal is the indicator signal output by the voltage comparison subunit; when the comparison unit includes both a rising edge comparison subunit and a voltage comparison subunit, the indicator signal includes indicator signal 1 and indicator signal 2 mentioned above) and the target voltage. When the target voltage is greater than the second preset value, if the indicator signal is received, a control signal is output to the enable signal output circuit, so that the enable signal output circuit can normally output the first enable signal, thereby ensuring that the level conversion module can perform the level conversion process.

[0146] Optionally, in embodiments of the present invention, such as Figure 10 As shown, the indicator signal control circuit d3 may include: the twenty-seventh transistor MN27, the twenty-eighth transistor MN28, the twenty-ninth transistor MN29, and a logic inverter f; wherein, the connection relationship between the twenty-seventh transistor MN27 to the twenty-ninth transistor MN29 and the logic inverter f can be as follows: Figure 10 As shown, it will not be elaborated further here.

[0147] Furthermore, transistors MN27 to MN29 can all be N-type transistors, or transistors MN27 to MN29 can all be P-type transistors; the specific configuration can be determined according to actual needs and is not limited here.

[0148] Furthermore, the specific structure of the indicator signal control circuit is not limited to... Figure 10 As shown, other structures that can realize the function of indicator signal control circuits can also be used, and are not limited here.

[0149] Optionally, in embodiments of the present invention, such as Figure 10 As shown, the reset signal control circuit d2 may include: a thirtieth transistor MN30 and a second resistor R2. The connection relationship between the thirtieth transistor MN30 and the second resistor R2 can be as follows: Figure 10 As shown, it will not be elaborated further here.

[0150] Furthermore, the thirtieth transistor MN30 can be either an N-type transistor or a P-type transistor, depending on actual needs, and is not limited here.

[0151] Furthermore, the specific structure of the reset signal control circuit is not limited to... Figure 10 As shown, other structures that can implement the reset signal control circuit function can also be used, and are not limited here.

[0152] Optionally, in embodiments of the present invention, such as Figure 10 As shown, the enable signal output circuit d1 may include: the thirty-first transistor MP31 and the thirty-second transistor MP32; wherein, the connection relationship between the thirty-first transistor MP31 and the thirty-second transistor MP32 can be as follows: Figure 10 As shown, it will not be elaborated further here.

[0153] Furthermore, the thirty-first transistor MP31 and the thirty-second transistor MP32 can be either P-type or N-type transistors, depending on actual needs, and are not limited here.

[0154] Furthermore, the specific structure of the enable signal output circuit is not limited to... Figure 10 As shown, other structures that can realize the function of the enable signal output circuit can also be used, and are not limited here.

[0155] II. The specific structure of the level conversion module is described below.

[0156] Optionally, in this embodiment of the invention, the level conversion module is specifically used for:

[0157] Upon receiving the second enable signal, the power supply voltage is converted into the target voltage according to the second reference signal;

[0158] Upon receiving the first enable signal, the power supply voltage is converted into the target voltage based on the first reference signal.

[0159] In this way, it can be ensured that the level conversion module can perform the level conversion process normally when it receives the first enable signal or the second enable signal, thereby providing power to the downstream electrical equipment normally.

[0160] Optionally, in embodiments of the present invention, such as Figure 11 As shown, the level conversion module may include: the thirty-third transistor MP33, the thirty-fourth transistor MP34, the thirty-fifth transistor MP35, the thirty-sixth transistor MP36, the thirty-seventh transistor MP37, the thirty-eighth transistor MN38, the thirty-ninth transistor MN39, the fortieth transistor MN40, the forty-first transistor MN41, the forty-second transistor MN42, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the second capacitor C2;

[0161] The connection relationships of transistors MP33 to MN42 (the 33rd transistor), resistors R3 to R5 (the 5th resistor), and capacitor C2 can be described as follows: Figure 11 As shown, it will not be elaborated further here.

[0162] Furthermore, transistors MP33 to MP37 can all be P-type transistors, and transistors MN38 to MN42 can all be N-type transistors; or, transistors MP33 to MP37 can all be N-type transistors, and transistors MN38 to MN42 can all be P-type transistors. The specific configuration can be set according to actual needs and is not limited here.

[0163] Furthermore, the structure of the level conversion module is not limited to... Figure 11 As shown, other structures that can implement the level conversion module function can also be used, and are not limited here.

[0164] III. The specific structure of the reference voltage module will be described below.

[0165] Optionally, in the embodiments of the present invention, the specific implementation of the reference voltage module can be found in the prior art, and will not be described in detail here.

[0166] IV. The working process of the level conversion device will be described below with reference to specific embodiments.

[0167] Example: The structure of the first subunit is as follows Figure 9 As shown, the structure of the second subunit is as follows: Figure 10 As shown, the structure of the comparison unit is as follows: Figure 6 As shown, the first reference signal S1 includes LPVR (which can be understood as a low-power reference voltage) and VB2 (which can be understood as a second bias voltage), and the second reference signal S2 includes, for example, an anti-lock-up reference voltage VRS and a first bias voltage VB1.

[0168] It should be noted that, in the embodiments of the present invention, the specific implementation of the first reference signal and the second reference signal is not limited to the first reference signal S1 including the low-power reference voltage LPVR and the second bias voltage VB2, and the second reference signal S2 including the anti-lock-up reference voltage VRS and the first bias voltage VB1. This is only used as an example for illustration. The specific implementation of the first reference signal and the second reference signal can be set according to actual needs, and is not limited here.

[0169] Furthermore, the following assumptions are made: when node P2 is high, it indicates the output of the reset signal Reset; when node P2 is low, it indicates no reset signal Reset is output. During startup, if node P4 is high, it indicates the output of the second enable signal EN2; if node P4 is low, it indicates no output of the second enable signal EN2. After startup, if node P4 is high, it indicates the output of the first enable signal EN1; if node P4 is low, it indicates no output of the first enable signal EN1. If k1 is low, it indicates the output of indicator signal 1; if k1 is high, it indicates no output of indicator signal 1. If k2 is low, it indicates the output of indicator signal 2; if k2 is high, it indicates no output of indicator signal 2.

[0170] (1) At startup:

[0171] like Figure 6 As shown, when the level conversion device starts up, there is no level conversion process yet, so the target voltage SVCC is generally 0. Since the reference voltage module 10 generates a low-power reference voltage LPVR and a second bias voltage VB2 based on the target voltage SVCC, the low-power reference voltage LPVR and the second bias voltage VB2 output by the reference voltage module 10 are both 0 at this time.

[0172] like Figure 9As shown, when the low-power reference voltage LPVR is 0, the branch consisting of the twelfth transistor MP12, the thirteenth transistor MP13, the sixteenth transistor MP16, and the seventeenth transistor MN17 is turned on, outputting the first bias VB1; correspondingly, the branch consisting of the eighteenth transistor MN18 and the nineteenth transistor MP19 is turned on, and under the mirror effect of the nineteenth transistor MP19 and the twentieth transistor MP20, the potential of node P1 is pulled high, outputting the anti-lock-up reference voltage VRS;

[0173] Furthermore, under the mirror effect of the nineteenth transistor MP19 and the twenty-third transistor MP23, the potential of node P2 is pulled up. Since the low-power reference voltage LPVR is 0, the twenty-fourth transistor MN24 is turned off. As a result, the twenty-fourth transistor MN24 has no ability to pull down the potential of node P2, so node P2 is at a high level, that is, the reset signal Reset is output.

[0174] like Figure 10 As shown, when the gate of the thirtieth transistor MN30 is high, the thirtieth transistor MN30 is turned on, which pulls the potential of node P3 low, causing the thirty-first transistor MP31 to turn on, and node P4 to be high, i.e., outputting the second enable signal EN2. Since the target voltage SVCC is 0, the logic inverter f cannot work properly, which in turn makes both the input and output of the logic inverter f low, so the twenty-ninth transistor MN29 has no pull-down capability for node P3. That is to say, during startup, only the reset signal control circuit d2 is active, and the indicator signal control circuit d3 is temporarily inactive.

[0175] like Figure 6 As shown, for the comparison unit 31, at startup, when the rising edge comparison subunit determines that the rising rate of the power supply voltage does not exceed the preset rate, the output k1 is low, indicating that the output indicator signal 1 is output; under the control of the reset signal Reset, the voltage comparison subunit outputs k2 low, indicating that the output indicator signal 2 is output; at this time, combined with Figure 10 As shown, when k1 is low and k2 is also low, both the twenty-seventh transistor MN27 and the twenty-eighth transistor 28 are turned off, so that the indicator signal control circuit d3 is temporarily inactive.

[0176] For the level conversion module 20, when it receives the second enable signal EN2, it indicates that the current target voltage SVCC may be too low and a level conversion process needs to be performed to convert the power supply voltage VIN to the target voltage SVCC.

[0177] It should be noted that during this stage, since both the low-power reference voltage LPVR and the second bias voltage VB2 are 0, the level conversion module 20 can perform the level conversion process based on the anti-lock-up reference voltage VRS and the first bias voltage VB1.

[0178] (2) After startup:

[0179] like Figure 6 As shown, after the level conversion device receives the second enable signal EN2, the target voltage SVCC gradually increases. Since the reference voltage module 10 generates a low-power reference voltage LPVR and a second bias voltage VB2 based on the target voltage SVCC, the low-power reference voltage LPVR and the second bias voltage VB2 output by the reference voltage module 10 are both greater than 0, or may have reached a preset threshold.

[0180] like Figure 9 As shown, as the target voltage SVCC gradually increases, the voltage divider FB of the target voltage SVCC also increases, causing the fifteenth transistor MN15 to turn on, and then the fourteenth transistor MP14 to turn on, causing the drain voltage of the thirteenth transistor MP13 to decrease; and because the low-power reference voltage LPVR increases, the current in the branch containing the sixteenth transistor MP16 and the seventeenth transistor MN17 decreases to 0, thereby causing the first bias VB1 of the output to decrease or even decrease to 0; correspondingly, the current in the branch formed by the eighteenth transistor MN18 and the nineteenth transistor MP19 becomes 0, thereby causing the anti-lock-up reference voltage VRS of the output to also decrease or even decrease to 0;

[0181] Furthermore, since the current in the branch formed by the eighteenth transistor MN18 and the nineteenth transistor MP19 is 0, the twenty-third transistor MP23 has no pull-up capability for the potential of node P2. Due to the increase of the low-power reference voltage LPVR, the twenty-fourth transistor MN24 is turned on. At the same time, the voltage divider FB of the target voltage SVCC can control the twenty-fifth transistor MN25 to turn on, forming a pull-down capability for the potential of node P2. At this time, the potential of node P2 flips to a low level, so there is no reset signal Reset output.

[0182] like Figure 10As shown, when the gate of the thirtieth transistor MN30 is low, the thirtieth transistor MN30 is cut off, causing the reset signal control circuit d2 to have no effect. Since the target voltage SVCC is greater than 0, the logic inverted f can work normally. If k1 and k2 are both low, the twentieth transistor MN29 is turned on through the action of the logic inverted f, pulling down the potential of node P3, causing the thirtieth transistor MP31 to turn on, pulling the point of node P4 high, and outputting the first enable signal EN1. That is to say, after startup, the reset signal control circuit d2 has no effect, and the indicator signal control circuit d3 has an effect.

[0183] When the level conversion module 20 receives the first enable signal EN1, it indicates that the power supply voltage VIN is not too high, so it can continue to perform the level conversion process to convert the power supply voltage VIN to the target voltage SVCC.

[0184] like Figure 6 As shown, for the comparison unit 31, after startup, when the rising edge comparison subunit 31a determines that the rising rate of the power supply voltage VIN does not exceed the preset rate, the output k1 is low, indicating that the output indicator signal 1 is output; since there is no reset signal Reset, the voltage comparison subunit 31b is no longer controlled by the reset signal Reset, and when it determines that the power supply voltage VIN does not exceed the first preset value, the output k2 is low, indicating that the output indicator signal 2 is output; if it determines that the power supply voltage VIN exceeds the first preset value, the output k2 is high, indicating that no indicator signal 2 is output;

[0185] At this time, combined Figure 10 As shown, when k1 is low and k2 is high, the 27th transistor MN27 is cut off and the 28th transistor 28 is turned on, pulling down the potential of node P4 so that the potential of node P4 is low, i.e., there is no first enable signal EN1 output; thus, the level conversion module 20 stops performing the level conversion process when it does not receive the first enable signal EN1, avoiding the output of a high target voltage SVCC, and protecting the subsequent electrical equipment.

[0186] It should be noted that during this stage, since both the anti-lock-up reference voltage VRS and the first bias voltage VB1 are 0, the level conversion module can perform the level conversion process based on the low-power reference voltage LPVR and the second bias voltage VB2.

[0187] In other words, when the anti-lock-up reference voltage VRS and the first bias voltage VB1 are 0, the low-power reference voltage LPVR and the second bias voltage VB2 are not 0. Therefore, the level conversion module can perform the level conversion process according to the low-power reference voltage LPVR and the second bias voltage VB2.

[0188] When the low-power reference voltage LPVR and the second bias voltage VB2 are 0, the anti-lock-up reference voltage VRS and the first bias voltage VB1 are not 0. Therefore, the level conversion module can perform the level conversion process according to the anti-lock-up reference voltage VRS and the first bias voltage VB1.

[0189] Therefore, when the low-power reference voltage LPVR and the second bias voltage VB2 are used as the first reference signal, and the anti-lock-up reference voltage VRS and the first bias voltage VB1 are used as the second reference signal, the first reference signal and the second reference signal can alternately provide signals to the level conversion module so that the level conversion module can perform the level conversion process.

[0190] One point to note is that during normal operation after the level conversion device has started, if the target voltage SVCC fluctuates significantly due to some reason, resulting in the target voltage SVCC being too low, a process similar to (1) above can be performed to raise the target voltage SVCC, avoid the level conversion device from locking up, and thus ensure that the level conversion device can work normally.

[0191] Based on the same inventive concept, this invention provides a level conversion method. The implementation principle of this method is similar to that of the aforementioned level conversion device. For the specific implementation of this method, please refer to the specific embodiments of the aforementioned device. Repeated details will not be repeated.

[0192] Specifically, an embodiment of the present invention provides a level conversion method, such as... Figure 12 As shown, it may include:

[0193] S1201. The enable control module outputs a second reference signal to the level conversion module based on the first reference signal; when it is determined that the power supply voltage provided by the power supply terminal meets the first preset condition, it outputs a first enable signal to the level conversion module; when it is determined that the target voltage meets the second preset condition, it outputs a second enable signal to the level conversion module; wherein, the first preset condition includes: the power supply voltage does not exceed the first preset value, and / or the rise rate of the power supply voltage when the level conversion device is started does not exceed the preset rate; the second preset condition includes: the target voltage is less than the second preset value;

[0194] The second preset value can be used to determine whether the target voltage is too low. That is, if the target voltage is less than the second preset value, it means that the target voltage is too low. The first preset value can be used to determine whether the power supply voltage is too high. That is, if the power supply voltage exceeds the first preset value, it means that the power supply voltage is too high. Furthermore, a further determination that the target voltage is too low is that the second preset value is less than the first preset value. The first and second preset values ​​can be set according to actual needs and are not limited here.

[0195] S1202. Under the control of the first enable signal or the second enable signal, the level conversion module converts the power supply voltage into the target voltage according to the first reference signal and / or the second reference signal.

[0196] S1203, the reference voltage module outputs the first reference signal to the level conversion module and the enable control module respectively according to the target voltage.

[0197] Optionally, in this embodiment of the invention, under the control of the first enable signal or the second enable signal, the power supply voltage is converted into the target voltage according to the first reference signal and / or the second reference signal, specifically including:

[0198] Upon receiving the second enable signal, the power supply voltage is converted into the target voltage according to the second reference signal;

[0199] Upon receiving the first enable signal, the power supply voltage is converted into the target voltage based on the first reference signal.

[0200] Optionally, in this embodiment of the invention, when the enable control module includes an enable unit and a comparison unit, when it is determined that the power supply voltage provided by the power supply terminal meets a first preset condition, a first enable signal is output to the level conversion module; and when it is determined that the target voltage meets a second preset condition, a second enable signal is output to the level conversion module, specifically including:

[0201] When the comparison unit determines that the power supply voltage meets the first preset condition, it outputs an indication signal to the enable unit.

[0202] When the enabling unit determines that the target voltage meets the second preset condition, it outputs the second enabling signal; when it determines that the target voltage does not meet the second preset condition and receives the indication signal, it outputs the first enabling signal.

[0203] It should be emphasized that the technical solutions provided in the embodiments of the present invention have the following advantages:

[0204] 1. A level shifting device for overvoltage protection is proposed. The level shifting process is controlled by using multiple methods such as rising edge detection, low power comparison, and precise comparison, thereby achieving overvoltage protection.

[0205] 2. By using the enable control module, the conflict between power-on (i.e., startup) deadlock and overvoltage shutdown protection is resolved, thus avoiding power-on deadlock and achieving overvoltage protection.

[0206] 3. The larger bias current caused by overvoltage can enhance the response speed of the first comparator, thereby further improving the timeliness of protection; and, when setting the specific structure of the second comparator, if it is also electrically connected to the second bias voltage, a fast response under overvoltage can also be achieved.

[0207] 4. When implementing overvoltage protection, only the comparator consumes minimal static power, making it suitable for various low-power and ultra-low-power scenarios.

[0208] 5. When implementing overvoltage protection, it can improve the stability of the level conversion module and the reference voltage module, and suppress the impact of sudden changes in power supply voltage at the power supply terminal.

[0209] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A level shifting device, characterized by, include: Level conversion module, reference voltage module, and enable control module; The reference voltage module is used for: Based on the target voltage output by the level conversion module, a first reference signal is output to both the level conversion module and the enable control module. The enabling control module is used for: Based on the first reference signal, a second reference signal is output to the level conversion module; when it is determined that the power supply voltage provided by the power supply terminal meets the first preset condition, a first enable signal is output to the level conversion module; when it is determined that the target voltage meets the second preset condition, a second enable signal is output to the level conversion module; wherein, the first preset condition includes: the power supply voltage does not exceed the first preset value, and / or the rise rate of the power supply voltage when the level conversion device is started does not exceed the preset rate; the second preset condition includes: the target voltage is less than the second preset value; The level conversion module is used for: Under the control of the first enable signal or the second enable signal, the power supply voltage is converted into the target voltage according to the first reference signal and / or the second reference signal.

2. The level shifting device of claim 1, wherein, The enable control module includes: an enable unit and a comparison unit; The comparison unit is electrically connected to both the power supply terminal and the enable unit, and the comparison unit is used for: When it is determined that the power supply voltage meets the first preset condition, an indication signal is output to the enable unit; The enabling unit is also electrically connected to the reference voltage module and the level conversion module, respectively, and the enabling unit is used for: When it is determined that the target voltage meets the second preset condition, the second enable signal is output to the level conversion module; when it is determined that the target voltage does not meet the second preset condition and the indication signal is received, the first enable signal is output to the level conversion module; and the second reference signal is output to the level conversion module according to the first reference signal.

3. The level conversion device as described in claim 2, characterized in that, The first preset condition includes: the rise rate of the power supply voltage does not exceed the preset rate when the level conversion device is started, and the comparison unit includes a rising edge comparison subunit; The rising edge comparison subunit is electrically connected to the enable unit and the power supply terminal, respectively, and the rising edge comparison subunit is used for: When the rise rate of the power supply voltage does not exceed the preset rate when the level conversion device is started, the indication signal is output to the enable unit.

4. The level conversion device as described in claim 3, characterized in that, The rising edge comparison subunit includes: a delay circuit, a difference setting circuit, and a first comparator; The first input terminal of the first comparator is electrically connected to the output terminal of the delay circuit, the second input terminal is electrically connected to the output terminal of the difference setting circuit, and the output terminal is electrically connected to the enable unit. The input terminal of the delay circuit is electrically connected to the power supply terminal; The input terminal of the difference setting circuit is electrically connected to the power supply terminal.

5. The level conversion device according to any one of claims 2-4, characterized in that, The first preset condition includes: the power supply voltage does not exceed the first preset value, and the comparison unit includes a voltage comparison subunit; The voltage comparison subunit is electrically connected to the enable unit, the power supply terminal, and the reference voltage module, respectively. The voltage comparison subunit is used for: Based on the power supply voltage and the first reference signal, when it is determined that the power supply voltage does not exceed the first preset value, the indicator signal is output to the enabling unit.

6. The level conversion device as described in claim 5, characterized in that, The voltage comparison subunit includes: a low-power comparison circuit, a precise comparison circuit, and a logic circuit; The low-power comparator circuit is electrically connected to the power supply terminal, the logic circuit, and the reference voltage module, respectively. The low-power comparator circuit is used for: When it is determined, based on the power supply voltage and the first reference signal, that the power supply voltage does not exceed the first preset value, a first indication signal is output to the logic circuit. The precise comparison circuit is electrically connected to the power supply terminal, the reference voltage terminal, and the logic circuit, respectively. The precise comparison circuit is used for: When it is determined, based on the power supply voltage and the reference voltage provided by the reference voltage terminal, that the power supply voltage does not exceed the first preset value, a second indication signal is output to the logic circuit. The logic circuit is used for: Upon receiving the first indication signal and the second indication signal, the indication signal is output.

7. The level conversion device as described in claim 6, characterized in that, The low-power comparison circuit includes a second comparator, and the precise comparison circuit includes a third comparator; The first input terminal of the second comparator is electrically connected to the power supply terminal, the second input terminal is electrically connected to the reference voltage module, and the output terminal is electrically connected to the logic circuit. The first input terminal of the third comparator is electrically connected to the power supply terminal, the second input terminal is electrically connected to the reference voltage terminal, and the output terminal is electrically connected to the logic circuit. The logic circuit includes a logic OR.

8. The level conversion device as described in claim 2, characterized in that, The enabling unit includes: a first subunit and a second subunit; The first subunit is electrically connected to the reference voltage module, the level conversion module, and the second subunit, respectively. The first subunit is used for: Based on the first reference signal, the second reference signal is output to the level conversion module, and a reset signal is output to the second subunit; The second subunit is also electrically connected to the comparison unit and the level conversion module, respectively, and the second subunit is used for: When it is determined that the target voltage does not meet the second preset condition and the indication signal is received, the first enable signal is output; when it is determined that the target voltage meets the second preset condition and the reset signal is received, the second enable signal is output.

9. The level conversion device as described in claim 8, characterized in that, The second subunit includes: an enable signal output circuit, a reset signal control circuit, and an indicator signal control circuit; The enable signal output circuit is electrically connected to the reset signal control circuit, the indicator signal control circuit, and the level conversion module, respectively. The reset signal control circuit is electrically connected to the first sub-unit; The indicator signal control circuit is electrically connected to the comparison unit and the level conversion module, respectively.

10. The level conversion device as claimed in claim 8, characterized in that, The first subunit includes: a reference signal generation circuit and a reset signal generation circuit; The reference signal generation circuit is electrically connected to the reference voltage module and the level conversion module, respectively. The reset signal generation circuit is electrically connected to the reference signal generation circuit and the second sub-unit, respectively.

11. The level conversion device as claimed in claim 1, characterized in that, The level conversion module is specifically used for: Upon receiving the second enable signal, the power supply voltage is converted into the target voltage according to the second reference signal; Upon receiving the first enable signal, the power supply voltage is converted into the target voltage based on the first reference signal.

12. A level conversion method, characterized in that, The level conversion method is applied to a level conversion device, and the level conversion method includes: The enable control module outputs a second reference signal to the level conversion module based on a first reference signal; when it determines that the power supply voltage provided by the power supply terminal meets a first preset condition, it outputs a first enable signal to the level conversion module; when it determines that the target voltage meets a second preset condition, it outputs a second enable signal to the level conversion module; wherein, the first preset condition includes: the power supply voltage does not exceed a first preset value, and / or the rise rate of the power supply voltage when the level conversion device is started does not exceed a preset rate; the second preset condition includes: the target voltage is less than a second preset value; Under the control of the first enable signal or the second enable signal, the level conversion module converts the power supply voltage into the target voltage according to the first reference signal and / or the second reference signal. The reference voltage module outputs the first reference signal to the level conversion module and the enable control module respectively, based on the target voltage.

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