An optical module performance debugging device, method and medium
By using an optical module performance debugging device and method, and by automatically adjusting register values using a two-dimensional electro-eye diagram, the problems of expensive equipment and low efficiency in existing technologies are solved, and efficient and low-cost optical module performance debugging is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SICHUAN INTERCONNECT INNOVATION TECHNOLOGY CO LTD
- Filing Date
- 2023-05-11
- Publication Date
- 2026-07-31
AI Technical Summary
Existing optical module performance debugging equipment is expensive, has low testing efficiency, and has high requirements for the consistency of optical devices.
An optical module performance debugging device is used, which includes a module board under test, a standard module board, an attenuation module, and a test module. The device automatically adjusts the register values by generating a two-dimensional electro-eye diagram to achieve optical module performance debugging.
This improved testing efficiency, reduced costs, and lowered the requirements for optical device consistency.
Smart Images
Figure CN116566507B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of optical module performance debugging technology, specifically relating to an optical module performance debugging device, method and medium. Background Technology
[0002] With the increasing sophistication of modern computer networks, traditional data transmission and processing methods can no longer meet the demands. Therefore, optical communication technology has been adopted, which improves data transmission speed and facilitates information processing. However, the ever-increasing demand for optical modules presents a significant challenge to the research, development, and production efficiency of these modules.
[0003] There are several methods for debugging the transceiver performance of existing optical modules. One method involves using high-precision equipment to quantify the module's performance specifications. This includes testing the module's optical power with a power meter, adjusting registers to bring it within the required range if it's outside the acceptable range, and then testing the transmitting-end eye diagram performance using a high-speed eye diagram oscilloscope to determine if the module's performance meets the requirements. Another method involves indirectly calculating the optical power value and extinction ratio using the bias current, and then measuring the receiving-end eye diagram with an oscilloscope to quantify the receiving-end performance.
[0004] The above method has the following drawbacks:
[0005] 1. The equipment used is expensive, the test items are performed in sequence, the test time is long, and the efficiency is low;
[0006] 2. Calculating the optical power output of the optical module indirectly through current requires high consistency of optical devices, which general optical devices cannot meet. Summary of the Invention
[0007] To address the shortcomings of existing technologies, such as expensive equipment, low testing efficiency, and high requirements for optical device consistency, this invention provides an optical module performance debugging device, method, and medium that are inexpensive, have high testing efficiency, and reduce the requirements for optical device consistency.
[0008] The objective of this invention is achieved through the following technical solution:
[0009] The first aspect of this invention discloses a method for debugging the performance of an optical module, comprising the following steps:
[0010] Obtain the value of the register of the module under test, wherein the register is a transmitting end register or a receiving end register;
[0011] Acquire the electrical signal to be tested, wherein the electrical signal to be tested is a standard module receiving end signal corresponding to the module under test and the signal is a signal after attenuation of the transmitting end signal of the module under test, or the electrical signal to be tested is a receiving end signal of the module under test and the signal is a signal after attenuation of the transmitting end signal of the standard module corresponding to the module under test;
[0012] A corresponding two-dimensional electro-eye diagram is generated based on the electrical signal to be tested;
[0013] Determine whether the two-dimensional electro-eye diagram meets the set requirements;
[0014] In response to the two-dimensional electro-eye diagram not meeting the requirements, a register adjustment instruction is generated so that the module under test adjusts the value of the transmitting end register or the receiving end register according to the register adjustment instruction until the two-dimensional electro-eye diagram of the standard module meets the set requirements.
[0015] In one possible design, generating a corresponding two-dimensional electrooculogram based on the electrical signal to be measured includes:
[0016] Calculate the amplitude of the electrical signal to be measured and determine the rise time and fall time;
[0017] Obtain the distribution of error data;
[0018] A two-dimensional electro-eye diagram is simulated and drawn based on the amplitude, rise time, fall time, and error data distribution of the electrical signal under test.
[0019] A second aspect of the present invention discloses an optical module performance debugging device, comprising:
[0020] A module board under test, wherein the module board under test is used to install and debug the module under test;
[0021] A standard module board, wherein the standard module board is used to install a standard module corresponding to the module under test;
[0022] An attenuation module is connected to the module board under test and the standard module board, and is used to attenuate the emitted light at one end before sending it to the other end.
[0023] A test module is provided, which is used to adjust the attenuation of the multimode attenuation module and adjust the value of the register of the module under test according to the signal received by the module board under test or the standard module board.
[0024] In one possible design, the attenuation module is a multimode attenuator.
[0025] In one possible design, a debugging interface is provided between the test module and the module under test board, and the debugging interface is used to connect to the optical module.
[0026] Compared with the prior art, the present invention has at least the following advantages and beneficial effects:
[0027] 1. This invention automatically processes data and debugs the optical module based on the two-dimensional electro-optic diagram by using a test module, resulting in high testing efficiency.
[0028] 2. This invention uses a test module, a module board under test, a standard module board, and an attenuation module to achieve performance debugging, which greatly reduces costs.
[0029] 3. This invention reduces the requirements for the consistency of optical devices. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a schematic diagram of the structure of the device of the present invention. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0033] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this invention can be combined with each other.
[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0037] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0038] Existing optical module performance debugging devices are expensive and inefficient. To address this, the inventors have developed an optical module performance debugging device and method, the latter relying on the device for implementation. Specifically, as follows... Figure 1 As shown, the optical module performance debugging device disclosed in this invention includes a module board under test, a standard module board, an attenuation module, and a test module.
[0039] The module under test (DUT) board is used to install and debug the DUT; the standard module board is used to install the standard module corresponding to the DUT; the attenuation module is connected to the DUT board and the standard module board, and is used to attenuate the emitted light at one end before sending it to the other end, that is, to attenuate the signal at the DUT transmitting end before sending it to the standard module receiving end, or to attenuate the signal at the standard module transmitting end before sending it to the DUT receiving end; the test module is used to adjust the attenuation amount of the multimode attenuation module and adjust the value of the DUT register according to the signal at the receiving end of the DUT board or the standard module board.
[0040] The test module is the core control center of the debugging device. It mainly realizes the performance debugging of the receiver and transmitter of the module under test, the generation of PRBS code pattern for high-speed communication between the module under test and the standard module, and the error detection and judgment. It can be an FPGA debugging module, a microcontroller debugging module or other intelligent control module.
[0041] The attenuation module attenuates the signal sent by the module under test or the standard module. In this solution, a multimode attenuator is preferred to simplify the circuit and layout.
[0042] The module under test (DUT) board has a module debugging interface and a high-speed communication interface. The DUT connects to the test module through the debugging interface and exchanges data with the test module through the high-speed communication interface.
[0043] The standard module board also has a high-speed communication interface, which can communicate with the module under test and exchange data with the test module.
[0044] This test module adjusts the values of the registers of the module under test (DUT) based on the receiving signal from the DUT or standard module to achieve optical module performance debugging. Debugging includes debugging the values of the receiving registers and the transmitting registers of the DUT. There is no fixed order for debugging the receiving and transmitting registers; the principle is to complete the debugging of one register value before proceeding to the next.
[0045] The debugging method of the optical module performance debugging device based on the above structure includes steps S11 to S15.
[0046] Step S11: Connect the module under test (DUT) and the standard module. In this step, the DUT and its corresponding standard module are respectively installed on the DUT board and the standard module board. The DUT and the standard module can be 10G PLCCs or other optical modules.
[0047] Step S12: Start the system. The module under test (DUT) communicates with the test module to confirm whether the DUT is powered on. If the DUT is powered on, proceed with the DUT debugging process.
[0048] Step S13: Debugging the module under test. This includes debugging the register values of the receiving end of the module under test and debugging the register values of the transmitting end of the module under test.
[0049] Specifically, debugging the register value of the transmitting end of the module under test includes steps S13-11 to S13-14.
[0050] Step S13-11: Obtain the initial value of the register of the module under test, that is, the initial value of the transmitter register of the module under test.
[0051] Step S13-12: Adjust the multimode attenuation module so that the module under test sends a signal, which is then attenuated by the multimode attenuation module and sent to the receiving end of the standard module.
[0052] Step S13-13: Obtain the electrical signal to be tested from the receiver of the standard module, generate a corresponding two-dimensional photoelectric eye diagram based on the electrical signal to be tested, and determine whether the two-dimensional photoelectric eye diagram meets the set requirements.
[0053] Specifically, taking the FPGA debugging module as an example, the test module acquires the electrical signal under test through the FPGA's internal SerDes interface. After the electrical signal under test passes through the internal equalizer, the amplitude, rise time, and fall time of the electrical signal under test are periodically acquired through the SerDes interface. At the same time, the distribution of bit error data that occurs during communication is recorded. Based on the obtained signal amplitude, rise and fall times, bit error data distribution, and other relevant data, a two-dimensional electro-eye diagram is simulated and plotted within the UI time range corresponding to the transmission rate.
[0054] Error data is obtained by comparing the data from the sending and receiving ends.
[0055] The following steps are used to determine whether the two-dimensional electro-eye diagram (EEM) meets the set requirements: Traverse the two-dimensional EEM and record the accumulated data points; divide the two-dimensional EEM into regions to obtain a data eye diagram. Different colors can be used to divide different regions of the two-dimensional EEM. Then, compare the data eye diagram with the middle region of the corresponding standard eye diagram to determine the template margin. Specifically, compare it with the middle region of the standard communication protocol eye diagram template. By gradually zooming in and out of the standard template region, the final template margin is calculated by comparing the allowable number of bit errors. Finally, determine whether the two-dimensional EEM meets the set requirements based on the template margin. When the template margin is greater than a threshold, the two-dimensional EEM is considered to meet the set requirements; conversely, if the template margin is less than or equal to a threshold, the two-dimensional EEM is considered to not meet the set requirements.
[0056] Steps S13-14: If the two-dimensional electro-eye diagram meets the set requirements, the process ends; if the two-dimensional electro-eye diagram does not meet the requirements, a register adjustment instruction is generated so that the module under test adjusts the value of the transmitting end register according to the register adjustment instruction, and then the value of the transmitting end register of the module under test is obtained again. Steps S13-12 and S13-13 are repeated until the two-dimensional electro-eye diagram meets the set requirements, that is, the eye diagram template margin is greater than the required value.
[0057] Similarly, debugging the register values of the receiving end of the module under test includes steps S13-21 to S13-24.
[0058] Step S13-21: Obtain the initial value of the register of the module under test, that is, the initial value of the receiver register of the module under test.
[0059] Step S13-22: Adjust the multimode attenuation module so that the standard module sends a signal, which is then attenuated by the multimode attenuation module and sent to the receiving end of the module under test.
[0060] Step S13-23: Obtain the electrical signal to be tested from the receiver of the module under test, generate a corresponding two-dimensional photoelectric sensor diagram based on the electrical signal to be tested, and determine whether the two-dimensional photoelectric sensor diagram meets the set requirements. This step is the same as step S13-13, and will not be described again here.
[0061] Step S13-24: If the two-dimensional photoelectric image meets the set requirements, the process ends; if the two-dimensional photoelectric image does not meet the requirements, a register adjustment instruction is generated so that the module under test adjusts the value of the receiving end register according to the register adjustment instruction, and then the value of the receiving end register of the module under test is obtained again. Steps S13-22 and S13-23 are repeated until the two-dimensional photoelectric image meets the set requirements.
[0062] The aforementioned device and method for optical module performance debugging significantly improves testing efficiency compared to existing technologies. Since this invention does not use an oscilloscope, but instead utilizes an FPGA for rapid processing of received and output data, the testing speed is fast and the accuracy is high. Conventional four-channel solutions using a bit error rate tester and oscilloscope cost around 500,000 RMB. This invention uses an FPGA motherboard, an external test board, and a standard board, employing data processing to calculate receiver performance, resulting in a very low cost, below 100,000 RMB.
[0063] In addition, the present invention also provides a computer-readable storage medium storing instructions that, when executed on a computer, perform any of the optical module performance debugging methods described above. Specifically, the memory may include, but is not limited to, random-access memory (RAM), read-only memory (ROM), flash memory, first-in-first-out (FIFO) memory, and / or first-in-last-out (FILO) memory, etc.
[0064] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for debugging the performance of an optical module, characterized in that, Includes the following steps: Obtain the value of the register of the module under test, wherein the register is a transmitting end register or a receiving end register; Acquire the electrical signal to be tested, wherein the electrical signal to be tested is a standard module receiving end signal corresponding to the module under test and the signal is a signal after attenuation of the transmitting end signal of the module under test, or the electrical signal to be tested is a receiving end signal of the module under test and the signal is a signal after attenuation of the transmitting end signal of the standard module corresponding to the module under test; Generate a corresponding two-dimensional electro-eye diagram based on the electrical signal to be tested, including: Calculate the amplitude of the electrical signal under test and determine the rise time and fall time. Obtain the distribution of error data. A two-dimensional photoelectric sensor diagram is simulated and drawn based on the amplitude, rise time, fall time, and error data distribution of the electrical signal under test. Determine whether the two-dimensional electro-eye diagram meets the set requirements; In response to the two-dimensional electro-eye diagram not meeting the requirements, a register adjustment instruction is generated so that the module under test adjusts the value of the transmitting end register or the receiving end register according to the register adjustment instruction until the two-dimensional electro-eye diagram of the standard module meets the set requirements.
2. The optical module performance debugging method according to claim 1, characterized in that: The determination of whether the two-dimensional electrooculogram meets the set requirements includes: Traverse the two-dimensional electrooculogram and record the data accumulation points; The two-dimensional electro-eye diagram is divided into regions to obtain a data eye diagram; The data eye diagram is compared with the middle area of the corresponding standard eye diagram to determine the template margin; The template margin is used to determine whether the two-dimensional electro-eye diagram meets the set requirements.
3. A computer-readable storage medium storing instructions thereon, characterized in that: When the instruction is executed on a computer, it performs the optical module performance debugging method according to any one of claims 1-2.
4. An optical module performance debugging device for implementing the optical module performance debugging method according to any one of claims 1 to 2, characterized in that, include: A module board under test, wherein the module board under test is used to install and debug the module under test; A standard module board, wherein the standard module board is used to install a standard module corresponding to the module under test; An attenuation module is connected to the module board under test and the standard module board, and is used to attenuate the emitted light at one end before sending it to the other end. A test module is provided, which is used to adjust the attenuation of the multimode attenuation module and adjust the value of the register of the module under test according to the signal received by the module board under test or the standard module board.
5. The optical module performance debugging device according to claim 4, characterized in that: The attenuation module is a multimode attenuator.
6. The optical module performance debugging device according to claim 4, characterized in that: A debugging interface is provided between the test module and the module board under test, and the debugging interface is used to connect to the optical module.