Circuit board processing method, circuit board structure, and apparatus

Abstract

The application discloses a circuit board processing method, a circuit board structure and equipment, and comprises the following steps: laminating a first dielectric layer on a first circuit board; embedding a first interconnection metal structure which is electrically connected with the first circuit board in the first dielectric layer to obtain a second circuit board; laminating a second dielectric layer on the second circuit board; embedding a target metal circuit which is electrically connected with the first interconnection metal structure in the second dielectric layer to obtain a target circuit board. According to the technical scheme, the target metal circuit which is electrically connected with the first interconnection metal structure is embedded in the second dielectric layer, so that when the surface part of the target metal circuit is etched, there is no side etching problem and the bottom of the middle layer circuit of the first circuit board is not recessed, thereby ensuring the reliability in the circuit board processing process.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a circuit board processing method, circuit board structure and equipment. Background Technology

[0002] In the fabrication of precision circuit boards, the SAP (Selective Aluminum Plating) process is commonly used. The SAP process involves creating the circuit pattern on a conductive seed layer, followed by etching the seed layer to expose the circuit pattern. However, when fabricating ultra-fine circuits smaller than 5 micrometers, the SAP process suffers from side etching and bottom depression issues due to the bottom conductive seed layer etching step. Side etching refers to the etching of the sides of the circuit pattern caused by the bottom conductive seed layer etching, leading to circuit deformation or poor connectivity. Bottom depression occurs when the etching rate of the bottom conductive seed layer is slower than that of the top, resulting in over-etching at the bottom of the circuit, thus affecting its reliability. Therefore, improving the reliability of precision circuit fabrication is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] This invention provides a circuit board processing method, circuit board structure, and equipment to solve the problem of poor reliability in existing precision circuit manufacturing processes.

[0004] A circuit board manufacturing method, comprising:

[0005] A first dielectric layer is deposited on the first circuit board;

[0006] A second circuit board is obtained by embedding a first interconnect metal structure electrically connected to the first circuit board within the first dielectric layer;

[0007] A second dielectric layer is deposited on the second circuit board;

[0008] The target metal circuit is obtained by embedding the target metal line that is electrically connected to the first interconnect metal structure in the second dielectric layer.

[0009] Further, the deposition of the first dielectric layer on the first circuit board includes:

[0010] A first insulating layer is fabricated on the first circuit board;

[0011] A first photoresist layer is fabricated on the first insulating layer to obtain a first dielectric layer comprising the first insulating layer and the first photoresist layer.

[0012] Furthermore, the first dielectric layer includes a first insulating layer and a first photoresist layer;

[0013] The method of embedding a first interconnect metal structure electrically connected to the first circuit board within the first dielectric layer to obtain a second circuit board includes:

[0014] On the first dielectric layer, a first interconnect hole is formed, wherein the first interconnect hole penetrates the first insulating layer and the first photoresist layer;

[0015] A conductive material is filled into the first interconnect hole to obtain a first interconnect metal structure that is electrically connected to the first circuit board. The first photoresist layer is then removed to obtain the second circuit board.

[0016] Further, the step of filling the first interconnect hole with conductive material to obtain a first interconnect metal structure electrically connected to the first circuit board, and removing the first photoresist layer to obtain the second circuit board, includes:

[0017] A first conductive seed layer is fabricated on the inner wall of the first interconnect hole and on the outer surface of the first photoresist layer;

[0018] The first conductive seed layer is electroplated to obtain the first metal layer;

[0019] The first metal layer is etched so that the first metal layer in the first interconnect hole is flush with the first insulating layer.

[0020] The first photoresist layer is removed to obtain the second circuit board.

[0021] Further, the deposition of the second dielectric layer on the second circuit board includes:

[0022] On the second circuit board, a second insulating layer is processed;

[0023] A second photoresist layer is fabricated on the second insulating layer to obtain a second dielectric layer comprising the second insulating layer and the second photoresist layer.

[0024] Further, a target metal line electrically connected to the first interconnect metal structure is embedded in the second dielectric layer to obtain a target circuit board, comprising:

[0025] A metal mask layer is fabricated on the second dielectric layer;

[0026] A second photoresist layer is fabricated on the metal mask layer, and a first photoresist pattern is created.

[0027] On the metal mask layer, a first mask pattern is fabricated based on a first photoresist pattern;

[0028] On the second dielectric layer, based on the first mask pattern, the target line trench is fabricated;

[0029] The target circuit board is obtained by filling the target line trench with conductive material and embedding the target metal line that is electrically connected to the first interconnecting metal structure.

[0030] Further, based on the first mask pattern, processing the target line trench includes: processing the target line trench on the second dielectric layer using plasma etching technology according to the first mask pattern.

[0031] Further, the step of filling the target line trench with conductive material and embedding the target metal line electrically connected to the first interconnecting metal structure includes:

[0032] Electroplating is performed on the target line trench to obtain a second metal layer;

[0033] The second metal layer is etched to obtain a pre-processed circuit structure, wherein the second metal layer in the target circuit trench of the pre-processed metal structure is flush with the second insulating layer.

[0034] The second photoresist layer in the pre-processed circuit structure is removed to obtain the target metal circuit that is electrically connected to the first interconnect metal structure.

[0035] A circuit board structure comprising a target circuit board processed by the above-described circuit board processing method.

[0036] A circuit board processing device for implementing the above-described circuit board processing method.

[0037] The aforementioned circuit board processing method, circuit board structure, and equipment involve depositing a first dielectric layer on a first circuit board and embedding a first interconnect metal structure electrically connected to the first circuit board within the first dielectric layer to obtain a second circuit board. The presence of the first interconnect metal structure prevents the target metal lines from exhibiting excessive arc radius or depressions at the connection points with the first interconnect metal structure, thereby improving the reliability of the circuit board processing and consequently the reliability of the target circuit board. A second dielectric layer is then deposited on the second circuit board, and a target metal line electrically connected to the first interconnect metal structure is embedded within the second dielectric layer to obtain the target circuit board. By embedding the target metal line electrically connected to the first interconnect metal structure within the second dielectric layer, side etching problems and bottom depressions in the intermediate layer lines of the first circuit board are avoided during the etching of the surface portion of the target metal line, thus ensuring the reliability of the circuit board processing. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart of a circuit board processing method according to an embodiment of the present invention;

[0040] Figure 2 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0041] Figure 3 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0042] Figure 4 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0043] Figure 5 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0044] Figure 6 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0045] Figure 7 This is another flowchart of a circuit board processing method according to one embodiment of the present invention;

[0046] Figure 8 This is a schematic flowchart of a circuit board processing method according to an embodiment of the present invention.

[0047] In the figure: 10, first circuit board; 20, first dielectric layer; 21, first insulating layer; 22, first photoresist layer; 30, first interconnect hole; 40, first interconnect metal structure; 50, second dielectric layer; 51, second insulating layer; 52, second photoresist layer; 60, target metal line; 61, target line trench; 71, first conductive seed layer; 72, second conductive seed layer; 81, first metal layer; 82, second metal layer. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0050] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0051] This embodiment provides a circuit board processing method, such as... Figure 1 As shown and Figure 8 As shown, it includes:

[0052] S101: A first dielectric layer 20 is deposited on the first circuit board 10.

[0053] S102: Embedding a first interconnect metal structure 40 electrically connected to the first circuit board 10 within the first dielectric layer 20, to obtain a second circuit board.

[0054] S103: Deposit a second dielectric layer 50 on the second circuit board.

[0055] S104: Embed the target metal line 60, which is electrically connected to the first interconnect metal structure 40, into the second dielectric layer 50 to obtain the target circuit board.

[0056] The first dielectric layer 20 refers to the dielectric layer used to assist in the processing of the first interconnect metal structure 40.

[0057] As an example, in step S101, the first circuit board 10 can be an intermediate layer in a multilayer circuit board. Specifically, before step S101, a circuit board substrate is provided, and the first circuit board 10 is laminated on the circuit board substrate. Optionally, the circuit board substrate and the first circuit board 10 may or may not contain metal layers. Optionally, the circuit board substrate can be an inner core board. Further, the first circuit board 10 can be laminated on the upper and lower surfaces of the inner core board respectively, so as to obtain a multilayer circuit board containing the inner core board in subsequent processing. Alternatively, the first circuit board 10 can be laminated on one of the surfaces of the inner core board, and after the multilayer circuit board is processed, the inner core board is peeled off to obtain a multilayer circuit board without the inner core board. Optionally, the first circuit board 10 can be a circuit board manufactured using PCB (Printed Circuit Board) technology, or a circuit board manufactured using RDL (Redistribution Layer) technology. In this example, a first dielectric layer 20 is fabricated on the first circuit board 10 to facilitate the subsequent deposition of other intermediate layer circuit boards or surface layer circuit boards in a multilayer circuit board on the first circuit board 10. It is understood that the circuit board substrate refers to the bottom layer circuit board in a multilayer circuit board, and the surface layer circuit board refers to the top layer circuit board in a multilayer circuit board. It should be noted that the first circuit board 10 includes pre-fabricated intermediate layer lines, which can be electrically connected to other intermediate layer circuit boards or surface layer circuit boards in the multilayer circuit board. Exemplarily, the pre-fabricated intermediate layer lines and other intermediate layer circuit boards or surface layer circuit boards in the multilayer circuit board can be electrically connected through the first interconnect metal structure 40 described in this application.

[0058] Furthermore, prior to step S101, the surface of the first circuit board 10 is cleaned to improve the adhesion of the first dielectric layer 20 when it is deposited on the first circuit board 10.

[0059] As an example, in step S102, a first interconnect metal structure 40 electrically connected to the first circuit board 10 is embedded within the first dielectric layer 20 to obtain a second circuit board. Exemplarily, a first interconnect hole 30 is first processed within the first dielectric layer 20, and then a conductive material is filled into the first interconnect hole 30 to obtain the first interconnect metal structure 40 embedded within the first dielectric layer 20 and electrically connected to the first circuit board 10. Optionally, the conductive material can be a metallic material, such as copper, nickel, chromium, zinc, silver, and gold.

[0060] It should be noted that since SAP or RDL processes directly achieve circuit fabrication and interlayer interconnection through electroplating, that is, the target metal circuit 60 is fabricated while filling the first interconnect hole 30, when the first dielectric layer 20 of the circuit board is thick, the electroplated copper filling of the first interconnect hole 30 will result in a large top curvature, which will affect signal transmission and insulation reliability. When the first dielectric layer 20 is thin, the depth of the first interconnect hole 30 is too shallow, making electroplating impossible. This results in unevenness of the top arc of the target metal line 60 or metal depression at the location of the first interconnect hole 30, affecting the uniformity of the filling of the first dielectric layer 20 and the stacking design of the first interconnect hole 30, thus impacting the reliability of the circuit board. Therefore, in this example, a first interconnect metal structure 40 electrically connected to the first circuit board 10 is embedded within the first dielectric layer 20 to obtain the second circuit board. During subsequent processing of the target metal line 60, the presence of the first interconnect metal structure 40 prevents excessive arc or depression at the connection point between the target metal line 60 and the first interconnect metal structure 40, thereby improving the reliability of the circuit board processing and ultimately enhancing the reliability of the target circuit board. Furthermore, side etching is prevented on the first interconnect metal structure 40.

[0061] The second dielectric layer 50 refers to the dielectric layer used to assist in the processing of the target metal circuit 60.

[0062] As an example, in step S103, a second dielectric layer 50 is deposited on the second circuit board so that the target metal line 60 can be fabricated based on the second dielectric layer 50 in subsequent steps.

[0063] As an example, in step S104, a target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded in the second dielectric layer 50 to obtain the target circuit board. In this example, since the target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded in the second dielectric layer 50, there will be no side etching problem or bottom depression problem of the intermediate layer line of the first circuit board 10 when the surface portion of the target metal line 60 is subsequently etched, thereby ensuring the reliability of the circuit board manufacturing process.

[0064] In this embodiment, a first dielectric layer 20 is deposited on the first circuit board 10, and a first interconnect metal structure 40 electrically connected to the first circuit board 10 is embedded in the first dielectric layer 20 to obtain a second circuit board. Due to the presence of the first interconnect metal structure 40, it is possible to prevent the target metal line 60 from having a large arc or a depression at the connection position with the first interconnect metal structure 40, thereby improving the reliability of circuit board processing and thus improving the reliability of the target circuit board. A second dielectric layer 50 is deposited on the second circuit board, and the target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded in the second dielectric layer 50 to obtain the target circuit board. By embedding the target metal line 60 electrically connected to the first interconnect metal structure 40 in the second dielectric layer 50, there will be no side etching problem or bottom depression problem of the intermediate layer line of the first circuit board 10 when etching the surface part of the target metal line 60, thereby ensuring the reliability of the circuit board processing.

[0065] In one embodiment, such as Figure 2 As shown, in step S101, the first dielectric layer 20 is deposited on the first circuit board 10, including:

[0066] S201: A first insulating layer 21 is processed on the first circuit board 10.

[0067] S202: On the first insulating layer 21, a first photoresist layer 22 is processed to obtain a first dielectric layer 20 including the first insulating layer 21 and the first photoresist layer 22.

[0068] As an example, in step S201, the surface of the first circuit board 10 is cleaned, and then a first insulating layer 21 is processed on the cleaned first circuit board 10 to improve the adhesion of the first insulating layer 21 when it is stacked on the first circuit board 10. Optionally, the material of the first insulating layer 21 can be ABF (Ajinomoto build-up film), PSPI (Photosensitive Polyimide), PI (Polyimide), or conventional FR4 (Flame Retardant 4), BT (Bismaleimide Triazine), and EMC (Epoxy Molding Compound).

[0069] As an example, in step S202, the first photoresist layer 22 can be a dry film or photoresist, or a specially formulated photoresist material without photosensitive components, or other specially formulated materials that can be selectively removed in a specific solution. The specific solution is one that can remove the first photoresist layer 22 without damaging the first insulating layer 21 and the conductive material. This ensures that the first insulating layer 21 and the conductive material are not damaged during subsequent processing of the first interconnect metal structure 40. Preferably, the first photoresist layer 22 is a specially formulated photoresist material without photosensitive components. Since the first photoresist layer 22 does not need to be photosensitive, using a photoresist material without photosensitive components can reduce the cost of the first photoresist layer 22.

[0070] In this embodiment, a first insulating layer 21 is processed on the first circuit board 10, and a first photoresist layer 22 is processed on the first insulating layer 21, thereby obtaining a first dielectric layer 20 including the first insulating layer 21 and the first photoresist layer 22. This allows the first interconnect metal structure 40, which is electrically connected to the first circuit board 10, to be embedded in the first dielectric layer 20, thus obtaining a second circuit board. Due to the presence of the first interconnect metal structure 40, it is possible to prevent the location where the target metal line 60 is connected to the first interconnect metal structure 40 from having a large arc or being concave, thereby improving the reliability of the circuit board processing and thus improving the reliability of the target circuit board.

[0071] In one embodiment, such as Figure 3 As shown, in step S102, the first dielectric layer 20 includes a first insulating layer 21 and a first photoresist layer 22; a first interconnect metal structure 40 electrically connected to the first circuit board 10 is embedded in the first dielectric layer 20 to obtain a second circuit board, comprising:

[0072] S301: A first interconnect hole 30 is processed on the first dielectric layer 20, wherein the first interconnect hole 30 penetrates the first insulating layer 21 and the first photoresist layer 22.

[0073] S302: Fill the first interconnect hole 30 with conductive material to obtain the first interconnect metal structure 40 electrically connected to the first circuit board 10, remove the first photoresist layer 22, and obtain the second circuit board.

[0074] As an example, in step S301, a first interconnect hole 30 is fabricated on the first dielectric layer 20, wherein the first interconnect hole 30 penetrates the first insulating layer 21 and the first photoresist layer 22. Exemplarily, a metal mask layer is fabricated on the first dielectric layer 20; a target photoresist layer is fabricated on the metal mask layer, and a target photoresist pattern is created; a target mask pattern is fabricated on the metal mask layer based on the target photoresist pattern; and the first interconnect hole 30 is fabricated on the first dielectric layer 20 based on the target mask pattern, ensuring that the first interconnect hole 30 penetrates the first insulating layer 21 and the first photoresist layer 22.

[0075] The metal mask layer remains stable during the fabrication of the first interconnect hole 30. The metal mask layer is made of any one or a composite layer of two of the following metals: titanium, copper, chromium, and nickel. Preferably, the thickness of the metal mask layer is 50–500 nanometers.

[0076] The target photoresist layer can be either a dry film or a photoresist. The choice can be made based on the size of the target mask pattern and is not limited here.

[0077] The process involves exposing, developing, etching the metal mask layer, and removing the target photoresist layer to obtain a target mask pattern. This target mask pattern exposes the first photoresist layer 22 in the first dielectric layer 20 at the position corresponding to the first interconnect hole 30. It should be noted that the processes of exposure, development, etching the metal mask layer, and removing the target photoresist layer can employ techniques known to those skilled in the art, as long as the target mask pattern exposes the first photoresist layer 22 in the first dielectric layer 20 at the position corresponding to the first interconnect hole 30; no limitations are imposed here.

[0078] The aperture size of the first interconnect hole 30 is determined based on practical experience. Plasma etching is then used to process the first interconnect hole 30 on the target mask pattern. In this example, because the exposure resolution is higher than that of laser drilling, a smaller first interconnect hole 30 can be fabricated. Furthermore, because the metal mask layer is thin (50–500 nm), the lateral etching during the etching process is minimal, resulting in a highly precise target mask pattern. This allows for the subsequent fabrication of the ultra-small first interconnect hole 30 and its corresponding first interconnect metal structure 40.

[0079] Further, based on the target mask pattern, plasma etching is used to process the first interconnect hole 30 on the first dielectric layer 20. As an example, a gas (such as oxygen, argon, nitrogen, etc.) is added to the etching equipment, and the gas pressure and flow rate are selected based on practical experience to form a plasma. By controlling the flow rate and pressure of different gases, the proportion of various particles in the plasma is adjusted to facilitate the precise processing of the first interconnect hole 30 on the first dielectric layer 20. Based on the target mask pattern, by adjusting the energy and bombardment time of the ions in the plasma, the removal of the first photoresist layer 22 and the first insulating layer 21 in the first dielectric layer 20 is controlled, thereby forming the first interconnect hole 30 to be processed. Further, the processed first circuit board 10 is cleaned to remove excess target photoresist layer, metal mask layer and other etching residues.

[0080] As an example, in step S302, conductive material is filled into the first interconnect hole 30 to obtain a first interconnect metal structure 40 electrically connected to the first circuit board 10. The first photoresist layer 22 is then removed to obtain the second circuit board. The first interconnect metal structure 40 is a conductive structure filled into the first interconnect hole 30, used to connect the first circuit board 10 and the target metal line 60. The target metal line 60 can be a conductive line in the first circuit board 10 of another intermediate layer in a multilayer circuit board or in the surface layer circuit board. Optionally, the conductive material can be a metallic material, such as copper, nickel, chromium, zinc, silver, and gold. It should be noted that the thickness of the first interconnect metal structure 40 in the first interconnect hole 30 needs to be within a suitable range and can be adjusted based on practical experience to ensure that, in subsequent steps, when processing the target metal line 60, the arc radius of the line at the connection point between the target metal line 60 and the first interconnect metal structure 40 is not too large or concave.

[0081] Preferably, the first photoresist layer 22 is a photoresist material. The first photoresist layer 22 is removed using a strong alkaline solution, such as sodium hydroxide or other organic base, to obtain the second circuit board.

[0082] In this embodiment, a first interconnect hole 30 is fabricated on the first dielectric layer 20, wherein the first interconnect hole 30 penetrates the first insulating layer 21 and the first photoresist layer 22. The first interconnect hole 30 is filled with conductive material to obtain a first interconnect metal structure 40 electrically connected to the first circuit board 10. The first photoresist layer 22 is removed to obtain a second circuit board. Since the first interconnect metal structure 40 exists, it can prevent the position where the target metal line 60 is connected to the first interconnect metal structure 40 from having a large line curvature or a depression, thereby improving the reliability of the circuit board fabrication and thus improving the reliability of the target circuit board.

[0083] In one embodiment, such as Figure 4 As shown, in step S302, conductive material is filled into the first interconnect hole 30 to obtain a first interconnect metal structure 40 electrically connected to the first circuit board 10. The first photoresist layer 22 is removed to obtain a second circuit board, including:

[0084] S401: A first conductive seed layer 71 is fabricated on the inner wall of the first interconnect hole 30 and the outer surface of the first photoresist layer 22.

[0085] S402: Electroplating is performed on the first conductive seed layer 71 to obtain the first metal layer 81.

[0086] S403: Etch the first metal layer 81 so that the first metal layer 81 in the first interconnect hole 30 is flush with the first insulating layer 21.

[0087] S404: Remove the first photoresist layer 22 to obtain the second circuit board.

[0088] As an example, in step S401, the first conductive seed layer 71 can be graphene oxide, carbon black, graphite, or conductive polymer adsorption, or it can be a metal, such as a first conductive seed layer 71 formed by chemical copper plating, titanium / copper sputtering, etc. In this embodiment, the first conductive seed layer 71 is fabricated on the inner wall of the first interconnect hole 30 and the outer surface of the first photoresist layer 22, so that the conductivity during copper electroplating does not depend on the metal layer on the first circuit board 10.

[0089] As an example, in step S402, when the first conductive seed layer 71 is graphene oxide, a relatively thin first metal layer 81 can be obtained by using a conventional electroplating method, i.e., an electroplating method known to those skilled in the art. When the first conductive seed layer 71 is adsorbed with carbon black, graphite, or conductive polymers, the low conductivity of the first conductive seed layer 71 leads to high equipment costs. When the first conductive seed layer 71 is formed of metal, if the material of the first conductive seed layer 71 and the metal mask layer are the same, then after processing the first interconnect hole 30 on the first dielectric layer 20, the step of removing excess metal mask layer is unnecessary. If the materials of the first conductive seed layer 71 and the metal mask layer are different, then after processing the first interconnect hole 30 on the first dielectric layer 20, the excess metal mask layer is removed, and a pulse electroplating method or a special electroplating method involving redox couples is used to reduce the surface coating thickness, thereby avoiding resource waste and cost increases, and thus reducing processing costs.

[0090] As an example, in step S403, the first metal layer 81 is etched. By controlling the etching time, the first metal layer 81 in the first interconnect hole 30 is flush with the first insulating layer 21, so as to ensure that the subsequently generated first interconnect metal structure 40 can prevent the problem of not being able to fill the first interconnect hole 30 on the thinner first dielectric layer 20, thereby improving the reliability of filling the first interconnect hole 30.

[0091] As an example, in step S404, the first photoresist layer 22 is removed to obtain the second circuit board. The process of removing the first photoresist layer 22 in step S302 of the above embodiment can be used, and will not be described again here.

[0092] In this embodiment, a first conductive seed layer 71 is formed on the inner wall of the first interconnect hole 30 and the outer surface of the first photoresist layer 22. The first conductive seed layer 71 is electroplated to obtain a first metal layer 81. The first metal layer 81 is etched to make the first metal layer 81 in the first interconnect hole 30 flush with the first insulating layer 21. The first photoresist layer 22 is removed to obtain a second circuit board. Since the first metal layer 81 is embedded in the first dielectric layer 20, there is no side etching problem when etching the first metal layer 81, thereby ensuring the reliability of the circuit board manufacturing process.

[0093] In one embodiment, such as Figure 5 As shown, in step S103, the second dielectric layer 50 is deposited on the second circuit board, including:

[0094] S501: On the second circuit board, process the second insulating layer 51.

[0095] S502: On the second insulating layer 51, a second photoresist layer 52 is processed to obtain a second dielectric layer 50 including the second insulating layer 51 and the second photoresist layer 52.

[0096] As an example, in step S201, the surface of the second circuit board is cleaned, and then a second insulating layer 51 is processed on the cleaned second circuit board to improve the adhesion of the second insulating layer 51 when it is deposited on the second circuit board. Optionally, the material of the second insulating layer 51 can be the same as the material of the first insulating layer 21 in the above embodiment, which will not be described again here.

[0097] As an example, in step S202, the second photoresist layer 52 can be a dry film or photoresist, or a specially formulated photoresist material without photosensitive components, or other specially formulated materials that can be selectively removed in a specific solution. This specific solution is one that can remove the second photoresist layer 52 without damaging the first insulating layer 21 and the conductive material. This ensures that the first insulating layer 21 and the conductive material are not damaged during subsequent processing of the first interconnect metal structure 40. Preferably, the second photoresist layer 52 is a specially formulated photoresist material without photosensitive components. Since the second photoresist layer 52 does not need to be photosensitive, using a photoresist material without photosensitive components can reduce the cost of the second photoresist layer 52.

[0098] In this embodiment, a second insulating layer 51 is processed on the second circuit board, and a second photoresist layer 52 is processed on the second insulating layer 51 to obtain a second dielectric layer 50 including the second insulating layer 51 and the second photoresist layer 52. This allows the target metal line 60, which is electrically connected to the first interconnect metal structure 40, to be embedded in the second dielectric layer 50 to obtain the target circuit board. By embedding the target metal line 60, which is electrically connected to the first interconnect metal structure 40, in the second dielectric layer 50, there will be no side etching problem or bottom depression problem of the intermediate layer line of the first circuit board 10 when etching the surface portion of the target metal line 60, thereby ensuring the reliability of the circuit board processing.

[0099] In one embodiment, such as Figure 6 As shown, in step S104, a target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded in the second dielectric layer 50 to obtain the target circuit board, including:

[0100] S601: A metal mask layer is processed on the second dielectric layer 50.

[0101] S602: On the metal mask layer, a second photoresist layer 52 is processed, and a first photoresist pattern is formed.

[0102] S603: On the metal mask layer, based on the first photoresist pattern, process the first mask pattern.

[0103] S604: On the second dielectric layer 50, based on the first mask pattern, the target line trench 61 is processed.

[0104] S605: Fill the target line trench 61 with conductive material and embed the target metal line 60 that is electrically connected to the first interconnect metal structure 40 to obtain the target circuit board.

[0105] As an example, in step S601, the metal mask layer is the same as the metal mask layer used when processing the first interconnect hole 30 in the above embodiment, and will not be described again here.

[0106] As an example, in step S602, a second photoresist layer 52 is fabricated on the metal mask layer, and a first photoresist pattern is created. This first photoresist pattern corresponds to the target metal line 60 and is designed based on practical experience; no limitations are imposed here. Exemplarily, the second photoresist layer 52 is exposed, developed, and then covered with a metal mask layer to obtain the first photoresist pattern.

[0107] As an example, in step S603, a first photoresist pattern is fabricated on the metal mask layer based on the first photoresist pattern. Based on the first photoresist pattern, the second photoresist layer 52 is etched and removed to obtain the first mask pattern, which exposes the second photoresist layer 52 in the second dielectric layer 50 at the position corresponding to the target metal line 60. It should be noted that the processes such as exposure, development, etching of the metal mask layer, and removal of the second photoresist layer 52 in the above embodiment can be processes known to those skilled in the art, as long as the second mask pattern exposes the second photoresist layer 52 in the second dielectric layer 50 at the position corresponding to the target metal line 60, and there is no limitation here.

[0108] As an example, in step S604, a target line trench 61 is processed on the second dielectric layer 50 based on the first mask pattern, so that the target metal line 60 can be embedded in the target line trench 61 in subsequent steps, preventing side etching problems and bottom depression problems of the intermediate layer lines of the first circuit board 10 when etching the surface portion of the target metal line 60, thereby ensuring the reliability of the circuit board processing.

[0109] As an example, in step SS605, conductive material is filled into the target line trench 61, and the target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded to obtain the target circuit board. In this example, the process of filling the target line trench 61 with conductive material and embedding the target metal line 60 electrically connected to the first interconnect metal structure 40 to obtain the target circuit board is similar to the process of filling the first interconnect hole 30 with conductive material in the above embodiment, and will not be described again here.

[0110] In this embodiment, a metal mask layer is processed on the second dielectric layer 50, a second photoresist layer 52 is processed on the metal mask layer, and a first photoresist pattern is formed. Based on the first photoresist pattern, a first mask pattern is processed on the metal mask layer. Based on the first mask pattern, a target line trench 61 is processed on the second dielectric layer 50. Conductive material is filled into the target line trench 61, and a target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded to obtain the target circuit board. By embedding the target metal line 60 electrically connected to the first interconnect metal structure 40 into the second dielectric layer 50, there will be no side etching problem or bottom depression problem of the intermediate layer line of the first circuit board 10 when etching the surface part of the target metal line 60, thereby ensuring the reliability of the circuit board processing.

[0111] In one embodiment, in step S604, processing the target line trench 61 based on the first mask pattern includes: processing the target line trench 61 on the second dielectric layer 50 using plasma etching technology according to the first mask pattern.

[0112] In this embodiment, based on the first mask pattern, plasma etching technology is used to process the target line trench 61 on the second dielectric layer 50. As an example, a gas (such as oxygen, argon, nitrogen, etc.) is added to the etching equipment, and the gas pressure and flow rate are selected based on practical experience to form a plasma. By controlling the flow rate and pressure of different gases, the proportion of various particles in the plasma is adjusted to accurately process the target line trench 61 on the second dielectric layer 50. Based on the first mask pattern, by adjusting the energy and bombardment time of the ions in the plasma, the removal of the second photoresist layer 52 and the second insulating layer 51 in the second dielectric layer 50 is controlled, thereby forming the target line trench 61 to be processed. Further, the processed second circuit board is cleaned to remove excess second photoresist layer 52, metal mask layer and other etching residues.

[0113] In one embodiment, such as Figure 7 As shown, in step S605, a conductive material is filled into the target line trench 61, and a target metal line 60 electrically connected to the first interconnect metal structure 40 is embedded, including:

[0114] S701: Electroplating is performed on the target line trench 61 to obtain the second metal layer 82.

[0115] S702: The second metal layer 82 is etched to obtain a pre-processed circuit structure. The second metal layer 82 in the target circuit trench 61 of the pre-processed metal structure is flush with the second insulating layer 51.

[0116] S703: The second photoresist layer 52 in the pre-processed circuit structure is removed to obtain the target metal circuit 60 that is electrically connected to the first interconnect metal structure 40.

[0117] As an example, in step S701, a second conductive seed layer 72 is fabricated on the target line trench 61, and electroplating is performed on the second conductive seed layer 72 to obtain a second metal layer 82. In this embodiment, the process of fabricating the second conductive seed layer 72 on the target line trench 61 and electroplating the second conductive seed layer 72 to obtain the second metal layer 82 is similar to the process used in steps S401-S402 above, and will not be described again here.

[0118] As an example, in step S702, the second metal layer 82 is etched to obtain a pre-processed circuit structure. The second metal layer 82 in the target circuit trench 61 of the pre-processed metal structure is flush with the second insulating layer 51. This allows for stress-free removal of excess copper plating on the surface of the second insulating layer 51, avoiding damage to the delicate target metal circuit 60 caused by processes such as mechanical polishing. Furthermore, by embedding the target metal circuit 60, which is electrically connected to the first interconnecting metal structure 40, into the second dielectric layer 50, side etching and bottom recessing of the intermediate layer circuits of the first circuit board 10 are avoided when etching the surface portion of the target metal circuit 60, thus ensuring the reliability of the circuit board manufacturing process.

[0119] As an example, in step S703, the second photoresist layer 52 in the pre-processed circuit structure is removed to obtain the target metal circuit 60 electrically connected to the first interconnect metal structure 40. The second photoresist layer 52 is made of photoresist material, and a strong alkaline solution, such as sodium hydroxide or other organic alkali, is used to remove the second photoresist layer 52 in the pre-processed circuit structure to obtain the target metal circuit 60 electrically connected to the first interconnect metal structure 40.

[0120] In this embodiment, the target line trench 61 is electroplated to obtain a second metal layer 82. The second metal layer 82 is etched to obtain a pre-processed line structure. The second metal layer 82 in the target line trench 61 of the pre-processed metal structure is flush with the second insulating layer 51. The second photoresist layer 52 in the pre-processed line structure is removed to obtain the target metal line 60 electrically connected to the first interconnect metal structure 40. This allows for stress-free removal of excess copper plating on the surface of the second insulating layer 51, avoiding damage to the delicate target metal line 60 caused by mechanical grinding and other processes. At the same time, by embedding the target metal line 60 electrically connected to the first interconnect metal structure 40 into the second dielectric layer 50, there is no side etching problem or bottom depression problem of the intermediate layer line of the first circuit board 10 when etching the surface part of the target metal line 60, thereby ensuring the reliability of the circuit board processing and ensuring the flatness of the target metal line 60 surface.

[0121] This embodiment provides a circuit board structure, including the target circuit board obtained by the circuit board processing method described above.

[0122] Optionally, the circuit board structure includes a circuit board substrate. Using the above-described circuit board processing method, a multilayer circuit board is fabricated on the circuit board substrate. Finally, the circuit board substrate is peeled off, and a solder mask layer is formed on the surface of the multilayer first circuit board 10, resulting in a circuit board structure without a circuit board substrate.

[0123] Optionally, the circuit board structure includes a circuit board substrate. Through-holes are formed on the circuit board substrate, and the through-holes are filled with electroplated copper. Circuit patterns are formed on both sides of the circuit board substrate. As needed, the circuit patterns can be formed using the circuit board method described above, or the through-hole filling and circuit pattern formation can be completed in one step using a conventional SAP process. Then, the target circuit board is processed on both sides of the circuit board substrate using the circuit board processing method described above, resulting in a circuit board structure with a circuit board substrate.

[0124] This embodiment provides a circuit board processing device for implementing the circuit board processing method described above.

[0125] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A circuit board processing method, characterized in that, include: A first dielectric layer is deposited on the first circuit board; The first dielectric layer includes a first insulating layer and a first photoresist layer; On the first dielectric layer, a first interconnect hole is formed, wherein the first interconnect hole penetrates the first insulating layer and the first photoresist layer; A conductive material is filled into the first interconnect hole to obtain a first interconnect metal structure that is electrically connected to the first circuit board. The first photoresist layer is removed to obtain a second circuit board. A second dielectric layer is deposited on the second circuit board; A target metal circuit electrically connected to the first interconnect metal structure is embedded in the second dielectric layer to obtain a target circuit board. The step of filling the first interconnect hole with conductive material to obtain a first interconnect metal structure electrically connected to the first circuit board, and removing the first photoresist layer to obtain a second circuit board includes: A first conductive seed layer is fabricated on the inner wall of the first interconnect hole and on the outer surface of the first photoresist layer; The first conductive seed layer is electroplated to obtain the first metal layer; The first metal layer is etched so that the first metal layer in the first interconnect hole is flush with the first insulating layer. The first photoresist layer is removed to obtain the second circuit board.

2. The circuit board processing method as described in claim 1, characterized in that, The deposition of the first dielectric layer on the first circuit board includes: A first insulating layer is fabricated on the first circuit board; A first photoresist layer is fabricated on the first insulating layer to obtain the first dielectric layer.

3. The circuit board processing method as described in claim 1, characterized in that, The deposition of the second dielectric layer on the second circuit board includes: A second insulating layer is fabricated on the second circuit board; A second photoresist layer is fabricated on the second insulating layer to obtain a second dielectric layer comprising the second insulating layer and the second photoresist layer.

4. The circuit board processing method as described in claim 3, characterized in that, Embedding target metal lines electrically connected to the first interconnect metal structure in the second dielectric layer yields a target circuit board, comprising: A metal mask layer is fabricated on the second dielectric layer; A second photoresist layer is fabricated on the metal mask layer, and a first photoresist pattern is created. On the metal mask layer, a first mask pattern is fabricated based on a first photoresist pattern; On the second dielectric layer, based on the first mask pattern, the target line trench is fabricated; The target circuit board is obtained by filling the target line trench with conductive material and embedding the target metal line that is electrically connected to the first interconnect metal structure.

5. The circuit board processing method as described in claim 4, characterized in that, Based on the first mask pattern, the target line trench is fabricated, including: according to the first mask pattern, using plasma etching technology, the target line trench is fabricated on the second dielectric layer.

6. The circuit board processing method as described in claim 4, characterized in that, The step of filling the target line trench with conductive material and embedding the target metal line electrically connected to the first interconnecting metal structure includes: Electroplating is performed on the target line trench to obtain a second metal layer; The second metal layer is etched to obtain a pre-processed circuit structure, wherein the second metal layer in the target circuit trench of the pre-processed circuit structure is flush with the second insulating layer. The second photoresist layer in the pre-processed circuit structure is removed to obtain the target metal circuit that is electrically connected to the first interconnect metal structure.

7. A circuit board structure, characterized in that, The target circuit board is obtained by the circuit board processing method described in any one of claims 1 to 6 above.

8. A circuit board processing equipment, characterized in that, Used to implement the circuit board processing method as described in any one of claims 1 to 6.

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