chip resistor

Abstract

A chip resistor (1) has a substrate (10), a first electrode (30), a second electrode (40), a first resistor body (16), a second resistor body (17), and a connecting electrode (20). The substrate (10) includes a first main surface (11). The first electrode (30) includes a first terminal electrode (31) and a first auxiliary electrode (32). The second electrode (40) includes a second terminal electrode (41) and a second auxiliary electrode (42). When the first main surface (11) of the substrate (10) is viewed from above, the first auxiliary electrode (32) has a larger area than the first terminal electrode (31), and the second auxiliary electrode (42) has a larger area than the second terminal electrode (41).

Description

Technical Field

[0001] This disclosure relates to chip resistors. Background Technology

[0002] Japanese Patent Application Publication No. 2004-200424 (Patent Document 1) discloses a chip resistor having a first electrode, a first resistive element, a conductive film, a second resistive element, and a second electrode. The first electrode is connected to the first resistive element. The second electrode is connected to the second resistive element. The conductive film electrically connects the first and second resistive elements in series.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent document 1: Japanese Patent Application Publication No. 2004-200424. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In the use of the chip resistor in Patent Document 1, there is a problem of excessive temperature rise and degradation of the chip resistor. This disclosure was made in view of the above problems, and its object is to provide a chip resistor that can improve heat dissipation.

[0008] Technical means for solving problems

[0009] The first aspect of this disclosure discloses a chip resistor comprising a substrate, a first electrode, a second electrode, a first resistive element, a second resistive element, and a connecting electrode. The substrate includes a main surface, a first end surface connected to the main surface, and a second end surface connected to the main surface. The first electrode is disposed on the first end surface side of the substrate. The second electrode is disposed on the second end surface side of the substrate. The first resistive element is disposed on the main surface of the substrate. The second resistive element is disposed on the main surface of the substrate and spaced apart from the first resistive element along the long side of the substrate, where the first end surface and the second end surface are spaced apart. The connecting electrode is disposed on the main surface of the substrate and electrically connects the first resistive element and the second resistive element in series. The first electrode includes a first terminal electrode and a first auxiliary electrode. The first terminal electrode is disposed on the main surface of the substrate and connected to the first resistive element. The first auxiliary electrode is connected to the first terminal electrode. The second electrode includes a second terminal electrode and a second auxiliary electrode. The second terminal electrode is disposed on the main surface of the substrate and connected to the second resistive element. The second auxiliary electrode is connected to the second terminal electrode. When viewed from above the main surface of the substrate, the first auxiliary electrode has an area significantly larger than that of the first terminal electrode, and the second auxiliary electrode has an area significantly larger than that of the second terminal electrode.

[0010] The second aspect of this disclosure discloses a chip resistor comprising a substrate, a first electrode, a second electrode, a first resistive element, a second resistive element, and a connecting electrode. The substrate includes a main surface, a first end surface connected to the main surface, and a second end surface connected to the main surface. The first electrode is disposed on the first end surface side of the substrate. The second electrode is disposed on the second end surface side of the substrate. The first resistive element is disposed on the main surface of the substrate. The second resistive element is disposed on the main surface of the substrate and spaced apart from the first resistive element along the long side of the substrate, where the first and second end surfaces are spaced apart. The connecting electrode is disposed on the main surface of the substrate and electrically connects the first and second resistive elements in series. The first electrode includes a first terminal electrode. The first terminal electrode is disposed on the main surface of the substrate and connected to the first resistive element. The second electrode includes a second terminal electrode. The second terminal electrode is disposed on the main surface of the substrate and connected to the second resistive element. When viewed from above the main surface of the substrate, the first gap between the first resistor and the first end face in the long side direction of the substrate is 0.3 mm or less when the substrate size in the long side direction is 1.6 mm or more, and 0.15 mm or less when the substrate size in the long side direction is 0.6 mm or more but less than 1.6 mm. When viewed from above the main surface of the substrate, the second gap between the second resistor and the second end face in the long side direction of the substrate is 0.3 mm or less when the substrate size in the long side direction is 1.6 mm or more, and 0.15 mm or less when the substrate size in the long side direction is 0.6 mm or more but less than 1.6 mm.

[0011] Invention Effects

[0012] The heat dissipation of the chip resistors of the first and second aspects of this disclosure can be improved. Attached Figure Description

[0013] Figure 1 This is a schematic top view of the chip resistor in the embodiment.

[0014] Figure 2 This is a surface-mount resistor in an implementation method. Figure 1 A schematic cross-sectional view at section line II-II shown.

[0015] Figure 3 This is a schematic cross-sectional view showing one step of a method for manufacturing a chip resistor according to an embodiment.

[0016] Figure 4 This is a schematic cross-sectional view showing one step of a method for manufacturing a chip resistor according to an embodiment.

[0017] Figure 5 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 3 and Figure 4A schematic cross-sectional view of the next process after the process shown.

[0018] Figure 6 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 5 A schematic cross-sectional view of the next process after the process shown.

[0019] Figure 7 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 6 A schematic cross-sectional view of the next process after the process shown.

[0020] Figure 8 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 7 A schematic cross-sectional view of the next process after the process shown.

[0021] Figure 9 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 8 A schematic cross-sectional view of the next process after the process shown.

[0022] Figure 10 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 9 A schematic cross-sectional view of the next process after the process shown.

[0023] Figure 11 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 10 A schematic cross-sectional view of the next process after the process shown.

[0024] Figure 12 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 11 A schematic cross-sectional view of the next process after the process shown.

[0025] Figure 13 This refers to the manufacturing method of a chip resistor in an embodiment. Figure 12 A schematic cross-sectional view of the next process after the process shown.

[0026] Figure 14 This is a schematic cross-sectional view of a chip resistor in the first variation of the embodiment.

[0027] Figure 15 This is a schematic cross-sectional view of a chip resistor in a second variation of the embodiment.

[0028] Figure 16 This is a schematic cross-sectional view of a chip resistor in the third variation of the embodiment. Detailed Implementation

[0029] The implementation method will be described below. Furthermore, reference numerals used to denote the same structure will not be repeated.

[0030] (Implementation Method)

[0031] Reference Figure 1 and Figure 2 The chip resistor 1 of the embodiment will be described below. The chip resistor 1 mainly includes a substrate 10, a first resistive element 16, a second resistive element 17, a connecting electrode 20, a first electrode 30, and a second electrode 40. The chip resistor 1 may also have an insulating protective film 24. The chip resistor 1 may also have a first stress-relieving layer 28 and a second stress-relieving layer 29. Figure 1 For ease of illustration, a portion of the first electrode 30, a portion of the second electrode 40, the insulating protective film 24, the first stress-relieving layer 28, and the second stress-relieving layer 29 are omitted.

[0032] The substrate 10 is an electrically insulating material, formed of an electrically insulating material such as aluminum oxide (Al2O3). The substrate 10 includes a first main surface 11, a second main surface 12 opposite to the first main surface 11, a first end surface 13, and a second end surface 14 opposite to the first end surface 13. The first main surface 11 and the second main surface 12 extend along a first direction (x-direction) and a second direction perpendicular to the first direction (y-direction), respectively. The first direction (x-direction) is the direction of the long side of the substrate 10. The second direction (y-direction) is the direction of the short side of the substrate 10. The first main surface 11 and the second main surface 12 are spaced apart from each other in a third direction (z-direction) perpendicular to the first direction (x-direction) and the second direction (y-direction). The third direction (z-direction) is the thickness direction of the substrate 10. When the chip resistor 1 is mounted on a circuit board (not shown), the second main surface 12 faces the circuit board.

[0033] The size L1 of the substrate 10 along its long side (x-direction) is not particularly limited, but is, for example, 0.6 mm or more and 6.4 mm or less. The size L2 of the substrate 10 along its short side (y-direction) is not particularly limited, but is, for example, 0.3 mm or more and 3.2 mm or less. The size L1 of the substrate 10 is, for example, 1.25 times or more and 2.25 times the size L2 of the substrate 10. When viewed from above the first main surface 11, the size of the substrate 10 is expressed as size L1 × size L2, and is, for example, 6.4 mm × 3.2 mm, 5.0 mm × 2.5 mm, 3.2 mm × 2.5 mm, 3.2 mm × 1.6 mm, 2.0 mm × 1.2 mm, 1.6 mm × 0.8 mm, 1.0 mm × 0.5 mm, or 0.6 mm × 0.3 mm.

[0034] The first end face 13 is connected to the first main face 11 and the second main face 12. The second end face 14 is connected to the first main face 11 and the second main face 12. The first end face 13 and the second end face 14 extend along the second direction (y direction) and the third direction (z direction), respectively. The first end face 13 and the second end face 14 are spaced apart from each other in the first direction (x direction).

[0035] The first resistor 16 and the second resistor 17, for example, have the function of limiting current or detecting current. The first resistor 16 and the second resistor 17 are disposed on the first main surface 11 of the substrate 10. The first resistor 16 and the second resistor 17 are formed, for example, by printing a paste containing glass paste in a resistive material such as ruthenium oxide (RuO2) or a silver-palladium alloy onto the first main surface 11 of the substrate 10 and then firing it. When viewed from above, the first resistor 16 and the second resistor 17 each have, for example, a rectangular shape. The first resistor 16 and the second resistor 17 are arranged in the long side direction (z-direction) of the substrate 10. The first resistor 16 and the second resistor 17 are separated from each other by a third interval G3 in the long side direction (z-direction) of the substrate 10.

[0036] The first resistor 16 is disposed on the first end face 13 side of the substrate 10. The first resistor 16 is closer to the first end face 13 than the second resistor 17.

[0037] When viewed from above the first main surface 11 of the substrate 10, the first gap G1 between the first resistor 16 and the first end face 13 in the long side direction (x direction) of the substrate 10 is, for example, 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. The first gap G1 can be 0.2 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.10 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. The first gap G1 between the first resistor 16 and the first end face 13 is smaller than the third gap G3 between the first resistor 16 and the second resistor 17 in the long side direction (x direction) of the substrate 10.

[0038] A first adjustment groove 18 is formed in the first resistive element 16. By forming the first adjustment groove 18 in the first resistive element 16, the resistance value of the chip resistor 1 (first resistive element 16) can be accurately determined.

[0039] When viewed from above the first main surface 11 of the substrate 10, the first adjustment groove 18 may, for example, have an L-shape. Specifically, when viewed from above the first main surface 11 of the substrate 10, the first adjustment groove 18 includes an adjustment groove portion 18a and an adjustment groove portion 18b. The adjustment groove portion 18a extends in a direction perpendicular to the direction of the current flowing through the first resistor 16 (the direction of the long side of the substrate 10 (x direction)) (the direction of the short side of the substrate 10 (y direction)). One end of the adjustment groove portion 18a extends to the outer periphery of the first resistor 16. The adjustment groove portion 18b extends in the direction of the current flowing through the first resistor 16 (the direction of the long side of the substrate 10 (x direction)). When viewed from above the first main surface 11 of the substrate 10, the adjustment groove portion 18b extends from the adjustment groove portion 18a toward the connecting electrode 20. The adjustment groove portion 18b is connected to the other end of the adjustment groove portion 18a.

[0040] The shortest distance D1 between the first end face 13 on the long side direction (x direction) of the substrate 10 and the first adjustment groove 18 is, for example, less than or equal to the sum of the first interval G1 and one-third of the size S1 of the first resistor 16 on the long side direction (x direction) of the substrate 10. The shortest distance D1 may also be less than 1.00 mm. In this embodiment, the shortest distance D1 is the distance between the first end face 13 on the long side direction (x direction) of the substrate 10 and the adjustment groove portion 18a. The adjustment groove portion 18a of the first adjustment groove 18 that is closest to the first end face 13 is closer to the first end face 13 than the first center line 16c of the first resistor 16 on the long side direction (x direction) of the substrate 10.

[0041] The second resistor 17 is disposed on the second end face 14 side of the substrate 10. The second resistor 17 is closer to the second end face 14 than the first resistor 16.

[0042] When viewed from above the first main surface 11 of the substrate 10, the second gap G2 between the second resistor 17 and the second end face 14 in the long side direction (x direction) of the substrate 10 is, for example, 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. The second gap G2 may also be 0.2 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.10 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. The second gap G2 between the second resistor 17 and the second end face 14 is smaller than the third gap G3 between the first resistor 16 and the second resistor 17 in the long side direction (x direction) of the substrate 10.

[0043] A second adjustment groove 19 is formed in the second resistor 17. By forming the second adjustment groove 19 in the second resistor 17, the resistance value of the chip resistor 1 (second resistor 17) can be accurately determined.

[0044] When viewed from above the first main surface 11 of the substrate 10, the second adjustment groove 19 may, for example, have an L-shape. Specifically, when viewed from above the first main surface 11 of the substrate 10, the second adjustment groove 19 includes an adjustment groove portion 19a and an adjustment groove portion 19b. The adjustment groove portion 19a extends in a direction perpendicular to the direction of the current flowing through the second resistor 17 (the direction of the long side of the substrate 10 (x-direction)) (the direction of the short side of the substrate 10 (y-direction)). One end of the adjustment groove portion 19a extends to the outer periphery of the second resistor 17. The adjustment groove portion 19b extends in the direction of the current flowing through the second resistor 17 (the direction of the long side of the substrate 10 (x-direction)). When viewed from above the first main surface 11 of the substrate 10, the adjustment groove portion 19b extends from the adjustment groove portion 19a toward the connecting electrode 20. The adjustment groove portion 19b is connected to the other end of the adjustment groove portion 19a.

[0045] The shortest distance D2 between the second end face 14 on the long side direction (x direction) of the substrate 10 and the second adjustment groove 19 is, for example, less than or equal to the sum of the second interval G2 and one-third of the dimension S2 of the second resistor 17 on the long side direction (x direction) of the substrate 10. The shortest distance D2 may also be less than 1.00 mm. In this embodiment, the shortest distance D2 is the distance between the second end face 14 on the long side direction (x direction) of the substrate 10 and the adjustment groove portion 19a. The adjustment groove portion 19a of the second adjustment groove 19, which is the shortest distance from the second end face 14, is closer to the second end face 14 than the second center line 17c of the second resistor 17 on the long side direction (x direction) of the substrate 10.

[0046] A connecting electrode 20 is disposed on the first main surface 11 of the substrate 10. The connecting electrode 20 electrically connects the first resistor 16 and the second resistor 17 in series. One end of the connecting electrode 20 is sandwiched between the first main surface 11 and the first resistor 16. The other end of the connecting electrode 20 is sandwiched between the first main surface 11 and the second resistor 17. One end of the first resistor 16 may also be sandwiched between the first main surface 11 and the connecting electrode 20. One end of the second resistor 17 may also be sandwiched between the first main surface 11 and the connecting electrode 20. The connecting electrode 20 is formed, for example, by printing a conductive paste, such as a paste containing glass paste in silver, onto the first main surface 11 of the substrate 10 and then firing it.

[0047] An insulating protective film 24 covers the first resistor 16 and the second resistor 17, protecting both resistors. The insulating protective film 24 may also cover the connecting electrode 20. The insulating protective film 24 may also cover a portion of the first terminal electrode 31 and a portion of the second terminal electrode 41. The insulating protective film 24 is located between the first auxiliary electrode 32 (first eaves 32b) and the first resistor 16, and between the second auxiliary electrode 42 (second eaves 42b) and the second resistor 17. The insulating protective film 24 includes an inner insulating protective layer 25 and an outer insulating protective layer 26.

[0048] The inner insulating protective layer 25 contacts and covers the first resistor 16 and the second resistor 17. The inner insulating protective layer 25 may also contact and cover the connecting electrode 20. The inner insulating protective layer 25 may also contact and cover a portion of the first terminal electrode 31 and a portion of the second terminal electrode 41. The inner insulating protective layer 25 may fill the first adjustment groove 18 and the second adjustment groove 19. The inner insulating protective layer 25 is formed, for example, of an insulating material such as glass. The inner insulating protective layer 25 is formed, for example, by printing a paste containing glass and then firing it. An outer insulating protective layer 26 is disposed on the inner insulating protective layer 25. The outer insulating protective layer 26 is formed, for example, of an insulating resin such as epoxy resin. The outer insulating protective layer 26 is formed, for example, by printing a paste containing epoxy resin and then firing it.

[0049] A first stress-relieving layer 28 and a second stress-relieving layer 29 are disposed on the second main surface 12 of the substrate 10. The first stress-relieving layer 28 is disposed on the portion of the second main surface 12 near the first end face 13. The second stress-relieving layer 29 is disposed on the portion of the second main surface 12 near the second end face 14. When viewed from above, the first stress-relieving layer 28 may also have a shape substantially the same as the first terminal electrode 31. When viewed from above, the second stress-relieving layer 29 may have a shape substantially the same as the second terminal electrode 41.

[0050] The first stress-relieving layer 28 and the second stress-relieving layer 29 are flexible. The first stress-relieving layer 28 and the second stress-relieving layer 29 alleviate the thermal stress caused by the difference between the coefficient of thermal expansion of the circuit board and the coefficient of thermal expansion of the chip resistor 1 (substrate 10) when the chip resistor 1 is mounted on a circuit board (not shown), and prevent cracks from forming in the chip resistor 1.

[0051] The thickness of each of the first stress-relieving layer 28 and the second stress-relieving layer 29 is, for example, 3 μm or more and 50 μm or less. Since the thickness of each of the first stress-relieving layer 28 and the second stress-relieving layer 29 is 3 μm or more, they possess sufficient flexibility to alleviate the aforementioned thermal stress. Since the thickness of each of the first stress-relieving layer 28 and the second stress-relieving layer 29 is 50 μm or less, the size of the chip resistor 1 can be miniaturized. Since the thickness of each of the first stress-relieving layer 28 and the second stress-relieving layer 29 is 50 μm or less, the curing time of the first stress-relieving layer 28 and the second stress-relieving layer 29 is shortened, allowing the chip resistor 1 to be manufactured in a shorter time.

[0052] The first stress-relieving layer 28 and the second stress-relieving layer 29 are formed, for example, of a flexible insulating resin such as epoxy resin or silicone resin. The first stress-relieving layer 28 and the second stress-relieving layer 29 are formed, for example, by printing a resin paste onto the second main surface 12 of the substrate 10 and then curing it. The first stress-relieving layer 28 and the second stress-relieving layer 29 may also be formed, for example, of a conductive resin containing conductive particles such as silver particles.

[0053] The first electrode 30 is disposed on the first end face 13 side of the substrate 10 and is connected to the first resistor 16. The first electrode 30 includes a first terminal electrode 31, a first auxiliary electrode 32, a first metal thin film layer 33, a first side electrode 34, and a first coating 35.

[0054] A first terminal electrode 31 is disposed on the first main surface 11 of the substrate 10. The first terminal electrode 31 is closer to the first end face 13 than the connecting electrode 20. The first terminal electrode 31 is connected to the first resistor 16. One end of the first terminal electrode 31 is sandwiched between the first main surface 11 and the first resistor 16. One end of the first resistor 16 may also be sandwiched between the first main surface 11 and the first terminal electrode 31. When viewed from above, the first main surface 11 of the substrate 10 overlaps with the insulating protective film 24. When viewed from above, the first terminal electrode 31 has, for example, a rectangular shape. The first terminal electrode 31 is formed, for example, by applying a conductive paste, such as a paste made by including silver in a glass paste, onto the first main surface 11 of the substrate 10 and then firing it.

[0055] A first auxiliary electrode 32 is disposed on and connected to the first terminal electrode 31. The first auxiliary electrode 32 is also disposed on the insulating protective film 24 (outer insulating protective layer 26). Specifically, the first auxiliary electrode 32 includes a first base 32a and a first eaves 32b. The first base 32a is disposed on and in contact with the first terminal electrode 31. The first eaves 32b protrudes from the first base 32a toward the connecting electrode 20. The first eaves 32b is in contact with the insulating protective film 24 (outer insulating protective layer 26).

[0056] When viewed from above on the first main surface 11 of the substrate 10, the first auxiliary electrode 32 overlaps with the first resistor 16. The first overlap width W between the first auxiliary electrode 32 and the first resistor 16 along the long side direction (x direction) of the substrate 10 is... 13 The first spacing G1 between the first resistor 16 and the first end face 13 along the long side of the substrate 10 is greater than or equal to the first distance G1. When viewed from above on the first main surface 11 of the substrate 10, the first auxiliary electrode 32 (first eaves 32b) overlaps with the insulating protective film 24. The third overlap width W between the first auxiliary electrode 32 and the insulating protective film 24 along the long side of the substrate 10 is... 14 The fourth overlap width W between the first terminal electrode 31 and the insulating protective film 24 in the long side direction of the substrate 10 is greater than that of the first terminal electrode 31. 15 big.

[0057] When viewed from above on the first main surface 11 of the substrate 10, the first auxiliary electrode 32 has an area larger than the first terminal electrode 31. The first width W of the first auxiliary electrode 32 in the long side direction (x-direction) of the substrate 10 is... 11 The width W of the first electrode of the first terminal electrode 31 in the long side direction of the substrate 10 is greater than that of the first electrode. 12 Large. The first width W of the first auxiliary electrode 32 in the long side direction of the substrate 10. 11 The first distance G1 between the first resistive element 16 and the first end face 13 in the long side direction of the substrate 10 is greater than or equal to the first distance G1. The maximum thickness of the first auxiliary electrode 32 is greater than the maximum thickness of the first terminal electrode 31. The first auxiliary electrode 32 has a larger volume than the first terminal electrode 31. The first auxiliary electrode 32 is formed, for example, by applying a conductive paste, such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin, onto the first terminal electrode 31 and the insulating protective film 24 (outer insulating protective layer 26) and then firing it.

[0058] A first metal thin film layer 33 is disposed on the first stress-relieving layer 28. Even if the first stress-relieving layer 28 is an electrical insulator, a first coating 35 can still be formed on the first stress-relieving layer 28. The first metal thin film layer 33 is formed, for example, from a conductive material such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin. The first metal thin film layer 33 is formed, for example, by printing a conductive paste such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin onto the first stress-relieving layer 28.

[0059] A first side electrode 34 is disposed on a first end face 13, a first terminal electrode 31, a first auxiliary electrode 32, and a first metal thin film layer 33 of a substrate 10. The first side electrode 34 includes a portion overlapping the first end face 13, a portion overlapping the first main face 11, and a portion overlapping the second main face 12. The first side electrode 34 enables the first auxiliary electrode 32 and the first metal thin film layer 33 to conduct to each other, and also enables the first terminal electrode 31 and the first metal thin film layer 33 to conduct to each other. The first side electrode 34 can be formed, for example, by printing and firing a conductive paste containing silver glass paste. The first side electrode 34 can also be formed by sputtering.

[0060] A first plating layer 35 is disposed on the first auxiliary electrode 32, the first side electrode 34, and the first metal thin film layer 33. The first plating layer 35 includes a first inner plating layer 36 and a first outer plating layer 37. The first inner plating layer 36 is disposed on the first auxiliary electrode 32, the first side electrode 34, and the first metal thin film layer 33. The first inner plating layer 36 protects the first terminal electrode 31, the first auxiliary electrode 32, the first side electrode 34, and the first metal thin film layer 33 from heat and impact. The first inner plating layer 36 is, for example, a nickel plating layer. The first outer plating layer 37 is disposed on the first inner plating layer 36. The first outer plating layer 37 is formed of a material that is easier to adhere to for bonding components such as solder compared to the first inner plating layer 36. The first outer plating layer 37 is, for example, a tin plating layer. Bonding components are attached to the first outer plating layer 37 and the wiring pattern of a circuit board (not shown), and the chip resistor 1 is mounted on the circuit board.

[0061] The second electrode 40 is disposed on the second end face 14 side of the substrate 10 and is connected to the second resistor 17. The second electrode 40 has the same electrode structure as the first electrode 30. Specifically, the second electrode 40 includes a second terminal electrode 41, a second auxiliary electrode 42, a second metal thin film layer 43, a second side electrode 44, and a second coating 45.

[0062] The second terminal electrode 41 is disposed on the first main surface 11 of the substrate 10. The second terminal electrode 41 is closer to the second end surface 14 than the connecting electrode 20. The second terminal electrode 41 is connected to the second resistor 17. One end of the second terminal electrode 41 is sandwiched between the first main surface 11 and the second resistor 17. One end of the second resistor 17 may also be sandwiched between the first main surface 11 and the second terminal electrode 41. When viewed from above the first main surface 11 of the substrate 10, the second terminal electrode 41 overlaps with the insulating protective film 24. When viewed from above the first main surface 11 of the substrate 10, the second terminal electrode 41 has, for example, a rectangular shape. The second terminal electrode 41 is formed, for example, by applying a conductive paste, such as a paste in which silver is contained in glass paste, onto the first main surface 11 of the substrate 10 and then firing it.

[0063] The second auxiliary electrode 42 is disposed on and connected to the second terminal electrode 41. The second auxiliary electrode 42 is also disposed on the insulating protective film 24 (outer insulating protective layer 26). Specifically, the second auxiliary electrode 42 includes a second base 42a and a second eaves 42b. The second base 42a is disposed on and in contact with the second terminal electrode 41. The second eaves 42b protrudes from the second base 42a toward the connecting electrode 20. The second eaves 42b is in contact with the insulating protective film 24 (outer insulating protective layer 26).

[0064] When viewed from above on the first main surface 11 of the substrate 10, the second auxiliary electrode 42 overlaps with the second resistor 17. The second overlap width W between the second auxiliary electrode 42 and the second resistor 17 along the long side direction (x-direction) of the substrate 10 is... 23 The second spacing G2 between the second resistor 17 and the second end face 14 in the long side direction of the substrate 10 is greater than or equal to the second spacing G2. When viewed from above the first main surface 11 of the substrate 10, the second auxiliary electrode 42 (second eaves 42b) overlaps with the insulating protective film 24. The fifth overlap width W between the second auxiliary electrode 42 and the insulating protective film 24 in the long side direction of the substrate 10 is... 24 The sixth overlap width W between the second terminal electrode 41 and the insulating protective film 24 in the long side direction of the substrate 10 25 big.

[0065] When viewed from above on the first main surface 11 of the substrate 10, the second auxiliary electrode 42 has an area larger than the second terminal electrode 41. The second width W of the second auxiliary electrode 42 in the long side direction (x-direction) of the substrate 10 is... 21 The second electrode width W of the second terminal electrode 41 in the long side direction of the substrate 10 is greater than that of the second electrode. 22 Large. The second width W of the second auxiliary electrode 42 in the long side direction of the substrate 10. 21The second distance G2 between the second resistive element 17 and the second end face 14 in the long side direction of the substrate 10 is greater than or equal to the second distance G2. The maximum thickness of the second auxiliary electrode 42 is greater than the maximum thickness of the second terminal electrode 41. The second auxiliary electrode 42 has a larger volume than the second terminal electrode 41. The second auxiliary electrode 42 is formed, for example, by applying a conductive paste containing a binder resin and silver particles dispersed in the binder resin onto the second terminal electrode 41 and the insulating protective film 24 (outer insulating protective layer 26) and then firing it.

[0066] A second metal thin film layer 43 is disposed on the second stress-relieving layer 29. Even if the second stress-relieving layer 29 is an electrical insulator, a second coating 45 can still be formed on the second stress-relieving layer 29 by the second metal thin film layer 43. The second metal thin film layer 43 is formed, for example, from a conductive material such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin. The second metal thin film layer 43 is formed, for example, by printing a conductive paste such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin onto the second stress-relieving layer 29.

[0067] The second side electrode 44 is disposed on the second end face 14, the second terminal electrode 41, the second auxiliary electrode 42, and the second metal thin film layer 43 of the substrate 10. The second side electrode 44 includes a portion overlapping the second end face 14, a portion overlapping the first main face 11, and a portion overlapping the second main face 12. The second side electrode 44 enables the second auxiliary electrode 42 and the second metal thin film layer 43 to conduct to each other, and also enables the second terminal electrode 41 and the second metal thin film layer 43 to conduct to each other. The second side electrode 44 can be formed, for example, by printing and firing a conductive paste in which silver is contained in a glass paste. The second side electrode 44 can also be formed by sputtering.

[0068] A second plating layer 45 is disposed on the second auxiliary electrode 42, the second side electrode 44, and the second metal thin film layer 43. The second plating layer 45 includes a second inner plating layer 46 and a second outer plating layer 47. The second inner plating layer 46 is disposed on the second auxiliary electrode 42, the second side electrode 44, and the second metal thin film layer 43. The second inner plating layer 46 protects the second terminal electrode 41, the second auxiliary electrode 42, the second side electrode 44, and the second metal thin film layer 43 from heat and shock. The second inner plating layer 46 is, for example, a nickel plating layer. The second outer plating layer 47 is disposed on the second inner plating layer 46. The second outer plating layer 47 is formed of a material that, compared to the second inner plating layer 46, facilitates the adhesion of bonding components such as solder. The second outer plating layer 47 is, for example, a tin plating layer. Bonding components are attached to the second outer plating layer 47 and the wiring pattern of a circuit board (not shown), and the chip resistor 1 is mounted on the circuit board.

[0069] Reference Figures 1 to 13An example of the manufacturing method of the chip resistor 1 in this embodiment will be described.

[0070] Reference Figure 3 and Figure 4 A sheet substrate 10s made of alumina is prepared. The sheet substrate 10s includes a first main surface 11 and a second main surface 12 opposite to the first main surface 11. A plurality of first dividing grooves 10g and a plurality of second dividing grooves 10h are formed on the first main surface 11 and the second main surface 12 of the sheet substrate 10s. The plurality of first dividing grooves 10g extend along a second direction (y direction) and are spaced apart from each other in a first direction (x direction). The plurality of second dividing grooves 10h extend along the first direction (x direction) and are spaced apart from each other in the second direction (y direction). The area defined by the first dividing grooves 10g and the second dividing grooves 10h corresponds to the substrate 10 of the chip resistor 1.

[0071] Reference Figure 5 Terminal electrodes 21 and connecting electrodes 20 are formed on the first main surface 11 of the sheet substrate 10s. The terminal electrodes 21 are formed on the first main surface 11 of the sheet substrate 10s in a manner that spans the first dividing groove 10g of the sheet substrate 10s. The connecting electrodes 20 are formed in the first direction (x direction) between a pair of adjacent terminal electrodes 21. The terminal electrodes 21 and the connecting electrodes 20 are formed, for example, by printing a conductive paste, such as a paste in which silver is contained in glass paste, onto the first main surface 11 and then firing it.

[0072] Reference Figure 6 A first resistor 16 and a second resistor 17 are formed on the first main surface 11 of the sheet substrate 10s. The first resistor 16 is in contact with the terminal electrode 21 and the connection electrode 20. The second resistor 17 is in contact with the terminal electrode 21 and the connection electrode 20. The first resistor 16 and the second resistor 17 are spaced apart from each other. The first resistor 16 and the second resistor 17 are formed by printing and firing a paste in which a resistive material such as ruthenium oxide (RuO2) or a silver-palladium alloy contains a glass paste. Alternatively, the first resistor 16 and the second resistor 17 may be formed on the first main surface 11 of the sheet substrate 10s, and then the terminal electrode 21 and the connection electrode 20 may be formed.

[0073] Reference Figure 7 An inner insulating protective layer 25 is formed covering the first resistor 16 and the second resistor 17. The inner insulating protective layer 25 is formed, for example, by printing a glass-containing paste onto the first resistor 16 and the second resistor 17 and then firing it. The inner insulating protective layer 25 may also be formed on the connecting electrode 20. The inner insulating protective layer 25 is... Figure 8In the adjustment groove forming process shown, the thermal shock acting on the first resistor 16 and the second resistor 17 is mitigated and the microparticles generated during the formation of the first adjustment groove 18 and the second adjustment groove 19 are prevented from adhering to the first resistor 16 and the second resistor 17, and the first resistance value of the first resistor 16 and the second resistance value of the second resistor 17 are changed.

[0074] Reference Figure 8 A first adjustment groove 18 and a second adjustment groove 19 are formed in the first resistor 16 and the second resistor 17. The first adjustment groove 18 and the second adjustment groove 19 are also formed in the inner insulating protective layer 25. The first adjustment groove 18 and the second adjustment groove 19 are formed, for example, by irradiating the first resistor 16 and the second resistor 17 with a laser. Specifically, by scanning the laser along the second direction (y direction), an adjustment groove portion 18a is formed in the first resistor 16 and an adjustment groove portion 19a is formed in the second resistor 17. Then, by scanning the laser along the first direction (x direction), an adjustment groove portion 18b is formed in the first resistor 16 and an adjustment groove portion 19b is formed in the second resistor 17. The formation of the first adjustment groove 18 and the second adjustment groove 19 ends when the sum of the first resistance value of the first resistor 16 and the second resistance value of the second resistor 17 becomes the target resistance value of the chip resistor 1.

[0075] Reference Figure 9 An outer insulating protective layer 26 is formed on the inner insulating protective layer 25. Specifically, the outer insulating protective layer 26 is formed by printing an epoxy resin-containing paste onto the inner insulating protective layer 25 and allowing it to cure. The outer insulating protective layer 26 may also fill the first adjustment groove 18 and the second adjustment groove 19. This forms an insulating protective film 24 comprising the inner insulating protective layer 25 and the outer insulating protective layer 26.

[0076] Reference Figure 10 A stress-relief layer 27 is formed on the second main surface 12 of the sheet substrate 10s. The stress-relief layer 27 is formed across the first dividing groove 10g. When viewed from above, the stress-relief layer 27 may also have a shape substantially the same as the terminal electrode 21. The stress-relief layer 27 is formed by printing a paste containing epoxy resin or silicone resin onto the second main surface 12 and allowing it to cure.

[0077] Reference Figure 11 A metal thin film layer 23 is formed on the stress relief layer 27. The metal thin film layer 23 is formed, for example, by printing a conductive paste, such as a silver paste containing an adhesive resin and silver particles dispersed in the adhesive resin, onto the second stress relief layer 29.

[0078] Reference Figure 11An auxiliary electrode 22 is formed on the terminal electrode 21 and the insulating protective film 24 (outer insulating protective layer 26). The auxiliary electrode 22 is formed, for example, by applying a conductive paste containing an adhesive resin and silver particles dispersed in the adhesive resin onto the first terminal electrode 31 and the insulating protective film 24 (outer insulating protective layer 26) and then firing it. When viewed from above on the first main surface 11 of the substrate 10, the first auxiliary electrode 32 overlaps with the first resistive element 16.

[0079] Reference Figure 12 The sheet substrate 10s is cut along multiple first dividing grooves 10g. The sheet substrate 10s is divided into multiple strip substrates 10t. By cutting the sheet substrate 10s along multiple first dividing grooves 10g, a first end face 13 and a second end face 14 are formed. By cutting the sheet substrate 10s along the first dividing grooves 10g, the terminal electrode 21 is divided into a first terminal electrode 31 and a second terminal electrode 41, the auxiliary electrode 22 is divided into a first auxiliary electrode 32 and a second auxiliary electrode 42, and the metal thin film layer 23 is divided into a first metal thin film layer 33 and a second metal thin film layer 43.

[0080] Reference Figure 13 A first side electrode 34 and a second side electrode 44 are formed on the first end face 13 and the second end face 14 of the strip substrate 10t. The first side electrode 34 is formed, for example, by printing a conductive paste, such as a paste containing silver and glass slurry, onto the first end face 13, the first terminal electrode 31, the first auxiliary electrode 32, and the first metal thin film layer 33, and then firing it. The second side electrode 44 is formed, for example, by printing a conductive paste, such as a paste containing silver and glass slurry, onto the second end face 14, the second terminal electrode 41, the second auxiliary electrode 42, and the second metal thin film layer 43, and then firing it. The first side electrode 34 and the second side electrode 44 can also be formed by sputtering.

[0081] Then, along multiple second dividing slots 10h (refer to...) Figure 4 The strip substrate 10t is cut. The strip substrate 10t is divided into multiple substrates 10.

[0082] Next, a first coating 35 and a second coating 45 are formed. The first coating 35 is formed on the first auxiliary electrode 32, the first side electrode 34, and the first metal thin film layer 33. The second coating 45 is formed on the second auxiliary electrode 42, the second side electrode 44, and the second metal thin film layer 43.

[0083] Specifically, a first inner plating layer 36 is formed on the first auxiliary electrode 32, the first side electrode 34, and the first metal thin film layer 33. A second inner plating layer 46 is formed on the second auxiliary electrode 42, the second side electrode 44, and the second metal thin film layer 43. The first inner plating layer 36 and the second inner plating layer 46 are, for example, nickel plating layers. Then, a first outer plating layer 37 is formed on the first inner plating layer 36. A second outer plating layer 47 is formed on the second inner plating layer 46. The first outer plating layer 37 and the second outer plating layer 47 are, for example, tin plating layers. Thus, a... Figure 1 and Figure 2 The chip resistor 1 shown.

[0084] (Modified Example)

[0085] In a first variation of this embodiment, when viewed from above the first main surface 11 of the substrate 10, the first adjustment groove 18 and the second adjustment groove 19 may also have Figure 14 The shape is an L-shape as shown. Specifically, when viewed from above on the first main surface 11 of the substrate 10, the adjustment groove portion 18b extends from the adjustment groove portion 18a toward the first end surface 13. The shortest distance D1 is the distance between the first end surface 13 and the adjustment groove portion 18b in the long side direction (x direction) of the substrate 10. When viewed from above on the first main surface 11 of the substrate 10, the adjustment groove portion 19b extends from the adjustment groove portion 19a toward the second end surface 14. The shortest distance D2 is the distance between the second end surface 14 and the adjustment groove portion 19b in the long side direction (x direction) of the substrate 10.

[0086] In a second variation of this embodiment, when viewed from above the first main surface 11 of the substrate 10, the first adjustment groove 18 and the second adjustment groove 19 may also have Figure 15 The hook shape is as shown. Specifically, the first adjustment groove 18 includes adjustment groove portion 18a, adjustment groove portion 18b, and adjustment groove portion 18c. The second adjustment groove 19 includes adjustment groove portion 19a, adjustment groove portion 19b, and adjustment groove portion 19c.

[0087] The adjustment groove portion 18a extends in a direction perpendicular to the direction of the current flowing through the first resistor 16 (the direction of the long side of the substrate 10 (x direction)) (the direction of the short side of the substrate 10 (y direction)). One end of the adjustment groove portion 18a extends to the outer periphery of the first resistor 16. The adjustment groove portion 18b extends in the direction of the current flowing through the first resistor 16 (the direction of the long side of the substrate 10 (x direction)). When viewed from above on the first main surface 11 of the substrate 10, the adjustment groove portion 18b extends from the adjustment groove portion 18a toward the connecting electrode 20. One end of the adjustment groove portion 18b is connected to the other end of the adjustment groove portion 18a. The adjustment groove portion 18c extends in a direction perpendicular to the direction of the current flowing through the first resistor 16 (the direction of the long side of the substrate 10 (x direction)) (the direction of the short side of the substrate 10 (y direction)). The other end of the adjustment groove portion 18c is connected to the other end of the adjustment groove portion 18b. The shortest distance D1 is the distance between the first end face 13 and the adjustment groove portion 18a on the long side direction (x direction) of the substrate 10.

[0088] The adjustment groove portion 19a extends in a direction perpendicular to the direction of the current flowing through the second resistor 17 (the direction of the long side of the substrate 10, x-direction) (the direction of the short side of the substrate 10, y-direction). One end of the adjustment groove portion 19a extends to the outer periphery of the second resistor 17. The adjustment groove portion 19b extends in the direction of the current flowing through the second resistor 17 (the direction of the long side of the substrate 10, x-direction). When viewed from above on the first main surface 11 of the substrate 10, the adjustment groove portion 19b extends from the adjustment groove portion 19a toward the connecting electrode 20. One end of the adjustment groove portion 19b is connected to the other end of the adjustment groove portion 19a. The adjustment groove portion 19c extends in a direction perpendicular to the direction of the current flowing through the second resistor 17 (the direction of the long side of the substrate 10, x-direction) (the direction of the short side of the substrate 10, y-direction) (the direction of the short side of the substrate 10). The other end of the adjustment groove portion 19c is connected to the other end of the adjustment groove portion 19b. The shortest distance D2 is the distance between the second end face 14 on the long side direction (x direction) of the substrate 10 and the adjustment groove portion 19a.

[0089] In a third variation of this embodiment, when viewed from above the first main surface 11 of the substrate 10, the first adjustment groove 18 and the second adjustment groove 19 may also have Figure 16 The hook shape is as shown. Specifically, the first adjustment groove 18 includes adjustment groove portion 18a, adjustment groove portion 18b, and adjustment groove portion 18c. The second adjustment groove 19 includes adjustment groove portion 19a, adjustment groove portion 19b, and adjustment groove portion 19c.

[0090] The first adjustment groove 18 of the third variation differs from the first adjustment groove 18 of the second variation in the following aspects. When viewed from above the first main surface 11 of the substrate 10, the adjustment groove portion 18b extends from the adjustment groove portion 18a toward the first end face 13. The shortest distance D1 is the distance between the first end face 13 and the adjustment groove portion 18c in the long side direction (x direction) of the substrate 10.

[0091] The second adjustment groove 19 of the third modification differs from the second adjustment groove 19 of the second modification in the following aspects. When viewed from above the first main surface 11 of the substrate 10, the adjustment groove portion 19b extends from the adjustment groove portion 19a toward the second end surface 14. The shortest distance D2 is the distance between the second end surface 14 and the adjustment groove portion 19c in the long side direction (x direction) of the substrate 10.

[0092] In the fourth variation of this embodiment, the second adjustment groove 19 may also be omitted.

[0093] The effects of the chip resistor 1 in this embodiment will be explained.

[0094] The chip resistor 1 of this embodiment includes a substrate 10, a first electrode 30, a second electrode 40, a first resistive element 16, a second resistive element 17, and a connecting electrode 20. The substrate 10 includes a main surface (first main surface 11), a first end surface 13 connected to the main surface, and a second end surface 14 connected to the main surface. The first electrode 30 is disposed on the first end surface 13 side of the substrate 10. The second electrode 40 is disposed on the second end surface 14 side of the substrate 10. The first resistive element 16 is disposed on the main surface of the substrate 10. The second resistive element 17 is disposed on the main surface of the substrate 10 and is spaced apart from the first resistive element 16 in the long side direction (x-direction) of the substrate 10, which is spaced apart from the first end surface 13 and the second end surface 14. The connecting electrode 20 is disposed on the main surface of the substrate 10 and electrically connects the first resistive element 16 and the second resistive element 17 in series. The first electrode 30 includes a first terminal electrode 31 and a first auxiliary electrode 32. The first terminal electrode 31 is disposed on the main surface of the substrate 10 and connected to the first resistive element 16. The first auxiliary electrode 32 is connected to the first terminal electrode 31. The second electrode 40 includes a second terminal electrode 41 and a second auxiliary electrode 42. The second terminal electrode 41 is disposed on the main surface of the substrate 10 and is connected to the second resistor 17. The second auxiliary electrode 42 is connected to the second terminal electrode 41. When viewed from above on the main surface of the substrate 10, the first auxiliary electrode 32 has a larger area than the first terminal electrode 31, and the second auxiliary electrode 42 has a larger area than the second terminal electrode 41.

[0095] When the first resistor 16 is positioned closer to the first end face 13 of the substrate 10 and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10, the areas of the first terminal electrode 31 and the second terminal electrode 41 are reduced when viewed from above the main surface (first main surface 11) of the substrate 10. However, in the chip resistor 1, when viewed from above the main surface of the substrate 10, the first auxiliary electrode 32 has a larger area than the first terminal electrode 31, and the second auxiliary electrode 42 has a larger area than the second terminal electrode 41. Therefore, even though the areas of the first terminal electrode 31 and the second terminal electrode 41 are reduced when viewed from above the main surface of the substrate 10, the heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1 through the first electrode 30 and the second electrode 40. This improves the heat dissipation of the chip resistor 1. Furthermore, because the heat dissipation of the chip resistor 1 is improved, the short-time overload (STOL) characteristic of the chip resistor 1 can also be improved.

[0096] When viewed from above, the first auxiliary electrode 32 overlaps with the first resistor 16, and the second auxiliary electrode 42 overlaps with the second resistor 17.

[0097] Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1 through the first electrode 30 and the second electrode 40. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 can also be improved.

[0098] In the chip resistor 1 of this embodiment, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first gap G1 between the first resistive element 16 and the first end face 13 in the long side direction (x direction) of the substrate 10 is 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and is 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. When viewed from above on the main surface of the substrate 10, the second gap G2 between the second resistive element 17 and the second end face 14 in the long side direction of the substrate 10 is 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and is 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm.

[0099] Therefore, the first resistor 16 is positioned closer to the first end face 13 of the substrate 10, and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 are also improved.

[0100] In the chip resistor 1 of this embodiment, the first width W of the first auxiliary electrode 32 in the long side direction (x direction) of the substrate 10 is... 11 The width W of the first electrode of the first terminal electrode 31 in the long side direction of the substrate 10 is greater than that of the first electrode. 12 Large. The second width W of the second auxiliary electrode 42 in the long side direction of the substrate 10. 21 The second electrode width W of the second terminal electrode 41 in the long side direction of the substrate 10 is greater than that of the second electrode. 22 big.

[0101] Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1 through the first electrode 30 and the second electrode 40. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 can also be improved.

[0102] In the chip resistor 1 of this embodiment, the first width W of the first auxiliary electrode 32 in the long side direction (x direction) of the substrate 10 is... 11 The first gap G1 between the first resistor 16 and the first end face 13 in the long side direction of the substrate 10 is greater than or equal to the second width W of the second auxiliary electrode 42 in the long side direction of the substrate 10. 21 The second interval G2 between the second resistor 17 and the second end face 14 in the long side direction of the substrate 10 is greater than or equal to the second interval G2.

[0103] Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The first resistor 16 is positioned closer to the first end face 13 of the substrate 10, and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 can also be improved.

[0104] In the chip resistor 1 of this embodiment, the first auxiliary electrode 32 on the long side direction (x direction) of the substrate 10 overlaps with the first resistive body 16 by a first width W. 13The first interval G1 between the first resistor 16 and the first end face 13 along the long side of the substrate 10 is greater than or equal to the first spacing G1. The second overlap width W between the second auxiliary electrode 42 and the second resistor 17 along the long side of the substrate 10 is greater than or equal to the second overlap width W. 23 The second interval G2 between the second resistor 17 and the second end face 14 in the long side direction of the substrate 10 is greater than or equal to the second interval G2.

[0105] Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The first resistor 16 is positioned closer to the first end face 13 of the substrate 10, and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 can also be improved.

[0106] The chip resistor 1 in this embodiment also has an insulating protective film 24 covering the first resistive element 16 and the second resistive element 17. The insulating protective film 24 is located between the first auxiliary electrode 32 and the first resistive element 16, and between the second auxiliary electrode 42 and the second resistive element 17.

[0107] The first auxiliary electrode 32 and the second auxiliary electrode 42 are disposed on the insulating protective film 24. Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1 through the first electrode 30 and the second electrode 40. This improves the heat dissipation of the chip resistor 1. The STOL characteristic of the chip resistor 1 can also be improved. The insulating protective film 24 protects the first resistor 16 and the second resistor 17, thus the chip resistor 1 has stable performance and a longer lifespan.

[0108] In the chip resistor 1 of this embodiment, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the first terminal electrode 31 overlap with the insulating protective film 24, and the second auxiliary electrode 42 and the second terminal electrode 41 also overlap with the insulating protective film 24. The third overlap width W between the first auxiliary electrode 32 and the insulating protective film 24 in the long side direction (x direction) of the substrate 10 is... 14 The fourth overlap width W between the first terminal electrode 31 and the insulating protective film 24 in the long side direction of the substrate 10 is greater than that of the first terminal electrode 31. 15 Large. The second auxiliary electrode 42 in the long side direction of the substrate 10 overlaps with the fifth overlap width W of the insulating protective film 24. 24 The sixth overlap width W between the second terminal electrode 41 and the insulating protective film 24 in the long side direction of the substrate 1025 big.

[0109] Therefore, when viewed from above on the main surface (first main surface 11) of the substrate 10, the first auxiliary electrode 32 and the second auxiliary electrode 42 have a large area. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1 through the first electrode 30 and the second electrode 40. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 can also be improved.

[0110] The chip resistor 1 of this embodiment includes a substrate 10, a first electrode 30, a second electrode 40, a first resistive element 16, a second resistive element 17, and a connecting electrode 20. The substrate 10 includes a main surface (first main surface 11), a first end surface 13 connected to the main surface, and a second end surface 14 connected to the main surface. The first electrode 30 is disposed on the first end surface 13 side of the substrate 10. The second electrode 40 is disposed on the second end surface 14 side of the substrate 10. The first resistive element 16 is disposed on the main surface of the substrate 10. The second resistive element 17 is disposed on the main surface of the substrate 10 and is spaced apart from the first resistive element 16 in the long side direction (x-direction) of the substrate 10, which is spaced apart from the first end surface 13 and the second end surface 14. The connecting electrode 20 is disposed on the main surface of the substrate 10 and electrically connects the first resistive element 16 and the second resistive element 17 in series. The first electrode 30 includes a first terminal electrode 31. The first terminal electrode 31 is disposed on the main surface of the substrate 10 and connected to the first resistive element 16. The second electrode 40 includes a second terminal electrode 41. The second terminal electrode 41 is disposed on the main surface of the substrate 10 and connected to the second resistor 17. When viewed from above the main surface of the substrate 10, the first gap G1 between the first resistor 16 and the first end face 13 in the long side direction of the substrate 10 is 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm. When viewed from above the main surface of the substrate 10, the second gap G2 between the second resistor 17 and the second end face 14 in the long side direction of the substrate 10 is 0.3 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 1.6 mm or more, and 0.15 mm or less when the size L1 of the substrate 10 in the long side direction (x direction) is 0.6 mm or more and less than 1.6 mm.

[0111] Therefore, the first resistor 16 is positioned closer to the first end face 13 of the substrate 10, and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1, improving the heat dissipation of the chip resistor 1. Furthermore, because the heat dissipation of the chip resistor 1 is improved, the STOL characteristic of the chip resistor 1 can also be improved.

[0112] In the chip resistor 1 of this embodiment, the first interval G1 between the first resistive element 16 and the first end face 13 and the second interval G2 between the second resistive element 17 and the second end face 14 are smaller than the third interval G3 between the first resistive element 16 and the second resistive element 17 in the long side direction (x direction) of the substrate 10.

[0113] Therefore, the first resistor 16 is positioned closer to the first end face 13 of the substrate 10, and the second resistor 17 is positioned closer to the second end face 14 of the substrate 10. The heat generated by the first resistor 16 and the second resistor 17 can be efficiently dissipated to the outside of the chip resistor 1. This improves the heat dissipation of the chip resistor 1. The STOL characteristics of the chip resistor 1 are also improved.

[0114] In the chip resistor 1 of this embodiment, a first adjustment groove 18 is formed in the first resistive element 16. The shortest distance D1 between the first end face 13 in the long side direction (x direction) of the substrate 10 and the first adjustment groove 18 is less than or equal to the sum of the first interval G1 and one-third of the size S1 of the first resistive element 16 in the long side direction (x direction) of the substrate 10.

[0115] When current flows through the chip resistor 1, the temperature around the first adjustment groove 18 in the first resistive element 16 is the highest within the first resistive element 16. In the chip resistor 1, the first adjustment groove 18 is positioned closer to the first end face 13 of the substrate 10. Therefore, the heat generated in the first resistive element 16 can be efficiently dissipated to the outside of the chip resistor 1, improving the heat dissipation of the chip resistor 1. The STOL characteristic of the chip resistor 1 can also be improved. By forming the first adjustment groove 18 in the first resistive element 16, the resistance value of the chip resistor 1 (first resistive element 16) can be accurately determined.

[0116] In the chip resistor 1 of this embodiment, a second adjustment groove 19 is formed in the second resistor body 17. The shortest distance D2 between the second end face 14 in the long side direction (x direction) of the substrate 10 and the second adjustment groove 19 is less than or equal to the sum of the second interval G2 and one-third of the dimension S2 of the second resistor body 17 in the long side direction (x direction) of the substrate 10.

[0117] When current flows through the chip resistor 1, the temperature around the second adjustment slot 19 in the second resistive element 17 is the highest within the second resistive element 17. In the chip resistor 1, the second adjustment slot 19 is positioned closer to the second end face 14 of the substrate 10. Therefore, the heat generated in the second resistive element 17 can be efficiently dissipated to the outside of the chip resistor 1, improving the heat dissipation of the chip resistor 1. The STOL characteristic of the chip resistor 1 can also be improved. By forming the second adjustment slot 19 in the second resistive element 17, the resistance value of the chip resistor 1 (second resistive element 17) can be accurately determined.

[0118] In the chip resistor 1 of this embodiment, a first adjustment groove 18 is formed in the first resistive body 16. The first groove portion of the first adjustment groove 18 that is the shortest distance from the first end face 13 (for example, any of the adjustment groove portions 18a, 18b, and 18c) is closer to the first end face 13 than the first center line 16c of the first resistive body 16 in the long side direction (x direction) of the substrate 10.

[0119] When current flows through the chip resistor 1, the temperature around the first adjustment groove 18 in the first resistive element 16 is the highest within the first resistive element 16. In the chip resistor 1, the first adjustment groove 18 is positioned closer to the first end face 13 of the substrate 10. Therefore, the heat generated in the first resistive element 16 can be efficiently dissipated to the outside of the chip resistor 1, improving the heat dissipation of the chip resistor 1. The STOL characteristic of the chip resistor 1 can also be improved. By forming the first adjustment groove 18 in the first resistive element 16, the resistance value of the chip resistor 1 (first resistive element 16) can be accurately determined.

[0120] In the chip resistor 1 of this embodiment, a second adjustment groove 19 is formed in the second resistive body 17. The second groove portion of the second adjustment groove 19 that is closest to the second end face 14 (for example, one of the adjustment groove portions 19a, 19b, 19c) is closer to the second end face 14 than the second center line 17c of the second resistive body 17 in the long side direction (x direction) of the substrate 10.

[0121] When current flows through the chip resistor 1, the temperature around the second adjustment groove 19 in the second resistive element 17 is the highest within the second resistive element 17. In the chip resistor 1, the second adjustment groove 19 is located closer to the second end face 14 of the substrate 10. Therefore, the heat generated in the second resistive element 17 can be efficiently dissipated to the outside of the chip resistor 1, improving the heat dissipation of the chip resistor 1. The STOL characteristic of the chip resistor 1 can also be improved. By forming the second adjustment groove 19 in the second resistive element 17, the resistance value of the chip resistor 1 (second resistive element 17) can be accurately determined.

[0122] The embodiments and variations thereof disclosed herein should be considered as examples rather than limitations. The scope of this disclosure is defined not by the foregoing description but by the scope of the claims, and should be considered to include all modifications within the meaning and scope equivalent to the scope of the claims.

[0123] Symbol Explanation

[0124] 1. Chip resistor, 10. Substrate, 10g. First dividing groove, 10h. Second dividing groove, 10s. Sheet substrate, 10t. Strip substrate, 11. First main surface, 12. Second main surface, 13. First end face, 14. Second end face, 16. First resistive element, 16c. First center line, 17. Second resistive element, 17c. Second center line, 18. First adjustment groove, 18a, 18b, 19a, 19b. Adjustment groove portions, 19. Second adjustment groove, 20. Connecting electrode, 21. Terminal electrode, 22. Auxiliary electrode, 23. Metal thin film layer, 24. Insulating protective film, 25. Inner insulating protective layer, 26. Outer insulating protective layer. Layer, 27 Stress-relieving layer, 28 First stress-relieving layer, 29 Second stress-relieving layer, 30 First electrode, 31 First terminal electrode, 32 First auxiliary electrode, 32a First base, 32b First eaves, 33 First metal thin film layer, 34 First side electrode, 35 First coating, 36 First inner coating, 37 First outer coating, 40 Second electrode, 41 Second terminal electrode, 42 Second auxiliary electrode, 42a Second base, 42b Second eaves, 43 Second metal thin film layer, 44 Second side electrode, 45 Second coating, 46 Second inner coating, 47 Second outer coating.

Claims

1. A chip resistor, characterized in that, have: A substrate comprising a main surface, a first end surface connected to the main surface, and a second end surface connected to the main surface; A first electrode is disposed on the first end face side of the substrate; The second electrode is disposed on the second end face side of the substrate; A first resistive element is disposed on the main surface; A second resistor is disposed on the main surface and spaced apart from the first resistor along the long side of the substrate, which is spaced apart from the first end face and the second end face; and A connecting electrode is disposed on the main surface, and the first resistive element and the second resistive element are electrically connected in series. The first electrode includes a first terminal electrode and a first auxiliary electrode. The first terminal electrode is disposed on the main surface and connected to the first resistor. The first auxiliary electrode is connected to the first terminal electrode. The second electrode includes a second terminal electrode and a second auxiliary electrode. The second terminal electrode is disposed on the main surface and connected to the second resistor. The second auxiliary electrode is connected to the second terminal electrode. When viewed from above the main surface, the first auxiliary electrode has an area larger than that of the first terminal, and the second auxiliary electrode has an area larger than that of the second terminal. When viewed from above, the first gap between the first resistor and the first end face in the long side direction of the substrate is 0.3 mm or less if the size of the substrate in the long side direction is 1.6 mm or more, and 0.15 mm or less if the size of the substrate in the long side direction is 0.6 mm or more but less than 1.6 mm. When viewed from above, the second gap between the second resistor and the second end face in the long side direction of the substrate is 0.3 mm or less when the size of the substrate in the long side direction is 1.6 mm or more, and 0.15 mm or less when the size of the substrate in the long side direction is 0.6 mm or more and less than 1.6 mm.

2. The chip resistor as described in claim 1, characterized in that, When viewed from above, the first auxiliary electrode overlaps with the first resistor, and the second auxiliary electrode overlaps with the second resistor.

3. The chip resistor as described in claim 1 or 2, characterized in that, A first adjustment groove is formed in the first resistive element. The shortest distance between the first end face of the substrate in the long side direction and the first adjustment groove is: the sum of the first interval between the first resistor in the long side direction of the substrate and the first end face and one-third or less of the size of the first resistor in the long side direction of the substrate.

4. The chip resistor as described in claim 3, characterized in that, A second adjustment groove is formed in the second resistive element. The shortest distance between the second end face of the substrate in the long side direction and the second adjustment groove is: the second interval between the second resistor in the long side direction and the second end face of the substrate and one-third or less of the size of the second resistor in the long side direction of the substrate.

5. The chip resistor as described in claim 1 or 2, characterized in that, The first width of the first auxiliary electrode in the long side direction of the substrate is larger than the first electrode width of the first terminal electrode in the long side direction of the substrate. The second width of the second auxiliary electrode in the long side direction of the substrate is larger than the second electrode width of the second terminal electrode in the long side direction of the substrate.

6. The chip resistor as described in claim 1 or 2, characterized in that, The first width of the first auxiliary electrode in the long side direction of the substrate is greater than or equal to the first interval between the first resistive element and the first end face in the long side direction of the substrate. The second width of the second auxiliary electrode in the long side direction of the substrate is greater than or equal to the second interval between the second resistive element and the second end face in the long side direction of the substrate.

7. The chip resistor as described in claim 1 or 2, characterized in that, The first overlap width between the first auxiliary electrode and the first resistor in the long side direction of the substrate is greater than or equal to the first interval between the first resistor and the first end face in the long side direction of the substrate. The second overlap width between the second auxiliary electrode and the second resistor in the long side direction of the substrate is greater than or equal to the second interval between the second resistor and the second end face in the long side direction of the substrate.

8. The chip resistor as described in claim 1 or 2, characterized in that, It also has an insulating protective film that covers the first resistor and the second resistor. The insulating protective film is located between the first auxiliary electrode and the first resistor, and between the second auxiliary electrode and the second resistor.

9. The chip resistor as described in claim 8, characterized in that, When viewed from above the substrate, the first auxiliary electrode and the first terminal electrode overlap with the insulating protective film, and the second auxiliary electrode and the second terminal electrode also overlap with the insulating protective film. The third overlap width between the first auxiliary electrode and the insulating protective film along the long side direction of the substrate is greater than the fourth overlap width between the first terminal electrode and the insulating protective film along the long side direction of the substrate. The fifth overlap width between the second auxiliary electrode and the insulating protective film in the long side direction of the substrate is greater than the sixth overlap width between the second terminal electrode and the insulating protective film in the long side direction of the substrate.

10. The chip resistor as claimed in claim 1, characterized in that, The first interval and the second interval are respectively smaller than the third interval between the first resistor and the second resistor in the long side direction of the substrate.

11. A chip resistor, characterized in that, have: A substrate comprising a main surface, a first end surface connected to the main surface, and a second end surface connected to the main surface; A first electrode is disposed on the first end face side of the substrate; The second electrode is disposed on the second end face side of the substrate; A first resistive element is disposed on the main surface; A second resistor is disposed on the main surface and spaced apart from the first resistor along the long side of the substrate, which is spaced apart from the first end face and the second end face; and A connecting electrode is disposed on the main surface, and the first resistive element and the second resistive element are electrically connected in series. The first electrode includes a first terminal electrode. The first terminal electrode is disposed on the main surface and connected to the first resistor. The second electrode includes a second terminal electrode. The second terminal electrode is disposed on the main surface and connected to the second resistor. When viewed from above, the first gap between the first resistor and the first end face in the long side direction of the substrate is 0.3 mm or less if the size of the substrate in the long side direction is 1.6 mm or more, and 0.15 mm or less if the size of the substrate in the long side direction is 0.6 mm or more but less than 1.6 mm. When viewed from above, the second gap between the second resistor and the second end face in the long side direction of the substrate is 0.3 mm or less when the size of the substrate in the long side direction of the substrate is 1.6 mm or more, and 0.15 mm or less when the size of the substrate in the long side direction of the substrate is 0.6 mm or more and less than 1.6 mm.

12. The chip resistor as described in claim 11, characterized in that, The first interval and the second interval are respectively smaller than the third interval between the first resistor and the second resistor in the long side direction of the substrate.

13. The chip resistor as described in claim 11 or 12, characterized in that, A first adjustment groove is formed in the first resistive element. The shortest distance between the first end face of the substrate in the long side direction and the first adjustment groove is: the sum of the first interval and one-third or less of the size of the first resistor in the long side direction of the substrate.

14. The chip resistor as described in claim 13, characterized in that, A second adjustment groove is formed in the second resistive element. The shortest distance between the second end face of the substrate in the long side direction and the second adjustment groove is: the second interval and one-third or less of the size of the second resistor in the long side direction of the substrate.

15. The chip resistor as claimed in claim 1 or 11, characterized in that, A first adjustment groove is formed in the first resistive element. The first groove portion of the first adjustment groove that is closest to the first end face is closer to the first end face than the first center line of the first resistor in the long side direction of the substrate.

16. The chip resistor as described in claim 15, characterized in that, A second adjustment groove is formed in the second resistive element. The second groove portion in the second adjustment groove that is closest to the second end face is closer to the second end face than the second center line of the second resistor in the long side direction of the substrate.

Images