Reconfigurable network security processor dedicated dma and design method

Abstract

The application belongs to the technical field of network security, and particularly relates to a special DMA for a reconfigurable network security processor and a design method. The special DMA comprises a DMA strategy controller and a plurality of chain DMA transmission controllers. The DMA strategy controller controls each chain DMA transmission controller to automatically execute an entire task according to a transmission strategy configured by a CPU once. The design method comprises the following steps: the DMA strategy controller starts one or more chain DMA transmission controllers to start transmission according to a strategy; when a chain DMA transmission controller being in transmission completes transmission, the DMA strategy controller is informed through a signal; and the DMA strategy controller judges whether to automatically execute data transmission of a next task according to CTC values of all chain DMA transmission controllers of a priority, all chain DMA transmission controllers of a previous priority and all chain DMA transmission controllers of a next priority, and an ANT register value of all chain DMA transmission controllers of the priority. The application improves network security service capability of the reconfigurable network security processor.

Description

Technical Field

[0001] This invention belongs to the field of network security technology, specifically relating to a reconfigurable network security processor dedicated DMA and its design method. Background Technology

[0002] Currently, common DMA methods mainly include block transfer DMA and ordinary chained DMA. When implementing network security protocols, the CPU needs to call DMA according to each operation in the protocol to send data to different modules for processing, completing the reassembly of network data packets step by step. This approach requires the CPU to participate in the processing of each operation in the network security protocol. During this process, the CPU needs to handle a large number of interrupt requests and wait for cache refreshes. The time spent handling these interrupt requests and refreshing the cache increases the interval between operations, preventing the full utilization of the performance of each functional module. It also reduces the time the CPU spends processing network security protocol headers, lowering data processing efficiency and ultimately hindering the full utilization of the network security service capabilities of the reconfigurable network security processor. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a dedicated DMA for a reconfigurable network security processor and its design method. The CPU configures all DMA descriptors for the entire task at once, and the dedicated DMA automatically executes the operations of each task according to the descriptors. This greatly reduces the number of times and the time the CPU needs to participate in the task processing, while fully leveraging the high efficiency and low latency characteristics of the dedicated DMA in dedicated hardware, reducing the gap between operations, and improving the network security service capabilities of the reconfigurable network security processor.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: This invention provides a dedicated DMA for a reconfigurable network security processor, including a DMA policy controller and multiple chained DMA transfer controllers. The DMA policy controller controls each chained DMA transfer controller to automatically execute all operations of the entire task according to the transfer policy configured by the CPU once, without the CPU participating in the task execution.

[0005] Furthermore, the DMA policy controller includes a policy register group, which provides multiple types of registers for each chained DMA transfer controller.

[0006] Furthermore, the policy register group includes the DSN register, TP register, CTC register, and ANT register; wherein, The DSN register: when DSN is 0, it means that the corresponding chained DMA transfer controller is not controlled by the policy and executes the transfer task according to the DMA descriptor chain; when DSN is non-zero, chained DMA transfer controllers with the same DSN are programmed into a data stream, and the data streams are independent of each other. TP Register: In the same data stream, the priority of each chain DMA transfer controller is determined by the value in the TP register. The chain DMA transfer controller with higher priority executes the transfer task before the chain DMA transfer controller with lower priority. Chain DMA transfer controllers with the same priority start to execute the transfer task at the same time. The chain DMA transfer controller of the next priority is started after all chain DMA transfer controllers of that priority have completed their execution. CTC register: All values ​​are cleared during initialization. When a chain DMA transfer controller completes a task transfer, the value of the CTC register corresponding to that chain DMA transfer controller is incremented by 1. After all the lowest priority chain DMA transfer controllers in the data stream complete their task transfers, the value of the CTC register of all chain DMA transfer controllers in the data stream is decremented by 1. ANT Register: Whether to start the next task's data transfer in a pipelined manner after the chained DMA transfer controller has completed the transfer is determined by the ANT register. If the ANT register is set, the CTC value condition check is started after the current task's transfer is completed. If the condition is met, the next task's data transfer is automatically started. If the ANT register is cleared, the current task enters an idle state after the transfer is completed, waiting for the DMA policy controller to start the next task's data transfer. Pipeline transfer is based on priority. If the ANT register of a chained DMA transfer controller in a priority is not set, then all chained DMA transfer controllers in that priority will not operate in pipelined mode.

[0007] Furthermore, the DMA policy controller also includes a policy execution module and a DMA transfer controller configuration module. The policy execution module controls each chained DMA transfer controller to execute transfer tasks according to the policy in the policy register group. The DMA transfer controller configuration module is a relay channel for the CPU to directly operate the chained DMA transfer controller.

[0008] This invention also provides a design method for a dedicated DMA for a reconfigurable network security processor, comprising the following: The CPU completes the transmission strategy configuration for all tasks at once according to the network security protocol; The DMA policy controller reads the transfer policy configuration of all tasks and starts one or more chained DMA transfer controllers to begin the transfer according to the policy. When a chained DMA transfer controller that is currently transferring completes the transfer, it notifies the DMA policy controller via a signal. The DMA policy controller then determines whether to automatically execute the data transfer of the next task based on the CTC values ​​of all chained DMA transfer controllers of this priority, all chained DMA transfer controllers of the previous priority, and all chained DMA transfer controllers of the next priority, as well as the ANT register values ​​of all chained DMA transfer controllers of this priority.

[0009] Furthermore, the conditions that must be met for automatically executing the data transfer of the next task are: first, the CTC values ​​of all chained DMA transfer controllers of this priority are equal; second, the CTC values ​​of all chained DMA transfer controllers of this priority are less than the minimum CTC value of all chained DMA transfer controllers of the previous priority, and are 1 greater than the minimum CTC value of all chained DMA transfer controllers of the next priority; and finally, the ANT bit of all chained DMA transfer controllers of this priority is set.

[0010] Furthermore, the data transfer process of the chained DMA transfer controller includes: The chained DMA transfer controller is in an idle state after power-on, and the DMA strategy controller sends a signal to start DMA transfer. The chained DMA transfer controller reads the descriptor from memory based on the address in the descriptor address register. If the correct descriptor is found, data transfer is initiated.

[0011] Furthermore, the data transfer process of the chained DMA transfer controller also includes: After the data transfer is complete, update the contents of the descriptor in memory and the value of the descriptor address register, and send a data transfer completion signal to the DMA policy controller. Then, start the next transfer process or enter an idle state, waiting for the DMA policy controller to send the start DMA transfer signal again.

[0012] Furthermore, if the current chained DMA transfer controller is the lowest priority and all other lowest priority chained DMA transfer controllers have completed their transfers, then a complete task flow is executed. The CTC values ​​of all chained DMA transfer controllers in this task flow are decremented by 1, and then the DMA policy controller restarts the chained DMA transfer controller transfer according to the policy.

[0013] Compared with the prior art, the present invention has the following advantages: 1. The reconfigurable network security processor dedicated DMA of the present invention uses a DMA policy controller to replace the CPU to complete the processing of each operation in the network security protocol, reducing the number of times and the time of CPU participation in the task processing, making the CPU process a single task, the data is continuous, and there is no need to frequently refresh the cache, thereby improving the efficiency of network data packet header processing.

[0014] 2. The DMA policy controller in the reconfigurable network security processor dedicated DMA of the present invention can start the next chained DMA transfer controller in a few clock cycles. The time interval between network security protocol processing steps can be shortened from tens of thousands of clock cycles during CPU processing to a few clock cycles, making the connection between the various steps of the network security protocol tighter and improving network security transmission capabilities.

[0015] In summary, by reducing CPU processing tasks and improving processing efficiency, as well as by more closely linking the various steps of network security protocols, the network security communication processing and service capabilities of reconfigurable network security processors can be effectively enhanced. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is an architecture diagram of the dedicated DMA for the reconfigurable network security processor according to an embodiment of the present invention; Figure 2 This is a flowchart illustrating the design method of a dedicated DMA for a reconfigurable network security processor according to an embodiment of the present invention. Figure 3 This is a schematic flowchart of the data transmission process of the chained DMA transfer controller according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] Example 1 like Figure 1 As shown, the reconfigurable network security processor dedicated DMA in this embodiment includes a DMA policy controller and multiple chained DMA transfer controllers. The DMA policy controller is the control core of the entire DMA. According to the transfer policy configured by the CPU at one time, it controls each chained DMA transfer controller to automatically execute all operations of the entire task. The CPU does not participate in the task execution process.

[0020] The DMA policy controller includes a policy register group, a policy execution module, and a DMA transfer controller configuration module. The policy register group provides four registers for each chained DMA transfer controller: "Data Stream Number (DSN)," "Transfer Priority (TP)," "AutomateNext Task (ANT)," and "Completion Task Count (CTC)."

[0021] DSN register: When DSN is 0, it means that the corresponding chained DMA transfer controller is not controlled by the policy and performs the transfer task according to the DMA descriptor chain; when DSN is non-zero, chained DMA transfer controllers with the same DSN are programmed into a data stream, and the data streams are independent of each other.

[0022] TP Register: Within the same data stream, the priority of each chained DMA transfer controller is determined by the value in the TP register. Higher-priority chained DMA transfer controllers execute their transfer tasks first, and only after these are completed can the next-highest priority chained DMA transfer controllers begin their tasks. Chained DMA transfer controllers of the same priority can start executing transfer tasks simultaneously, but they must wait for all chained DMA transfer controllers of that priority to complete their tasks before starting the next priority chained DMA transfer controller.

[0023] CTC register: All values ​​are cleared to zero during initialization. When a chain DMA transfer controller completes a task transfer, the value of the CTC register corresponding to that chain DMA transfer controller is incremented by 1. After all the lowest priority chain DMA transfer controllers in the data stream complete their task transfers, the value of the CTC register of all chain DMA transfer controllers in the data stream is decremented by 1.

[0024] ANT register: Each network processing task can be divided into multiple steps, each with a priority level. Data transfer in a single step is completed by one or more chained DMA transfer controllers. Different steps of different tasks form a data pipeline, which can significantly improve data processing efficiency. However, for certain special protocols or scenarios, pipelined operation is not permitted. The ANT register is used to control whether the chained DMA transfer controller operates in a pipelined manner.

[0025] Pipeline transfer is based on priority. If the ANT register of a chained DMA transfer controller in a priority is not set, then all chained DMA transfer controllers in that priority will not operate in pipelined mode.

[0026] After the chained DMA transfer controller completes the transfer, whether to start the next task's data transfer in a pipelined manner is determined by the ANT register. If the ANT register is set, the CTC value condition check is started after the current task's transfer is completed. If the condition is met, the next task's data transfer is automatically started. If the ANT register is cleared, the current task's transfer is completed and the system enters an idle state, waiting for the DMA policy controller to start the next task's data transfer.

[0027] The policy execution module controls each chained DMA transfer controller to execute transfer tasks according to the policies in the policy register group. The DMA transfer controller configuration module is the intermediary channel for the CPU to directly operate the chained DMA transfer controllers.

[0028] Based on the above-mentioned reconfigurable network security processor dedicated DMA, such as Figure 2 As shown, this embodiment also proposes a design method for a dedicated DMA for a reconfigurable network security processor, which includes the following: After power-on, the CPU initializes the dedicated DMA for the reconfigurable network security processor and configures the policy register groups of each chained DMA transfer controller. After the descriptors of each chained DMA transfer controller are configured, the data flow is started.

[0029] The DMA policy controller initiates one or more chained DMA transfer controllers to begin transfer according to the policy.

[0030] When a chained DMA transfer controller completes a transfer, it notifies the DMA policy controller via a signal. The DMA policy controller then determines whether to automatically execute the next task's data transfer based on the CTC values ​​of all chained DMA transfer controllers of this priority, the chained DMA transfer controllers of the previous priority, and the chained DMA transfer controllers of the next priority, as well as the ANT values ​​of all chained DMA transfer controllers of this priority. First, the CTC values ​​of all chained DMA transfer controllers of this priority must be equal. Second, the CTC values ​​of all chained DMA transfer controllers of this priority must be less than the minimum CTC value of all chained DMA transfer controllers of the previous priority, and greater than the minimum CTC value of all chained DMA transfer controllers of the next priority by one. Finally, the ANT values ​​of all chained DMA transfer controllers of this priority must be set. Only then can the next task's data transfer be automatically executed; otherwise, it must wait for the DMA policy controller's start signal before data transfer can begin.

[0031] If the current chained DMA transfer controller is the lowest priority and all other lowest priority chained DMA transfer controllers have completed their transfers, then a complete task flow is executed. The CTC value of all chained DMA transfer controllers in this task flow is decremented by 1, and then the DMA policy controller restarts the chained DMA transfer controller transfer according to the policy.

[0032] like Figure 3 As shown, the data transmission process of the chained DMA transfer controller is as follows: The chained DMA transfer controller is in an idle state after power-on, and the DMA policy controller sends a signal to start DMA transfer.

[0033] The chained DMA transfer controller reads the descriptor from memory based on the address in the descriptor address register. If the correct descriptor can be read, data transfer is started; otherwise, it enters an idle state and reports an error status to the DMA policy controller.

[0034] After the data transfer is complete, update the contents of the descriptor in memory and the value of the descriptor address register, and send a data transfer completion signal to the DMA policy controller. Then, start the next transfer process or enter an idle state, waiting for the DMA policy controller to send the start DMA transfer signal again.

[0035] Example 2 This embodiment uses an "encrypt-reassemble-send" model for verification. Each task includes three steps: data encryption, data packet reassembly, and data packet transmission. The encryption step includes two DMA operations: sending plaintext into the cryptographic engine and sending the key into the cryptographic engine. The reassembly step includes two DMA operations: transmitting the packet header and transmitting the ciphertext. The transmission step includes sending the reassembled data to the network interface.

[0036] This model uses five chained DMA transfer controllers, all with their DSN registers configured to 1, forming a single data stream. (If hardware resources are sufficient, five more chained DMA transfer controllers can be configured with their DSN registers set to 2, forming two independent data streams that can be executed in parallel.) The encryption process uses chained DMA transfer controllers 0 and 1 to transfer data, with the TP register set to 3 (highest priority) and the ANT register set to 1 (supporting pipelined mode). The reassembly process uses chained DMA transfer controllers 2 and 3 to transfer data, with the TP register set to 2 (secondary priority) and the ANT register set to 1 (supporting pipelined mode). The transmission process uses chained DMA transfer controller 4 to transfer data, with the TP register set to 1 (lowest priority) and the ANT register set to 1 (supporting pipelined mode).

[0037] Before a task begins, the CPU must complete the above-mentioned policy control and configure all descriptors for at least one task. During the execution of a task, the CPU continuously and rapidly adds DMA descriptors for new tasks, enabling the dedicated DMA to work continuously in a pipelined manner.

[0038] During transmission, due to the different data lengths and data generation rates, the time required for chain DMA transmission controller 0 (transmitting the key) and chain DMA transmission controller 2 (transmitting the packet header) is set to T, and the time required for chain DMA transmission controller 1 (transmitting plaintext), chain DMA transmission controller 3 (transmitting ciphertext), and chain DMA transmission controller 4 (transmitting the reassembled data packet) is set to 2T.

[0039] For ease of description, the CTC register name of each chained DMA transfer controller is labeled as CTC plus the controller number. For example, the CTC register of chained DMA transfer controller 2 is labeled as CTC2.

[0040] The working process of the dedicated DMA of the reconfigurable network security processor is as follows: (1) Start time: The CTC value of all chain DMA transfer controllers is 0 and they are in an idle state. The DMA policy controller starts the chain DMA transfer controller 0 and chain DMA transfer controller 1 to start the transfer according to the descriptor of the first task.

[0041] (2) At time T: Chain DMA transfer controller 0 completes the transfer. At this time, CTC0 is 1 and CTC1 is 0. Since CTC0 and CTC1 are different, chain DMA transfer controller 0 does not meet the start conditions and enters the idle state.

[0042] (3) At time 2T: Chain DMA transfer controller 1 completes the transfer, and CTC1 is 1. Since the highest priority CTC0 and CTC1 are equal and are 1 greater than the next highest priority CTC2 and CTC3, chain DMA transfer controller 0 and chain DMA transfer controller 1 start the encryption process of the second task. At the same time, chain DMA transfer controller 2 and chain DMA transfer controller 3 start the reassembly process of the first task.

[0043] (4) At time 3T: the chain DMA transfer controller 0 and chain DMA transfer controller 2 have completed the transfer. At this time, CTC0 is 2, CTC1 is 1, CTC2 is 1, and CTC3 is 0. The chain DMA transfer controller 0 and chain DMA transfer controller 2 do not meet the start conditions and enter the idle state.

[0044] (5) At time 4T: The transmission of the chain DMA transfer controller 1 and the chain DMA transfer controller 3 is completed. CTC0 is 2, CTC1 is 2, CTC2 is 1, and CTC3 is 1. At this time, CTC0 and CTC1 are 1 greater than the next higher priority CTC2 and CTC3. The chain DMA transfer controller 0 and the chain DMA transfer controller 1 meet the start conditions again and start the encryption process of the third task. At the same time, CTC2 and CTC3 are equal and both less than CTC0 and CTC1, and are 1 greater than CTC4. The chain DMA transfer controller 2 and the chain DMA transfer controller 3 meet the start conditions and start the reassembly process of the second task. The chain DMA transfer controller 4 starts the transmission process of the first task.

[0045] (6) At time 5T: the chain DMA transfer controller 0 and chain DMA transfer controller 2 have completed the transfer. At this time, CTC0 is 3, CTC1 is 2, CTC2 is 2, and CTC3 is 1. Neither chain DMA transfer controller 0 nor chain DMA transfer controller 2 meets the start conditions and enters the idle state.

[0046] (7) At time 6T: The transmission of the chained DMA transfer controllers 1, 3, and 4 is completed. The value of CTC0 is 3, the value of CTC1 is 3, the value of CTC2 is 2, the value of CTC3 is 2, and the value of CTC4 is 1. Since all the steps of the first task are completed, all CTC values ​​are reduced by 1. Therefore, the value of CTC0 is 2, the value of CTC1 is 2, the value of CTC2 is 1, the value of CTC3 is 1, and the value of CTC4 is 0. At this time, CTC0 and CTC1 are equal and are 1 greater than the next-priority CTC2 and CTC3. Therefore, the chained DMA transfer controllers 0 and 1 meet the start conditions again and start the encryption step of the fourth task. At the same time, CTC2 and CTC3 are equal and are less than the higher-priority CTC0 and CTC1, and are 1 greater than the lower-priority CTC4. The chained DMA transfer controllers 2 and 3 meet the start conditions and start the reassembly step of the third task. Meanwhile, since CTC4 is lower than the previous priority CTC2 and CTC3, the chained DMA transfer controller 4 meets the startup conditions and starts the transmission process of the second task.

[0047] Repeat the above steps to complete the "encryption-reassembly-send" model task queue in a pipeline manner. By verifying that the dedicated DMA of the reconfigurable network security processor can achieve efficient and continuous data transfer and zero CPU involvement in the data transfer process, the processing capability of the network security processor is improved.

[0048] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0049] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is only used to illustrate the technical solution of the present invention, and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

[0050] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present invention can be implemented using various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0051] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0052] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0053] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0054] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0055] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A dedicated DMA for a reconfigurable network security processor, characterized in that, It includes a DMA policy controller and multiple chained DMA transfer controllers. The DMA policy controller controls each chained DMA transfer controller to automatically execute all operations of the entire task according to the transfer policy configured by the CPU at one time. The CPU does not participate in the task execution process. The DMA policy controller includes a policy register group, which provides multiple types of registers for each chained DMA transfer controller; the policy register group includes a DSN register, a TP register, a CTC register, and an ANT register; wherein... The DSN register: when DSN is 0, it means that the corresponding chained DMA transfer controller is not controlled by the policy and executes the transfer task according to the DMA descriptor chain; when DSN is non-zero, chained DMA transfer controllers with the same DSN are programmed into a data stream, and the data streams are independent of each other. TP Register: In the same data stream, the priority of each chain DMA transfer controller is determined by the value in the TP register. The chain DMA transfer controller with higher priority executes the transfer task before the chain DMA transfer controller with lower priority. Chain DMA transfer controllers with the same priority start to execute the transfer task at the same time. The chain DMA transfer controller with the next priority is started after all chain DMA transfer controllers with the same priority have completed their execution. CTC register: All values ​​are cleared during initialization. When a chain DMA transfer controller completes a task transfer, the value of the CTC register corresponding to that chain DMA transfer controller is incremented by 1. After all the lowest priority chain DMA transfer controllers in the data stream complete their task transfers, the value of the CTC register of all chain DMA transfer controllers in the data stream is decremented by 1. ANT Register: Whether to start the next task's data transfer in a pipelined manner after the chained DMA transfer controller has completed the transfer is determined by the ANT register. If the ANT register is set, the CTC value condition check is started after the current task's transfer is completed. If the condition is met, the next task's data transfer is automatically started. If the ANT register is cleared, the current task enters an idle state after the transfer is completed, waiting for the DMA policy controller to start the next task's data transfer. Pipeline transfer is based on priority. If the ANT register of a chained DMA transfer controller in a priority is not set, then all chained DMA transfer controllers in that priority will not operate in pipelined mode. The DMA policy controller further includes a policy execution module and a DMA transfer controller configuration module. The policy execution module controls each chained DMA transfer controller to execute transfer tasks according to the policy in the policy register group. The DMA transfer controller configuration module is a relay channel for the CPU to directly operate the chained DMA transfer controller.

2. The design method for a dedicated DMA for a reconfigurable network security processor according to claim 1, characterized in that, Includes the following: The CPU completes the transmission strategy configuration for all tasks at once according to the network security protocol; The DMA policy controller reads the transfer policy configuration of all tasks and starts one or more chained DMA transfer controllers to begin the transfer according to the policy. When a chained DMA transfer controller completes its transfer, it notifies the DMA policy controller via a signal. The DMA policy controller then determines whether to automatically execute the next task's data transfer based on the CTC values ​​of all chained DMA transfer controllers of this priority, all chained DMA transfer controllers of the previous priority, and all chained DMA transfer controllers of the next priority, as well as the value of the ANT register of all chained DMA transfer controllers of this priority. The conditions for automatically executing the next task's data transfer are as follows: First, the CTC values ​​of all chained DMA transfer controllers of this priority are equal; second, the CTC values ​​of all chained DMA transfer controllers of this priority are less than the minimum CTC value of all chained DMA transfer controllers of the previous priority, and are 1 greater than the minimum CTC value of all chained DMA transfer controllers of the next priority; finally, the ANT register of all chained DMA transfer controllers of this priority is set. If the current chained DMA transfer controller is the lowest priority and all other lowest priority chained DMA transfer controllers have completed their transfers, then a complete task flow is executed. The CTC values ​​of all chained DMA transfer controllers in this task flow are decremented by 1, and then the DMA policy controller restarts the chained DMA transfer controller transfer according to the policy. The data transfer process of the chained DMA transfer controller includes: The chained DMA transfer controller is in an idle state after power-on, and the DMA strategy controller sends a signal to start DMA transfer. The chained DMA transfer controller reads the descriptor from memory based on the address in the descriptor address register. If the correct descriptor can be read, the data transfer is initiated. After the data transfer is complete, update the contents of the descriptor in memory and the value of the descriptor address register, and send a data transfer completion signal to the DMA policy controller. Then, start the next transfer process or enter an idle state, waiting for the DMA policy controller to send the start DMA transfer signal again.

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