A high-precision hardware backdoor detection method for an incomplete gate-level netlist

Abstract

The application discloses a high-precision hardware backdoor detection method for an incomplete gate-level netlist, and relates to the field of hardware security. The application aims at high-precision hardware backdoor detection under the premise that IC reverse engineering is difficult to obtain a 100% accurate logic netlist under limited resource conditions. Based on the fact that the measurable characteristic value of a hardware backdoor node is much larger than that of a normal node, and combined with a layout position file obtained through reverse engineering, the original characteristic value is continuously approached through IO, global average and range search, so that subsequent clustering judgment can be effectively implemented. High-precision hardware backdoor detection is realized under the condition that the netlist is incomplete.

Description

Technical Field

[0001] This invention relates to the field of hardware security. In response to the incomplete gate-level netlists obtained by current chip reverse engineering techniques, a high-precision hardware backdoor detection method is proposed, which enhances the versatility of silicon-based chip hardware backdoor detection technology and provides a new approach for silicon-based hardware backdoor detection. Background Technology

[0002] Over the past two decades, hardware security and trust have become pressing issues due to the globalization of the semiconductor supply chain and the ubiquitous network connectivity of computing devices. Hardware backdoors, due to their stealthy nature, are difficult to detect during traditional chip verification and testing. Furthermore, the arbitrary selection of the payload of a hardware backdoor grants attackers immense freedom, making the damage caused by hardware backdoors incalculable.

[0003] Currently, hardware backdoor detection technology can be divided into pre-silicon (PS) detection and post-silicon (PS) detection based on the execution stage. PS primarily targets hardware design documents before tape-out, such as HDL files, netlist files, and GDSII files. PS methods are relatively abundant, including functional verification, structural analysis, code and circuit coverage analysis, and formal verification. PS primarily targets finished integrated circuit chips (ICs) after tape-out and can be further divided into non-destructive and destructive methods. Non-destructive methods include functional testing and side-channel analysis. Destructive methods are the highest level of protection against hardware backdoors. Through reverse engineering (RE), the IC is compared to a prototype or model for visual verification, eliminating the possibility of backdoors at the lowest physical level.

[0004] In 2007, Dakshi Agrawal et al. first proposed the concept of "hardware backdoors" at the IEEE Symposium on Security and Privacy, and also proposed a method to detect hardware backdoors by setting "power consumption fingerprints" on the chip's side channels. In 2010, Hicks et al. from the University of Illinois proposed an Unused Circuit Identification (UCI) detection method. This method detects malicious backdoors hidden in circuits during chip design; essentially, it finds unused circuit parts during testing and marks them as potentially malicious logic. In 2013, Waksman et al. from Columbia University proposed a detection method based on extracting signal node control value features (FANCI) from circuit truth tables to mark Trojan signal nodes. In 2016, Hassan Salmani et al. from Harvard University introduced the Sandia Controllability / Observability Analysis Program (SCOAP) into hardware backdoor detection and combined it with machine learning algorithms to propose a referenceless hardware backdoor detection and recovery technique (COTD) based on gate-level netlist controllability and observability. In 2018, Vashistha et al. proposed the Trojan Scanner, which uses a reliable GDSII (Golden Layout) and scanning electron microscopy (SEM) images to identify malicious modifications made to the netlist during circuit manufacturing. In 2020, Stern et al. used a non-destructive back-end laser probing method to detect Trojans. By comparing two different sets of photoelectric frequency mapping (EOFM) images, Trojan timing devices can be identified, thus locating the hardware Trojan timing devices (FFs).

[0005] IC reverse engineering aims to extract high-level abstract representations, such as gate-level or functional-level netlists, from physical ICs or mask data to understand or verify IC functional models. Its process flow includes chip depackaging, chemical or plasma etching, wheel polishing, electron microscopy imaging and storage, image stitching, image recognition and processing, and automated software netlist extraction. With the rapid advancement of integrated circuit process nodes, IC reverse engineering is facing significant challenges. Lippmann et al. proposed that, given sufficient time and resources, reverse engineering can recover the building blocks of any given IC with up to 99% accuracy. However, from the perspective of commercial entities involved in hardware development and design, the goal is not to completely prevent reverse engineering, but rather to postpone this process long enough to introduce entirely new designs and technologies. Therefore, expecting reverse engineering to achieve 100% accuracy and enable backdoor detection within a reasonable timeframe is unrealistic.

[0006] In summary, known methods for detecting hardware backdoors in ICs have not considered the problem of incomplete gate-level netlists from the perspective of reverse engineering. However, this method achieves high-precision backdoor detection for incomplete gate-level netlists, filling the application gap for silicon-based hardware backdoor detection based on reverse engineering. Summary of the Invention

[0007] This invention proposes a high-precision hardware backdoor detection method for incomplete gate-level netlists. This method addresses the issue of incomplete input gate-level netlists in reverse engineering-based backdoor detection techniques. Without requiring a gold circuit sample, this method can accurately detect whether the netlist under test contains hardware backdoors and identify suspicious trojan nodes. It solves the problem that existing hardware backdoor detection methods cannot detect incomplete gate-level netlists and fills a gap in the application of reverse engineering-based backdoor detection techniques.

[0008] This invention aims to deduce possible logical connections between breakpoints in the IC reverse engineering of incomplete gate-level netlists (due to missing devices or connections), by combining the physical proximity of breakpoints in the IC reverse layout file. This allows for high-precision detection of hardware backdoors in the IC. The process involves: first, preprocessing and modeling the gate-level netlist; second, identifying and locating breakpoint signals; then, iteratively calculating testability feature values ​​for the breakpoint signals to approximate the breakpoint feature values ​​of the original complete netlist; and finally, using an unsupervised clustering algorithm to compare inter-class distances to determine backdoors. In this invention, the breakpoint feature values ​​iterate continuously to approximate the original values, therefore, it is necessary to calculate the testability feature values ​​starting from different initial conditions. The complete process of this invention is as follows: Figure 1 As shown. Therefore, the technical solution of this invention is: a high-precision hardware backdoor detection method for incomplete gate-level netlists, the method comprising:

[0009] Step 1: Preprocessing and modeling of incomplete gate-level netlists;

[0010] First, read the incomplete gate-level netlist file, extract the I / O and internal signal nodes to form a directed graph vertex set V = {v1, v2, v3, ..., v...} M Each vertex object in the set has a signal name, a driving logic unit name, and a driving logic unit type.

[0011] Secondly, the input and output signal nodes of the logic devices are mapped to the edges of a directed graph, forming an edge set E = {e1, e2, e3, ..., e}. i ,…e k}; where one side e i = <n i ,n j > indicates vertex n i Let n be an input node of a device, and in the directed graph point to the output node n of the same device. jEach edge includes: the name of the head node, the name of the tail node, the name of the input signal pin, and the name of the logic device to which it belongs.

[0012] Each gate-level logical netlist is mapped to a directed graph G = (V, E), which consists of a vertex set V and an edge set E.

[0013] Step 2: Identification and location of breakpoint signals;

[0014] Import the GDSII file into the EDA (Electronic Design Automation) tool, and use the EDA tool to perform a Design Rule Check (DRC) on the layout to filter out missing nodes = {n1, n2, ..., n}. m}; Secondly, obtain the disconnection n i pins(n) connected to the device i )={p1,p2,…,p n}, and n i Breakpoint type Type(n i Classification as shown in Equation 1:

[0015]

[0016] in, The set is empty, and outpins = {C1, SO, CO, S, Q, QN, ZN, Y}, where C1, SO, CO, S, Q, QN, ZN, Y are the output pin names of different devices in the component library; that is, if a disconnect signal is not connected to any device pin, it is recorded as an ISOLATE type disconnect signal, which represents an isolated type disconnect signal; otherwise, if the disconnect signal is not connected to any device output pin, it is recorded as an MI type disconnect signal, which represents an input missing type disconnect signal; if it is connected to any device output pin, it is recorded as an MO type disconnect signal, which represents an output missing type disconnect signal.

[0017] Finally, the non-ISOLATE type breakpoint signal n i The normalized coordinate position of any connected logic device relative to the lower left corner of the IC core (Location(n)) i )={x i ,y i},x i ∈[0,1],y i Enter the location attribute of the breakpoint signal in [0,1], and enter the breakpoint type in the breakpoint type attribute;

[0018] Step 3: Iteratively calculate the testability feature values;

[0019] Testability includes three metrics: cc0(v), cc1(v), and co(v), which are the controllability of the combination 0 of signal v, the controllability of the combination 1, and the observability of the combination.

[0020] Step 3.1: Initialize I / O using breakpoints;

[0021] Define the chip input port set as I and the output port set as O; then perform the initialization operations from Equations 2 to 5 on each node;

[0022] cc0(v)=cc1(v)=1, co(v)=∞, v∈I∪MI (2)

[0023] cc0(v)=cc1(v)=∞, co(v)=0, v∈O∪MO (3)

[0024] cc0(v)=cc1(v)=1,co(v)=0,v∈ISOLATE (4)

[0025] cc0(v)=cc1(v)=∞,co(v)=∞,For others (5)

[0026] Step 3.2: Calculate the testability feature values;

[0027] First, the topological order of the signal nodes is determined so that the calculation of the signal node feature values ​​can be completed in an orderly manner under linear time complexity. Then, the controllability features of the signal nodes are calculated according to the forward topological order, i.e., the order from input to output. Finally, the observability features of the signal nodes are calculated according to the reverse topological order, i.e., the order from output to input.

[0028] The topological order of the signal nodes was determined using the Kosaraju algorithm.

[0029] The controllability index of the logic gate output signal is equal to the minimum sum of the controllability indices of the input signals that need to be controlled to set the signal to 1 or 0, plus 1.

[0030] The observability index of a logic gate input signal is equal to the observability index of the output signal plus the minimum sum of the controllability indices required to set other input signals to non-controllable values, plus 1.

[0031] Step 3.3: Assign global average values ​​to breakpoints;

[0032] The controllability index of MI-type breakpoint signals is initialized to the average controllability of MO-type breakpoint signals, while the observability index of MO-type breakpoint signals is initialized to the average observability index of MI-type breakpoint signals. In addition, in order to eliminate the influence of constant signals, the characteristic value range of the signals participating in the mean calculation needs to be checked; that is, the initialization operation of each signal is performed as shown in Equation 6-10.

[0033] cc0(v)=cc1(v)=1, co(v)=∞, v∈I (6)

[0034] cc0(v)=cc1(v)=∞, co(v)=0, v∈O (7)

[0035]

[0036]

[0037]

[0038] Where node represents a single breakpoint signal;

[0039] Then calculate the testability index again to provide more reliable feature values ​​for subsequent range search assignment;

[0040] Step 3.4: Set values ​​for the breakpoint range search;

[0041] First, a kd-tree is constructed starting from the non-isolated breakpoint signals; second, a range search is performed on each MO-class breakpoint signal, and the average CO feature value of the MI-class breakpoint signals obtained from the search is assigned to the MO-class breakpoint signal that started the search, as shown in Equation 11.

[0042]

[0043] Where SNI={node|node∈SN∩node∈MI∩co(node)<∞} is the set of MI class breakpoint signals obtained by the search and whose CO feature values ​​are valid, and SN is the set of nodes returned by the kd-tree range search;

[0044] Similarly, a range search is performed for each MI-type breakpoint signal, and the average of the CC1 and CC0 eigenvalues ​​of the MO-type breakpoint signals obtained from the search is assigned to the MI breakpoint signal that started the search, as shown in Equations 12 and 13.

[0045]

[0046]

[0047] Wherein, SNO0={node|node∈SN∩node∈MO∩cc0(node)<∞} is the set of MO class breakpoint signals obtained by searching and whose CC0 feature values ​​are valid; SNO1={node|node∈SN∩node∈MO∩cc1(node<∞} is the set of MO class breakpoint signals obtained by searching and whose CC1 feature values ​​are valid;

[0048] If no target class breakpoint signal is found, the average feature value of the target class breakpoint signal is assigned to the breakpoint signal that started the search.

[0049] Step 4: Clustering determination;

[0050] First, the CC0 and CC1 eigenvalues ​​of each signal node are merged into a single eigenvalue CC, as shown in Formula 14:

[0051]

[0052] Secondly, the signal nodes are divided into three categories using a clustering algorithm; then, the inter-class distance is used to determine whether each cluster is a Trojan signal node cluster; finally, the detection results are reported.

[0053] Furthermore, the clustering method in step 4 is as follows:

[0054] The clustering process is performed on the entire controllable and observable node set N = {n1, n2, ..., n}. M To proceed, first input the points n. i ∈N represents the set of eigenvectors D = {(CC(n)} i ),CO(n i )),n i ∈N}; Secondly, considering the distribution characteristics of Trojan nodes, the origin, the point with the largest observable value, and the point with the largest controllable value are selected as the initial cluster center set {μ1,μ2,μ3}, as shown in Equation 15:

[0055]

[0056] Finally, iterate through set D and calculate n. i Node corresponding feature vector D i Euclidean distance d from the center of each cluster ij As shown in Equation 16, clusters are divided according to the distance of each point to the nearest cluster center, as shown in Equations 17-18, where λ i For n i Node cluster marker, For n i The node is assigned to the node cluster; and the cluster center position is updated as shown in Equation 19:

[0057] d ij =||D i -u j || 2 D i ∈D,j∈{1,2,3} (16)

[0058] λ i =arg min j∈{1,2,3} d ij (17)

[0059]

[0060]

[0061] The process continues until it converges and stabilizes to the final node cluster partition {C1,C2,C3} and cluster center {μ1,μ2,μ3}.

[0062] Furthermore, the method for determining whether each cluster is a Trojan signal node cluster by inter-class distance in step 4 is as follows:

[0063] The classification and judgment are based on a difference threshold related to the standard deviation of ordinary node clusters. When the distance between clusters exceeds the threshold, it is judged as a Trojan cluster. First, based on the distance from the cluster center to the origin, each cluster is labeled as C1, C2, C3 from smallest to largest. Second, the standard deviation σ1 of cluster C1 is calculated, as shown in Equation 20:

[0064]

[0065] Where K is the number of nodes in cluster C1, and μ is the center vector of cluster C1; set the threshold T1 = 3σ1, and calculate the distance between classes C1 and C2 as I. 12 , if I 12 If T1 >, then C2 and C3 are both determined to be Trojan node clusters; if I 12 If the threshold is ≤T1, then C2 is determined to be a normal node cluster, and C1 and C2 are considered to be the same normal node cluster. The standard deviation σ2 of clusters C1 and C2 is calculated, and a new threshold T2 = 3σ2 is set to determine cluster C3. The inter-cluster distance between clusters C1, C2 and C3 is calculated as I. 12,3 , if I 12,3 If T2 is true, then C3 is determined to be a Trojan node cluster; otherwise, C3 is determined to be a normal node cluster.

[0066] Finally, uncontrollable or unobservable nodes, as well as clusters of Trojan nodes identified through clustering, are reported to the user as Trojan nodes.

[0067] This invention proposes a high-precision hardware backdoor detection method for incomplete gate-level netlists. This invention aims to achieve high-precision hardware backdoor detection, addressing the challenge of obtaining 100% accurate logic netlists under limited resources during IC reverse engineering. Based on the fact that the testability feature values ​​of hardware backdoor nodes are much larger than those of normal nodes, and combined with the layout location file obtained from reverse engineering, the original feature values ​​are continuously approximated through IO, global averaging, and range search methods, thus enabling effective subsequent clustering judgments. This achieves high-precision hardware backdoor detection even under incomplete netlist conditions. Attached Figure Description

[0068] Figure 1 Flowchart of a method for detecting hardware backdoors in incomplete gate-level netlists;

[0069] Figure 2 Mapping gate-level netlists to directed graphs;

[0070] Figure 3 Flowchart of iterative computation of testability feature values;

[0071] Figure 4 Flowchart for calculating testability feature values;

[0072] Figure 5 Schematic diagram for calculating the controllability index of basic logic devices;

[0073] Figure 6 Schematic diagram of the calculation of observability index for basic logic devices;

[0074] Figure 7 Breakpoint range search assignment algorithm flow;

[0075] Figure 8 MO-type breakpoint range search and assignment algorithm flow;

[0076] Figure 9 MI-type breakpoint range search and assignment algorithm flow. Detailed Implementation

[0077] This invention conducts experiments on three key samples (RS232-T1300, S15850-T100, and S35932-T100) in the Trust-Hub sample set. For each sample, components, wires, or a combination of both are randomly lost. The experiments are repeated 100 times at different loss scales (0.1%, 0.5%, 1%, and 5%) to calculate the detection accuracy, i.e., the average detection rate. Additionally, 100 experiments are performed on the corresponding malware-free samples (RS232-TiFree, s15850-TjFree, and s35932-TjFree) to calculate the detection error rate, i.e., the average false alarm rate. The mixed loss refers to the simultaneous loss of components and wires at a specified scale. The experimental results are shown in the table.

[0078] A high-precision hardware backdoor detection method for incomplete gate-level netlists, the method comprising:

[0079] Step 1: Preprocessing and modeling of incomplete gate-level netlists;

[0080] The purpose of the netlist preprocessing stage is to convert the abstract logical netlist into a directed graph data model that the program can use. First, the incomplete gate-level netlist file is read, and I / O and internal signal nodes are extracted to form a directed graph vertex set V = {v1, v2, v3, ..., v...}. M Each vertex object has attributes such as signal name, driving logic unit name, and driving logic unit type;

[0081] Secondly, the input and output signal nodes of the logic devices are mapped to the edges of a directed graph, forming an edge set E = {e1, e2, e3, ..., e}. k}; where one side e i = <n i ,n j > indicates vertex n i Let n be an input node of a device, and in the directed graph point to the output node n of the same device. j Each edge includes attributes such as the head node name, tail node name, input signal pin name, and the name of the logic device to which it belongs;

[0082] Therefore, each gate-level logical netlist can be mapped to a directed graph G = (V, E), where G consists of a vertex set V and an edge set E. The mapping relationship between gate-level netlists and directed graphs is as follows: Figure 2 As shown.

[0083] 2. Breakpoint signal identification and location

[0084] This step identifies breakpoint signals by performing rule checking (DRC) on the GDSII reverse layout file and marks their relative positions in the layout for subsequent breakpoint feature prediction algorithms. First, the GDSII file is imported into an EDA tool, and the EDA tool is used to perform DRC on the layout to filter out breakpoint signals: missnodes = {n1, n2, ..., n}. m Next, obtain the disconnection number n. i The pin names connected to the device are pins(n i )={p1,p2,…,p n}, and n i Breakpoint type Type(n i Classification as shown in Equation 1:

[0085]

[0086] Where outpins = {C1, SO, CO, S, Q, QN, ZN, Y} is the set of device output pin names. That is, if a disconnect signal is not connected to any device pin, it is recorded as an ISOLATE type (isolated) disconnect signal; otherwise, if the disconnect signal is not connected to any device output pin, it is recorded as an MI type (input missing) disconnect signal; if it is connected to any device output pin, it is recorded as an MO type (output missing) disconnect signal.

[0087] Finally, the non-ISOLATE type breakpoint signal n i The normalized coordinate position of any connected logic device relative to the lower left corner of the IC core (Location(n)) i )={x i ,y i},xi ∈[0,1],y i Enter the location attribute of the breakpoint signal in [0,1], and enter the breakpoint type in the breakpoint type attribute for subsequent range search.

[0088] 3. Iteratively calculate the testability feature values.

[0089] Testability is a relative metric for the workload or cost of testing logic circuits. Previous research has shown that the testability of signal nodes in Trojan trigger circuits is much higher than that of normal nodes to achieve the stealth requirement of triggering under specific conditions. This invention follows the framework of the SCOAP testability analysis algorithm, subdividing testability into controllability and observability using three metrics: CC0(s), CC1(s), and CO(s), representing the controllability of combination 0, the controllability of combination 1, and the observability of combination s. Generally speaking, these three combined testability metrics (CC0, CC1, and CO) relate to the number of signals that must be manipulated to control the input signal s or observe the output signal s, reflecting the difficulty of controlling or observing internal signals s from the chip's I / O. This step iteratively calculates testability feature values ​​to estimate the original testability feature values ​​in the event of missing information. The specific sub-processes are as follows... Figure 3 As shown, each sub-step has the same number as the one in the figure.

[0090] 3.1 Breakpoint for I / O initialization

[0091] This sub-step treats breakpoint signals as I / O ports to initiate testability feature calculations, laying the foundation for subsequent iterations. Define the chip's input port set as I and the output port set as O. Then, perform initialization operations from Equations 2 to 5 on each node.

[0092] cc0(v)=cc1(v)=1, co(v)=∞, v∈I∪MI (22)

[0093] cc0(v)=cc1(v)=∞, co(v)=0, v∈O∪MO (23)

[0094] cc0(v)=cc1(v)=1,co(v)=0,v∈ISOLATE (24)

[0095] cc0(v)=cc1(v)=∞,co(v)=∞,For others (25)

[0096] For I and MI type breakpoint signals, set the characteristic values ​​CC0 = CC1 = 1, CO = ∞; for O and MO type breakpoint signals, set the characteristic values ​​CC0 = CC1 = ∞, CO = 0; for ISOLATE type signals, set the characteristic values ​​CC0 = CC1 = 1, CO = 0; and for other signals, set the characteristic values ​​CC0 = CC1 = CO = ∞.

[0097] 3.2 Calculate the testability feature value

[0098] After each initialization sub-step is completed, the testability eigenvalues ​​can be calculated. The calculation process is as follows: Figure 4 As shown, firstly, the topological order of the signal nodes is statistically analyzed so that the calculation of the signal node feature values ​​can be completed in an orderly manner under linear time complexity; then, the controllability features of the signal nodes are calculated according to the forward topological order (from input to output); finally, the observability features of the signal nodes are calculated according to the reverse topological order (from output to input).

[0099] Because feedback loops exist in the logic circuit, and the nodes in the loops are located in the same strongly connected branch, this invention uses Kosaraju... [8] The algorithm calculates the topological order of signal nodes and then calculates the measurability features based on the topological order, which is more efficient than the recursive calculation based on the signal path.

[0100] Once the topology order is determined, the controllability index of each device can be calculated by traversing from the input port to the output port in sequence. After the controllability of all inputs of a logic gate is determined, the output controllability can be calculated. The basic idea is that the controllability index of the logic gate's output signal is equal to the minimum sum of the controllability indices of the input signals that need to be controlled to set that signal to 1 or 0, plus 1. The controllability calculation of basic logic devices is as follows: Figure 5 As shown.

[0101] After all signal controllability indices are established, the observability index is calculated by traversing each device in reverse order from output to input. Once the observability index of the logic gate's output signal is determined, the observability of the input signal can be calculated. The basic idea is that the observability index of the logic gate's input signal equals the observability index of the output signal plus the minimum sum of the controllability indices required to set other input signals to non-controllable values, plus 1. The calculation of the observability index of basic logic devices is as follows: Figure 6 As shown.

[0102] 3.3 Global Average Assignment of Breakpoints

[0103] Previously, in Step 3.1, the breakpoint signal was treated as an I / O port and its testability characteristic value had already been calculated once. Obviously, the testability characteristic value of the breakpoint signal would be greatly reduced, thereby indirectly lowering the testability characteristic value of nearby signal nodes. Therefore, this step uses the method of assigning a global average characteristic value to the breakpoint to re-initialize the testability characteristic value in order to drive the second testability index calculation to further approximate the original characteristic value.

[0104] Since the MO-type breakpoint signal input is not missing, its controllability index is relatively accurate after the first calculation of the measurability index. Similarly, the MI-type breakpoint signal's observability index is relatively accurate. Therefore, the controllability index of the MI-type breakpoint signal is initialized to the average controllability of the MO-type breakpoint signal, and the observability index of the MO-type breakpoint signal is initialized to the average observability index of the MI-type breakpoint signal. Furthermore, to eliminate the influence of constant signals, the eigenvalue range of the signals participating in the averaging operation needs to be checked. That is, each signal is initialized using the following equation 6-10.

[0105] cc0(v)=cc1(v)=1, co(v)=∞, v∈I (26)

[0106] cc0(v)=cc1(v)=∞, co(v)=0, v∈O (27)

[0107]

[0108]

[0109]

[0110] For Trojan breakpoints, averaging the initial characteristic value significantly increases the overall characteristic value of the Trojan triggering circuit. However, for ordinary breakpoints, averaging the initial characteristic value avoids making it too large, which could lead to false alarms due to excessively high characteristic values ​​in the normal circuit. After initializing the breakpoints with a global average assignment, the testability index is recalculated to provide more reliable characteristic values ​​for subsequent range search assignments.

[0111] 3.4 Breakpoint Range Search and Assignment

[0112] After global averaging, the breakpoint feature values ​​are closer to the original feature values ​​than when treated as I / O. However, when breakpoint signals of MI and MO classes are correlated, the feature values ​​calculated for subsequent breakpoint signals tend to be lower. Averaging, on the other hand, causes breakpoint feature values ​​to become too uniform, making it difficult to identify some malware nodes. Therefore, this invention proposes combining layout location information with a range search of breakpoint signals to differentiate breakpoint feature values, further approximating the original breakpoint feature values ​​and thus exposing malware nodes. The breakpoint range search and assignment algorithm flow is as follows: Figure 7 As shown.

[0113] After calculating the initial data, this step initializes the feature values ​​for MO-type breakpoints, MI-type breakpoints, and remaining points respectively.

[0114] Kd-tree [9] This is a data structure used for region lookup in computational geometry. It offers excellent performance, balancing storage space and search time, and is suitable for breakpoint range search tasks involving incomplete gate-level netlists. First, a kd-tree is constructed starting from non-isolated breakpoint signals; second, values ​​are assigned to MO-type breakpoint range search as follows... Figure 8 As shown in Equation 11, a range search is performed on each MO-type breakpoint signal, and the average CO feature value of the searched MI-type breakpoint signals is assigned to the MO-type breakpoint signal that started the search.

[0115]

[0116] Where SNI={node|node∈SN∩node∈MI∩co(node)<∞} is the set of MI-class breakpoint signals obtained by the search and whose CO feature values ​​are valid, and SN is the set of nodes returned by the kd-tree range search.

[0117] Similarly, the assignment of values ​​for the breakpoint range search of MI type is as follows: Figure 9 As shown, a range search is performed for each MI-type breakpoint signal, and the average of the CC1 and CC0 feature values ​​of the searched MO-type breakpoint signals is assigned to the MI breakpoint signal that started the search, as shown in Equations 12 and 13.

[0118]

[0119]

[0120] Wherein, SNO0={node|node∈SN∩node∈MO∩cc0(node)<∞} is the set of MO class breakpoint signals obtained by searching and whose CC0 eigenvalues ​​are valid. SNO1={node|node∈SN∩node∈MO∩cc1(node<∞} is the set of MO class breakpoint signals obtained by searching and whose CC1 eigenvalues ​​are valid.

[0121] If no target class breakpoint signal is found, the average feature value of the target class breakpoint signal is assigned to the breakpoint signal that initiated the search. Similar to step 3.3, a feature value range check is required when calculating the mean and range search. The measurability feature values ​​calculated in this initial measurability step are closer to the original feature values ​​and have differentiated characteristics, thus effectively supporting the clustering judgment in Step 4.

[0122] 4. Clustering judgment

[0123] Due to their stealth, Trojan signal nodes have much larger CC1, CC0, and CO eigenvalues ​​than normal nodes. This is reflected in the two-dimensional plane of measurable eigenvalues ​​with CC and CO as the x and y axes. Trojan nodes are far away from normal node clusters, and Trojan signal node clusters are distributed at x-inf and y-inf, while normal signal node clusters are distributed near the origin.

[0124] Therefore, this step first merges the CC0 and CC1 eigenvalues ​​of each signal node into a single eigenvalue CC, as shown in Formula 14:

[0125]

[0126] Secondly, through K-means

[10] The clustering algorithm divides the signal nodes into three classes; then, it determines whether each cluster is a Trojan signal node cluster based on the inter-class distance. Finally, the detection results are reported.

[0127] The clustering process is performed on the entire controllable and observable node set N = {n1, n2, ..., n}. M To proceed, first input the points n. i ∈N represents the set of eigenvectors D = {(CC(n)} i ),CO(n i )),n i ∈N}. Secondly, considering the distribution characteristics of Trojan nodes, the origin, the point with the largest observable value, and the point with the largest controllable value are selected as the initial cluster center set {μ1,μ2,μ3}, as shown in Equation 15.

[0128]

[0129] Finally, iterate through set D and calculate n. i Node corresponding feature vector D i Euclidean distance d from the center of each cluster ij As shown in Equation 16, clusters are divided according to the distance of each point to the nearest cluster center, as shown in Equations 17-18, where λ i For n i Node cluster label, C λi For n i The node is assigned to the node cluster. The cluster center position is updated as shown in Equation 19.

[0130] d ij =||D i -u j || 2 ,D i ∈D,j∈{1,2,3} (36)

[0131] λ i =arg min j∈{1,2,3}d ij (37)

[0132]

[0133]

[0134] The process continues until it converges and stabilizes to the final node cluster partition {C1,C2,C3} and cluster center {μ1,μ2,μ3}.

[0135] The classification is based on a difference threshold related to the standard deviation of ordinary node clusters. Clusters exceeding this threshold are classified as Trojan horse clusters. First, based on the distance from the cluster center to the origin, clusters are labeled C1, C2, and C3 from smallest to largest. Second, the standard deviation σ1 of cluster C1 is calculated, as shown in Equation 20:

[0136]

[0137] Where K is the number of nodes in cluster C1, and μ is the center vector of cluster C1. Setting a threshold T1 = 3σ1, the distance between classes C1 and C2 is calculated as I. 12 , if I 12 If T1 >, then C2 and C3 are both determined to be Trojan node clusters; if I 12 If the threshold is ≤T1, then C2 is determined to be a normal node cluster, and C1 and C2 are considered to be the same normal node cluster. The standard deviation σ2 of clusters C1 and C2 is calculated, and a new threshold T2 = 3σ2 is set to determine cluster C3. The inter-cluster distance between clusters C1, C2 and C3 is calculated as I. 12,3 , if I 12,3 If T2 is selected, C3 is determined to be a Trojan node cluster; otherwise, C3 is determined to be a normal node cluster.

[0138] Finally, uncontrollable or unobservable nodes, as well as clusters of Trojan nodes identified through clustering, are reported to the user as Trojan nodes.

[0139] As shown in the table, the present invention has an average detection rate of up to 98.3% for all loss types and loss ratios, and an average false alarm rate of 0.64%, enabling high-precision hardware backdoor detection for incomplete gate-level netlists.

[0140]

[0141]

Claims

1. A high-precision hardware backdoor detection method for incomplete gate-level netlists, the method comprising: Step 1: Preprocessing and modeling of incomplete gate-level netlists; First, read the incomplete gate-level netlist file and extract the I / O and internal signal nodes to form a set of vertices in a directed graph. Each vertex object in the set has a signal name, a driving logic unit name, and a driving logic unit type; Secondly, the input and output signal node pairs of the logic devices are mapped to the edges of a directed graph, forming an edge set. ; one of the sides Represents vertices A node is an input node of a device, and in a directed graph, it points to an output node of the same device. Each edge includes: the name of the head node, the name of the tail node, the name of the input signal pin, and the name of the logic device to which it belongs. Each gate-level logical netlist is mapped to a directed graph. From vertex set and edge set composition; Step 2: Identification and location of breakpoint signals; Import the GDSII file into an EDA (Electronic Design Automation) tool, and use the EDA tool to perform a Design Rule Check (DRC) on the layout to filter out open circuit signals. Secondly, obtain the disconnection information. Pin names connected to the device and will Breakpoint type Classification as shown in Equation 1: ； in, It is an empty set. ,in This refers to the output pin names of different devices in the component library; that is, if a disconnect signal is not connected to any device pin, it is denoted as [pin name missing]. Breakpoint-like signals, A breakpoint signal is an isolated breakpoint signal. Otherwise, if the breakpoint signal is not connected to any device output pin, it is called an MI breakpoint signal, which represents an input missing breakpoint signal. If it is connected to any device output pin, it is called an MO breakpoint signal, which represents an output missing breakpoint signal. Finally, non Breakpoint signal Normalized coordinate position of any connected logic device relative to the lower left corner of the IC core Enter the location attribute of the breakpoint signal and the breakpoint type in the breakpoint type attribute; Step 3: Iteratively calculate the testability feature values; Testability includes three metrics: , , That is, signal Combinatorial controllability, combinatorial controllability, and combinatorial observability; Step 3.1: Initialize I / O using breakpoints; Define the chip input port set as The output port set is Then perform initialization operations from Equations 2 to 5 on each node; ； ； ； ； Step 3.2: Calculate the testability feature values; First, the topological order of the signal nodes is determined so that the calculation of the signal node feature values ​​can be completed in an orderly manner under linear time complexity. Then, the controllability features of the signal nodes are calculated according to the forward topological order, i.e., the order from input to output. Finally, the observability features of the signal nodes are calculated according to the reverse topological order, i.e., the order from output to input. The topological order of the signal nodes was determined using the Kosaraju algorithm. The controllability index of the logic gate output signal is equal to the minimum sum of the controllability indices of the input signals that need to be controlled to set the signal to 1 or 0, plus 1. The observability index of a logic gate input signal is equal to the observability index of the output signal plus the minimum sum of the controllability indices required to set other input signals to non-controllable values, plus 1. Step 3.3: Assign global average values ​​to breakpoints; The controllability index of MI-type breakpoint signals is initialized to the average controllability of MO-type breakpoint signals, while the observability index of MO-type breakpoint signals is initialized to the average observability index of MI-type breakpoint signals. In addition, in order to eliminate the influence of constant signals, the characteristic value range of the signals participating in the mean calculation needs to be checked; that is, the initialization operation of each signal is performed as shown in Equation 6-10. ； ； ； ； ； in, Indicates a single breakpoint signal; Then calculate the testability index again to provide more reliable feature values ​​for subsequent range search assignment; Step 3.4: Set values ​​for the breakpoint range search; First, construct a kd-tree starting from the non-isolated breakpoint signals; second, perform a range search for each MO-class breakpoint signal, and then combine the searched MI-class breakpoint signals... The average eigenvalue is assigned to the MO-class breakpoint signal that initiates the search, as shown in Equation 11. ； in, For search results and The set of MI-class breakpoint signals with valid eigenvalues. Returns a set of nodes for a range search in a kd-tree; Similarly, perform a range search for each MI-type breakpoint signal, and then use the searched MO-type breakpoint signals... The average eigenvalues ​​are assigned to the MI breakpoint signal that initiates the search, as shown in Equations 12 and 13. ； ； in, For search results and A set of MO-class breakpoint signals with valid eigenvalues; For search results and A set of MO-class breakpoint signals with valid eigenvalues; If no target class breakpoint signal is found, the average feature value of the target class breakpoint signal is assigned to the breakpoint signal that started the search. Step 4: Clustering determination; First, each signal node... and Eigenvalues ​​are merged into one eigenvalue As shown in Formula 14: ； Secondly, the signal nodes are divided into three categories using a clustering algorithm; then, the inter-class distance is used to determine whether each cluster is a Trojan signal node cluster; finally, the detection results are reported.

2. The high-precision hardware backdoor detection method for incomplete gate-level netlists as described in claim 1, characterized in that, The clustering method in step 4 is as follows: The clustering process is performed on all controllable and observable node sets. To proceed, first input the points. The eigenvector set represented as a two-dimensional eigenvector Secondly, considering the distribution characteristics of Trojan nodes, the origin, the point with the largest observable value, and the point with the largest controllable value are selected as the initial cluster center set. As shown in Equation 15: ； Finally, continuously traverse the set. ,calculate Node corresponding feature vector Euclidean distance from the center of each cluster As shown in Equation 16, clusters are divided according to the distance of each point to the nearest cluster center, as shown in Equations 17-18. for Node cluster marker, for The node is assigned to the node cluster; and the cluster center position is updated as shown in Equation 19: ； ； ； ； Until convergence and stabilization to the final node cluster partitioning and cluster center .

3. The high-precision hardware backdoor detection method for incomplete gate-level netlists as described in claim 1, characterized in that, The method for determining whether each cluster is a Trojan signal node cluster by inter-class distance in step 4 is as follows: The classification and judgment process involves setting a difference threshold related to the standard deviation of ordinary node clusters. When the distance between clusters exceeds the threshold, they are identified as Trojan horse clusters. First, based on the distance from the cluster center to the origin, each cluster is marked from smallest to largest. Secondly, calculation Cluster standard deviation As shown in Equation 20: ； Where K is Number of cluster nodes for Cluster center vector; set threshold ,calculate Inter-class distance is ,like Then determine All are clusters of Trojan horse nodes; if Then determine For ordinary node clusters, and Treating them as the same normal node cluster, calculate Cluster standard deviation And set a new threshold To judge Cluster; computation Clusters and The distance between clusters is ,like Then determine If it is a Trojan node cluster, otherwise determine... It is a normal node cluster; Finally, uncontrollable or unobservable nodes, as well as clusters of Trojan nodes identified through clustering, are reported to the user as Trojan nodes.

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