Multi-threaded synthesis optimization method based on hierarchical structure partitioning and recombination

Abstract

The application belongs to the technical field of digital circuit, and particularly relates to a multi-thread comprehensive optimization method based on hierarchical structure division and reorganization. The application first performs RTL synthesis on user design to generate a hierarchical structure module; then divides and reorganizes the generated hierarchical structure to generate a multi-module hierarchical structure with uniform size; and finally simultaneously performs synthesis on multiple modules by using a multi-thread scheduling algorithm. The key of the application lies in that an effective hierarchical division and reorganization algorithm is provided. For a super large scale integrated circuit, the optimization speed is greatly improved while the optimization effect is ensured, so that the efficiency of chip development and test is improved.

Description

Technical Field

[0001] This invention belongs to the field of digital circuit technology, specifically relating to a multi-threaded synthesis optimization method based on hierarchical structure partitioning and reorganization. Background Technology

[0002] Logic synthesis maps user-designed logic functions (i.e., Boolean algebra) to devices in a standard device library. Logic synthesis mainly consists of two parts: logic optimization and process mapping. Logic optimization refers to optimizing the gate-level netlist to eliminate redundant logic. Process mapping involves converting the logic-optimized gate-level netlist into library cells corresponding to the specified process technology.

[0003] A module is a fundamental concept in circuit design, representing a function. Every design system consists of several modules. Modern large-scale integrated circuits are hierarchical, multi-module designs, with circuit scales reaching tens of billions of transistors. The traditional approach is to flatten the entire design down to the top-level module and then perform synthesis optimization on that module. However, this method is increasingly inadequate for handling very large-scale designs. Currently, a common approach is to preserve the original hierarchical structure of the user design and employ multi-threaded methods for parallel synthesis optimization of multiple modules. However, this method suffers from a significant decrease in synthesis results compared to traditional methods, and synthesis time remains largely unchanged. Neither of these methods adequately meets the needs of modern designs. This invention proposes a multi-threaded synthesis optimization method based on hierarchical structure partitioning and reorganization, which improves synthesis speed while maintaining optimization quality, effectively solving the synthesis problems of very large-scale designs.

[0004] Explanation of proper nouns:

[0005] Logic synthesis: The process of mapping user-designed logic functions (i.e., Boolean algebra) to devices in a standard device library;

[0006] Multithreading: Multithreading technology refers to using multiple threads to perform calculations simultaneously for highly parallel tasks, thereby achieving the goal of speeding up the process.

[0007] Module flattening: Merging a submodule into the calling module at the upper level;

[0008] Module partitioning: Divide a module into a series of sub-modules, ensuring equivalence before and after the partitioning;

[0009] Rent's rule: The exponential relationship between the number of input / output ports and the number of logic gates in a circuit module: p = kn r , where p is the number of ports, n is the number of logic units, k is the coefficient, and r is the rand index. Summary of the Invention

[0010] The purpose of this invention is to propose a multi-threaded synthesis optimization method based on hierarchical structure partitioning and reorganization, so as to improve synthesis speed and ensure optimization quality.

[0011] This invention divides and reorganizes the user-designed hierarchical structure into modules to generate a multi-module hierarchy with relatively uniform size. Then, it uses a multi-threaded scheduling algorithm to synthesize multiple modules, thereby achieving high-performance synthesis of ultra-large-scale circuits and solving the ultra-large-scale design problem that is difficult for current advanced synthesis tools at home and abroad to handle.

[0012] The multi-threaded comprehensive optimization method based on hierarchical structure partitioning and reorganization proposed in this invention includes the following steps:

[0013] (i) The hardware description language (HDL) file designed by the user is synthesized by RTL to generate a hierarchical structure module and converted into a process-independent gate-level netlist.

[0014] (ii) Use a cross-module global optimization algorithm to perform cross-module global optimization on the gate-level netlist generated in step (i);

[0015] (iii) A partial flattening algorithm based on a hierarchical structure is used to partially flatten the netlist optimized in step (ii) to remove sub-modules that are too small or have too shallow logical depth.

[0016] (iv) The super-large modules in the netlist generated in step (iii) are actively partitioned using a module partitioning algorithm to generate sub-modules of relatively uniform size;

[0017] (v) Use a multi-threaded scheduling algorithm to optimize multi-module, multi-threaded parallel logic and process mapping.

[0018] This invention involves three key technologies: a cross-module global optimization algorithm for hierarchical circuits, a hierarchical structure reorganization algorithm, and a multi-threaded scheduling algorithm; each will be described in detail below.

[0019] The cross-module global optimization algorithm described in step (II).

[0020] This mainly includes constant elimination, logic gate simplification, and redundant logic gate elimination optimization. In hierarchical design, the algorithm traverses all nets starting from the input port of the top-level module. If a net is a constant signal (VCC or GND), it analyzes whether the logic gates connected to this net can be simplified and how to make the output of the simplified logic gates constant. Then, it further analyzes the logic gates that simplify its connections. If a constant signal is output to an instance, the circuit module of this instance is processed one-to-one to generate a circuit module that is only bound to this instance, and the constant signal is passed to the corresponding input port of this circuit module for further constant optimization.

[0021] The algorithm continuously performs constant signal passing and logic gate simplification until no logic gate can be simplified. Constant signal passing can be performed across module levels, thus achieving global optimization on a hierarchical netlist.

[0022] The partial flattening algorithm described in step (iii).

[0023] Currently, with the increasing scale of circuit designs, implementing circuits using a single module is no longer suitable. Most designs consist of a top-level module and multiple sub-modules. For the hierarchical structure originally designed by the user, sub-modules that are too small or have a shallow average logic depth are detrimental to the quality of the final logic synthesis. Moreover, if there are too many small modules, it will also increase the overhead of creating, closing, and switching threads, thereby reducing the overall efficiency of multi-threaded logic synthesis. Therefore, this invention performs a flattening operation on these sub-modules that are too small or have a shallow average logic depth. The specific algorithm is as follows:

[0024] (1) Traverse the entire netlist. To avoid repetition, a bottom-up traversal method is used. For each module, this algorithm uses the number of logic gate characters LN and the average logic depth parameter K to evaluate its size and average logic depth, respectively. The formula for calculating K is:

[0025]

[0026] In the formula, input_num and output_num represent the number of input / output ports of the module, respectively;

[0027] (2) For modules with LN less than Φ1 or K less than Φ2, call the Flatten function to flatten them to the next level; here Φ1 is an empirical value, which can be flexibly determined according to the size of the user circuit design, and the recommended value range is 1000-20000; in this invention, the value of this parameter can be 1000; Φ2 is an empirical value, which can be flexibly determined according to the different types of user circuit design, and the recommended value range is 1-10; in this invention, the value of this parameter can be 5.

[0028] The pseudocode for the partial flattening algorithm for hierarchical structures is attached as Appendix 1.

[0029] The module partitioning algorithm described in step (iv).

[0030] After the partial flattening algorithm of the hierarchical structure, all overly small modules in the netlist have been flattened into higher-level modules. At this point, some modules in the netlist may have a much larger number of logic gates than other modules. These overly large modules will cause their synthesis optimization time to be much longer than that of other modules, affecting the acceleration effect of multi-threaded algorithms. Therefore, this invention proposes an active module partitioning algorithm to divide these overly large logic modules into several modules of relatively uniform size, thereby improving the multi-threaded acceleration effect. The module partitioning algorithm adopts the MFFC partitioning algorithm and the connectivity-based clustering algorithm, and avoids partitioning logic gates with many connections according to the Lant rule, thus ensuring that the module partitioning does not have a significant impact on the optimization effect. In this way, it can improve the multi-threaded optimization acceleration effect while ensuring the optimization quality.

[0031] The module partitioning algorithm used in this invention has the following specific steps:

[0032] (1) Generate an initial cluster based on the MFFC (max fanout-free cone) of logic gates, i.e., a small-scale partition. For other elements, generate a cluster for each element.

[0033] (2) Count the connections between each cluster (the number of lines connecting each cluster) and generate a Connectivity Map (CM);

[0034] (3) Select the largest cluster (i.e., the one with the most logic gates) from the initial clusters;

[0035] (4) Check if the current cluster size is large enough. If so, proceed to process (5). If not, merge it with the cluster with the closest connection and merge the connection relationship statistics tables of the two clusters at the same time.

[0036] (5) Determine whether all initial clusters have been merged. If not, repeat step (3). If yes, exit the partitioning process.

[0037] (6) Generate new modules and hierarchical structures based on the partitioning results.

[0038] The pseudocode for the module partitioning algorithm is attached as Appendix 2; the algorithm flowchart is shown below. Figure 2 See the algorithm diagram. Figure 3 , Figure 4 .

[0039] This invention proposes a logic synthesis process suitable for multi-threaded acceleration, and also designs an algorithm for quickly partitioning excessively large-scale modules. Combining the two further accelerates the running speed of the entire logic synthesis, shortens the running time, and ensures good optimization results.

[0040] The multi-threaded computation scheduling algorithm described in step (v) sorts the modules from largest to smallest based on the number of logic gates; then, each module is assigned a thread for comprehensive optimization computation; for a given number of threads mt, mt modules are selected from the module queue and mt threads are assigned to them for comprehensive optimization operation; after a thread completes its operation, a new unprocessed module is selected and a new thread is assigned; the scheduling algorithm will execute this process until all modules have completed comprehensive optimization computation.

[0041] This invention designs a logic synthesis process suitable for multi-threaded acceleration, and also designs an algorithm for quickly partitioning excessively large-scale modules. Combining the two further accelerates the running speed of the entire logic synthesis, shortens the running time, and ensures good optimization results. Attached Figure Description

[0042] Figure 1 This is a flowchart of the multi-threaded comprehensive optimization method of the present invention.

[0043] Figure 2 Flowchart of the module partitioning and reorganization algorithm.

[0044] Figure 3 This is a diagram illustrating the module division.

[0045] Figure 4 This is a schematic diagram of module reorganization. Detailed Implementation

[0046] This invention proposes a hierarchical structure module partitioning and reorganization algorithm. The specific process is as follows: traverse the entire netlist. For each module in the netlist, its size is measured by the number of literals (the size of the bytes occupied by its logic functions) and the number of components. Modules with too few literals or components are simply flattened. Medium-sized modules are retained without processing. For excessively large modules, a clustering algorithm is used to partition them, generating new modules and a hierarchical structure. These new modules are relatively similar in size. Finally, these modules are processed in parallel for subsequent logic optimization and process mapping.

[0047] Tables 1 and 2 compare the experimental results (4 threads) of the proposed solution with the synthesis results of Baseline (an industrial FPGA synthesis software). The test examples are a set of open-source test suites ranging from tens of thousands to millions of LUTs. The Baseline column in the tables shows the results of running the Baseline software, while Ours-MT4 shows the results of running the proposed solution with 8 threads. Table 1 uses the results of the default Baseline synthesis flow (flattening the entire netlist to the top-level module, then performing logic optimization and process mapping on the top-level module) as a reference. The comparison shows that, with comparable area (0.19%), the running speed is 34.81 times faster than before, while timing performance is also improved by 1.25%. Table 2 shows the results of Baseline using 8-thread hierarchical synthesis. The comparison shows that, with comparable area (-0.74%), the running speed is 6.7 times faster than before, while timing performance is also improved by 2.9%.

[0048] The above specific embodiments are specific support for the fast logic synthesis solution proposed in this invention, and should not be used to limit the scope of protection of this invention. Any equivalent changes or modifications made on the basis of this technical solution in accordance with the technical ideas proposed in this invention shall still fall within the scope of protection of this invention.

[0049] Table 1: Synthesis results of Baseline1 and ours

[0050]

[0051] Table 2: Synthesis results of Baseline2 and ours

[0052]

[0053] Appendix 1: Pseudocode for Hierarchical Structure Partial Flattening Algorithm

[0054]

[0055] Appendix 2: Pseudocode for the Module Partitioning Algorithm

Claims

1. A multi-threaded comprehensive optimization method based on hierarchical structure partitioning and reorganization, characterized in that, The specific steps are as follows: (i) The hardware description language (HDL) file designed by the user is synthesized by RTL to generate a hierarchical structure module and converted into a process-independent gate-level netlist; (ii) A cross-module global optimization algorithm is used to perform cross-module global optimization on the gate-level netlist generated in step (i); (iii) A hierarchical partial flattening algorithm is used to partially flatten the netlist optimized in step (ii) to remove sub-modules with too few logic gate characters or too shallow logic depth. The specific process of the algorithm for partially flattening the figure is as follows: (1) Traverse the entire netlist. For each module, evaluate its size and average logic depth using the number of logic gate characters LN and the average logic depth parameter K, respectively. The formula for calculating K is: ， (1) In the formula, and These represent the number of input / output ports for the module, respectively. (2) For modules with LN less than Φ1 or K less than Φ2, call the Flatten function to flatten them to the next level; here Φ1 is an empirical value, which is flexibly determined according to the size of the user circuit design, and the value range is 1000-20000; Φ2 is an empirical value, which is determined according to the different types of user circuit design, and the value range is 1-10. (iv) The super-large modules in the netlist generated in step (iii) are actively partitioned using a module partitioning algorithm to generate uniformly sized sub-modules; (v) Use a multi-threaded scheduling algorithm to optimize multi-module, multi-threaded parallel logic and process mapping.

2. The multi-threaded synthesis optimization method according to claim 1, characterized in that, The cross-module global optimization algorithm described in step (II) includes constant elimination, logic gate simplification, and redundant logic gate elimination optimization; Specifically, starting from the input port of the top-level module, all nets are traversed. If a net is a constant signal (VCC or GND), the logic gates connected to this net are analyzed to see if they can be simplified and how to make the output of the simplified logic gates constant. Then, the logic gates that simplify its connections are further analyzed. If a constant signal is output to an instance unit, the circuit module of this instance unit is processed one-to-one to generate a circuit module that is only bound to this instance unit. The constant signal is then passed to the corresponding input port inside this circuit module for further constant optimization. Continuously pass constant signals and simplify logic gates until no logic gate can be simplified.

3. The multi-threaded synthesis optimization method according to claim 1, characterized in that, The module partitioning algorithm described in step (iv) has the following specific steps: (1) Generate an initial cluster based on MFFC for logic gates, i.e., a small-scale partitioning, and generate a cluster for each other element; (2) Count the connections between each cluster, i.e. the number of connecting lines between each cluster, and store them in CM; (3) Select the largest cluster from the initial clusters, that is, the cluster with the most logic gates; (4) Check if the current cluster size is large enough. If so, proceed to process (5). If not, merge it with the cluster with the closest connection and merge the connection relationship statistics tables of the two clusters at the same time. (5) Determine whether all initial clusters have been merged. If not, repeat step (3). If yes, exit the partitioning process. (6) Generate new modules and hierarchical structures based on the partitioning results.

4. The multi-threaded synthesis optimization method according to claim 3, characterized in that, The multi-threaded computation scheduling algorithm described in step (5) sorts the modules from largest to smallest based on the number of logic gates, and then assigns a thread to each module for comprehensive optimization computation. Specifically, for a given number of threads mt, mt modules are selected from the module queue and mt threads are assigned to them for comprehensive optimization. After a thread completes its operation, a new unprocessed module is selected and a new thread is assigned to it. This process is repeated until all modules have completed their comprehensive optimization computation.

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