Method of forming gate oxide layer and method of forming shield gate trench device

Abstract

The application provides a gate oxide layer forming method and a shield gate trench type device forming method, and applies to the technical field of semiconductors. According to the forming method, after a shield gate polysilicon with a first height is formed by using an etching process, the top corner of the shield gate polysilicon with the first height is not directly subjected to an oxidation process to form the gate oxide layer as in the prior art, but is first reduced from a right angle or an acute angle to a round angle with two arc-shaped sides, and then is subjected to the oxidation process, so as to reduce the diffusion distance of oxygen atoms (oxygen) in the subsequent oxidation process by reducing the top corner of the exposed shield gate polysilicon, and thus ensure that the exposed shield gate polysilicon after the corner reduction can be completely oxidized, and thus all of the shield gate polysilicon is converted into the gate oxide layer, that is, the C GP gate oxide layer, the shield gate polysilicon gate and the gate oxide layer are reduced, and the switching loss of the device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming an inter-gate oxide layer and a method for forming a shielded gate trench device. Background Technology

[0002] Power MOSFETs with shielded gate trenches (SGTs) represent the most advanced power MOSFET technology currently available. They simultaneously achieve low on-resistance (Rdson) and low reverse recovery capacitance (Crss), thereby reducing both conduction and switching losses and improving system efficiency. The gate structure of a shielded gate trench device includes a shielded polysilicon and a polysilicon gate (also known as the control gate). The shielded polysilicon, often referred to as source polysilicon or shielded gate, is formed within the trench. Depending on the placement of the shielded polysilicon and the polysilicon gate within the trench, they are typically classified as either a top-bottom structure or a left-right structure. In a top-bottom structure, the shielded polysilicon is located at the bottom of the trench, and the polysilicon gate is located at the top, with the polysilicon gate and shielded polysilicon in a top-bottom relationship.

[0003] Currently, there are generally two approaches to fabricating the inter-gate oxide IPO (Initial Gate Oxide) layer for shielded gate trench devices (SGTs) with an upper and lower structure. One approach involves forming the shielded gate in the trench and then depositing and etching an inter-gate oxide IPO layer on the top surface of the shielded gate. This approach is complex and has high process requirements. The other approach involves forming the shielded gate polysilicon in the trench and then exposing the top of the shielded gate polysilicon by etching back the shielded dielectric layer deposited on the trench sidewalls. The exposed shielded gate polysilicon is then oxidized to obtain the resulting silicon dioxide as the inter-gate oxide IPO layer. Obviously, compared to the first approach, the second approach has a simpler and more stable process.

[0004] However, in the current second approach, because it uses an etching process to remove the shielding dielectric layers on both sides of the shielding gate polysilicon to expose the shielding gate polysilicon of a predetermined height, the height of the exposed shielding gate polysilicon is much higher than the height of the remaining shielding dielectric layers after etching on both sides. Figure 1 As shown, this leads to the subsequent filling of the polysilicon gate, the inter-gate oxide layer, and the shielding gate, forming the C... GP Larger, while C GP A larger value results in a larger gate charge Qg and a larger Qgs between the gate and drain, which increases the switching losses of the shielded gate trench device during the switching process. Summary of the Invention

[0005] The purpose of this invention is to provide a method for forming an inter-gate oxide layer and a method for forming a shielded gate trench device. In the process of forming the inter-gate oxide layer using a thermal oxidation process, by employing techniques such as corner reduction and thinning, the thickness and height of the shielded gate polysilicon exposed after etching for thermal oxidation into the inter-gate oxide layer are reduced. This allows the height-reduced shielded gate polysilicon to be fully oxidized, i.e., completely converted into the inter-gate oxide layer, thereby reducing the C-value of the polysilicon gate, inter-gate oxide layer, and shielded gate. GP The purpose is to reduce the switching losses of the devices.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for forming an inter-gate oxide layer, which may include at least the following steps:

[0007] A semiconductor substrate is provided, wherein at least one trench is formed in the semiconductor substrate, a shielding dielectric layer is covered on the inner surface of the trench, and a shielding gate polysilicon is filled in the lower space of the trench.

[0008] The shielding dielectric layer is wet-etched, removing at least a portion of the shielding dielectric layer along a direction perpendicular to the surface of the semiconductor substrate, to expose the shielding gate polysilicon with a first height and a right angle or acute angle at the top corner.

[0009] The exposed top corners of the shielding gate polysilicon, which are either right angles or acute angles, are subjected to corner-reduction treatment so that the top corners of the exposed shielding gate polysilicon are transformed from right angles or acute angles into rounded corners;

[0010] The semiconductor substrate is subjected to a thermal oxidation process to oxidize the shielding gate polysilicon with a preset height and rounded corners to silicon dioxide, and the silicon dioxide is used as the inter-gate oxide layer, and the remaining unoxidized shielding gate polysilicon located below the silicon dioxide is used as the shielding gate.

[0011] Furthermore, before or after performing corner-reducing treatment on the exposed top corner of the shielding gate polysilicon which is at a right angle or an acute angle, the method for forming the inter-gate oxide layer provided by the present invention further includes: a step of thinning the height of the shielding gate polysilicon from a first height to a second height along a direction perpendicular to the surface of the semiconductor substrate.

[0012] Furthermore, the ratio of the second height to the first height can specifically be 30%-90%.

[0013] Furthermore, the thickness range of the shielding dielectric layer covering the inner surface of the trench can specifically be:

[0014] Furthermore, in the step of wet etching the shielding dielectric layer to remove the shielding dielectric layer at a predetermined height on both sides of the shielding gate polysilicon in a direction perpendicular to the surface of the semiconductor substrate, a portion of the thickness of the shielding dielectric layer covering the sidewalls of the upper space of the trench can also be simultaneously etched in a direction parallel to the surface of the semiconductor substrate. This allows the thickness range of the remaining shielding dielectric layer on the sidewalls of the upper space of the trench to be specifically:

[0015] Furthermore, after performing corner-removing treatment on the exposed top corner of the shielding gate polysilicon, which has a right angle or an acute angle, the method for forming the inter-gate oxide layer provided by the present invention further includes the step of performing P-type or N-type ion implantation on the shielding gate polysilicon along the depth direction of the trench.

[0016] Furthermore, after the P-type or N-type ion implantation, the method for forming the inter-gate oxide layer provided by the present invention further includes: wet etching to remove the remaining shielding dielectric layer covering the sidewalls of the upper space of the trench, so as to expose the semiconductor substrate corresponding to the sidewalls of the upper space of the trench.

[0017] Furthermore, in the step of performing a thermal oxidation process on the semiconductor substrate to oxidize the shielding gate polysilicon of the exposed angle with a preset height into silicon dioxide, the semiconductor substrate exposed on the sidewall of the upper space of the trench can also be oxidized simultaneously to form a gate oxide layer of the shielding gate trench device on the sidewall of the upper space of the trench.

[0018] Furthermore, the material of the shielding dielectric layer may specifically include silicon dioxide.

[0019] Furthermore, in the thermal oxidation process, the preset height of the shielding gate polysilicon, which is oxidized to silicon dioxide by oxidizing the exposed, rounded-corner shielding gate polysilicon, can be the same as the second height.

[0020] Secondly, based on the method for forming the inter-gate oxide layer as described above, the present invention also provides a method for forming a shielded gate trench device, comprising:

[0021] Using the method described above for forming an inter-gate oxide layer, a shielding dielectric layer, a shielding gate, and an inter-gate oxide layer located on the top surface of the shielding gate are formed in a trench within a semiconductor substrate;

[0022] Polysilicon is filled in the trench to form a polysilicon gate, which is isolated from the semiconductor substrate by a gate oxide layer on the sidewall of the trench and from the shielding gate by an inter-gate oxide layer.

[0023] Furthermore, in the method for forming the shielded gate trench device provided in the embodiments of the present invention, the step of forming a trench in the semiconductor substrate may specifically include:

[0024] A semiconductor substrate is provided, and a hard mask layer is formed on the surface of the semiconductor substrate;

[0025] Using the hard mask layer as a mask, the semiconductor substrate is etched to form at least one of the trenches.

[0026] Furthermore, the hard mask layer may specifically include a first oxide layer and / or a second oxide layer stacked sequentially, or the hard mask layer may specifically include an ONO stack structure composed of a first oxide layer, a nitride layer and a second oxide layer stacked sequentially.

[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0028] In a method for forming an inter-gate oxide layer provided by the present invention, a shielding medium is first formed on the inner surface of a semiconductor substrate, and a trench filled with shielding polysilicon is formed in the lower space of the trench. Then, a portion of the shielding medium layer on both sides of the shielding gate polysilicon in the lower space of the trench is removed using a wet etching process along a direction perpendicular to the surface of the semiconductor substrate, so as to expose the shielding gate polysilicon with a height of a first height and a right angle or acute angle at the top corner. Then, the exposed shielding gate polysilicon with a right angle or acute angle at the top corner is subjected to a corner-reducing process to change the top corner of the exposed shielding gate polysilicon from the right angle or acute angle to a rounded corner. After that, a thermal oxidation process is performed on the semiconductor substrate to oxidize the exposed shielding gate polysilicon with a rounded corner at a predetermined height into silicon dioxide, and the silicon dioxide is used as the inter-gate oxide layer.

[0029] The method for forming the inter-gate oxide layer provided by this invention, after forming a shielding gate polysilicon with a first height using an etching process, does not directly perform an oxidation process to form the inter-gate oxide layer as in existing technologies. Instead, it first reduces the top corner of the shielding gate polysilicon of the first height from a right angle or acute angle to a rounded corner on both sides. Then, it performs an oxidation process to reduce the diffusion distance of oxygen atoms (oxygen) during subsequent oxidation by reducing the exposed top corner of the shielding gate polysilicon. This ensures that the exposed shielding gate polysilicon after corner reduction can be fully (completely) oxidized, thus converting it entirely into the inter-gate oxide layer. In other words, it ultimately reduces the C-value of the polysilicon gate, inter-gate oxide layer, and shielding gate. GP And to reduce the switching losses of the devices.

[0030] Furthermore, in the forming method provided by the present invention, after or before the corner of the first height of the shielding gate polysilicon is eliminated, the first height of the shielding gate polysilicon can be thinned, thereby reducing the height of the exposed shielding gate polysilicon for thermal oxidation into the inter-gate oxide layer. That is, by reducing the height of the exposed shielding gate polysilicon, the diffusion distance of oxygen atoms (oxygen) in the subsequent oxidation process is further reduced, thereby ensuring that the shielding gate polysilicon exposed after corner elimination can be fully (completely) oxidized, and thus completely transformed into the inter-gate oxide layer.

[0031] Meanwhile, due to the formation method provided by the present invention, the thickness of the shielding medium layer covering the sidewall of the upper space of the trench is reduced. Then, an ion implantation process is performed on the shielding gate polysilicon that has been treated by corner elimination and / or thinning in the lower space of the trench, thereby increasing the ion implantation dose and improving the ion implantation uniformity in the shielding gate polysilicon that has been treated by corner elimination and / or thinning. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the fabrication process in the existing method for forming the inter-gate oxide layer;

[0033] Figure 2 This is a schematic flowchart of a method for forming an inter-gate oxide layer according to an embodiment of the present invention;

[0034] Figures 3-9 This is a schematic diagram of the preparation process of a method for forming an inter-gate oxide layer according to an embodiment of the present invention;

[0035] Figure 10 This is an SEM image of the inter-gate oxide layer located in multiple trenches, formed using existing inter-gate oxide layer formation methods;

[0036] Figure 11 for Figure 10 A magnified view of a portion of the SEM image of the inter-gate oxide layer formed in one of the trenches shown in the SEM image;

[0037] Figure 12 To utilize Figure 2 The image shown is a SEM image of the inter-gate oxide layer formed in multiple trenches by the inter-gate oxide layer formation method provided in an improved embodiment of the present invention.

[0038] Figure 13 for Figure 12 A magnified view of a portion of the SEM image of the inter-gate oxide layer formed within one of the trenches shown, to compare with... Figures 3-9 The diagram shown corresponds to the structural schematic diagram in the preparation process;

[0039] Figure 14 This is a schematic flowchart of a method for forming a shielded trench device according to an embodiment of the present invention;

[0040] in, Figures 3-9 The specific reference numerals in the attached figures are as follows:

[0041] 100 - Semiconductor substrate; 110 / 110' / 110” - Shielding dielectric layer;

[0042] 120 - Shielding gate polysilicon; 130 - Inter-gate oxide layer;

[0043] 140 - Shielding gate; 150 - Gate oxide layer;

[0044] a - First altitude; b - Second altitude;

[0045] 101 - Trench; 160 - Polysilicon gate. Detailed Implementation

[0046] As described in the background section, there are currently two common approaches to fabricating the inter-gate oxide IPO (IPO) layer for shielded gate trench devices (SGTs) with an upper and lower structure. One approach involves forming the shielded gate in the trench and then depositing and etching an IPO layer on the top surface of the shielded gate. This approach is complex and has high process requirements. The other approach involves forming the shielded gate polysilicon in the trench and then exposing the top of the shielded gate polysilicon by etching back the shielded dielectric layer deposited on the trench sidewalls. The exposed shielded gate polysilicon is then oxidized to obtain the resulting silicon dioxide as the IPO layer. Obviously, compared to the first approach, the second approach has a simpler and more stable process.

[0047] However, in the current second approach, on the one hand, because it uses an etching process to remove the shielding dielectric layers on both sides of the shielding gate polysilicon to expose the shielding gate polysilicon of a predetermined height, the height of the exposed shielding gate polysilicon is much higher than the height of the remaining shielding dielectric layers on both sides after etching. For example... Figure 1 The C shown is C. GP This leads to the subsequent filling of the polysilicon gate, the inter-gate oxide layer, and the shielding gate, forming the C... GP Larger, while C GP A larger value results in a larger gate charge Qg and a larger Qgs between the gate and drain, which increases the switching losses of the shielded gate trench device during the switching process.

[0048] On the other hand, in the existing technology, after forming a shielding gate polysilicon in the lower space of a trench formed in a semiconductor substrate using deposition and chemical mechanical polishing (CMP) processes, an ion implantation process is performed on the shielding gate polysilicon located in the lower space of the trench to increase the ion doping concentration in the polysilicon and make it easier to oxidize. Therefore, the existing technology inevitably suffers from the problem that the thickness of the shielding dielectric layer (silicon dioxide) covering the sidewalls of the trench is relatively thick, which leads to a limited depth of the ion implantation process, resulting in problems with the uniformity of ion implantation and the limitation of implantation dose.

[0049] To address the two problems existing in the second solution mentioned above, the researchers of this invention have proposed solutions to improve upon them. Specifically, after forming a shielding gate polysilicon with a first height using an etching process, instead of directly performing an oxidation process to form the inter-gate oxide layer as in existing technologies, the top corner of the first-height shielding gate polysilicon is first reduced from a right angle or acute angle to a rounded corner on both sides. Then, an oxidation process is performed to reduce the diffusion distance of oxygen atoms (oxygen) during subsequent oxidation by reducing the exposed top corner of the shielding gate polysilicon, thereby ensuring that the exposed shielding gate polysilicon after corner reduction can be fully (completely) oxidized. Furthermore, the thickness of the shielding dielectric layer covering the sidewalls of the upper space of the trench is thinned. Finally, an ion implantation process is performed on the shielding gate polysilicon and the shielding dielectric layers on both sides of it in the lower space of the trench, after the corner reduction and / or thinning treatment.

[0050] To address this, the present invention provides a method for forming an inter-gate oxide layer and a method for forming a shielded gate trench device. During the process of forming the inter-gate oxide layer using a thermal oxidation process, the thickness and height of the shielded gate polysilicon exposed after etching, used for thermal oxidation to form the inter-gate oxide layer, are reduced through processes such as corner elimination and thinning. This allows the height-reduced shielded gate polysilicon to be fully oxidized, i.e., completely converted into the inter-gate oxide layer, thereby reducing the C-value of the polysilicon gate, inter-gate oxide layer, and shielded gate. GP The purpose is to reduce the switching losses of the devices.

[0051] refer to Figure 2 As shown, Figure 2 This is a schematic flowchart of a method for forming an inter-gate oxide layer according to an embodiment of the present invention; wherein, the method for forming an inter-gate oxide layer may include the following steps:

[0052] Step S201: A semiconductor substrate is provided, wherein at least one trench is formed in the semiconductor substrate, a shielding dielectric layer is covered on the inner surface of the trench, and a shielding gate polysilicon is filled in the lower space of the trench.

[0053] Step S202: Wet etching of the shielding dielectric layer, removing at least a portion of the shielding dielectric layer at both sides of the shielding gate polysilicon in a direction perpendicular to the surface of the semiconductor substrate, to expose the shielding gate polysilicon with a first height and a right angle or acute angle at the top corner;

[0054] Step S203: Perform corner-removal treatment on the exposed top corner of the shielding gate polysilicon, which is a right angle or an acute angle, so that the top corner of the exposed shielding gate polysilicon is changed from a right angle or an acute angle to a rounded corner;

[0055] Step S204: Perform a thermal oxidation process on the semiconductor substrate to oxidize the shielding gate polysilicon with a preset height and rounded corners to silicon dioxide, and use the silicon dioxide as the inter-gate oxide layer, and use the remaining unoxidized shielding gate polysilicon located below the silicon dioxide as the shielding gate.

[0056] The method for forming the inter-gate oxide layer and the method for forming the shielded gate trench device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may also be implemented in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0057] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0058] See Figure 3In step S201 above, a semiconductor substrate 100 is first provided. Specifically, the semiconductor substrate 100 can be any suitable substrate material known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors. It also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Alternatively, it can be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate. For example, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer.

[0059] Next, a hard mask layer (not shown) can be formed on the surface of the semiconductor substrate 100, and a trench 101 can be formed in the semiconductor substrate 100 using the hard mask layer as a mask. Then, a shielding dielectric layer 110 made of silicon dioxide can be deposited on the inner surface (both sidewalls and bottom) of the trench 101 using a deposition process.

[0060] Next, the trench 101 is filled with shielding gate polysilicon 120, and then subjected to chemical mechanical polishing (CMP) and etching to obtain the desired result. Figure 3 The shielding gate polysilicon 120 (remaining in the trench 101 after the CMP process) is shown filling the lower space of the trench 101. The thickness of the shielding dielectric layer 110 formed on the inner surface of the trench 101 at this time ranges from 8 mm. That is, specifically as well as arrive Any integer or decimal between any two values ​​will not be elaborated here.

[0061] It is understood that, in this embodiment of the invention, after the trench 101 is formed, the hard mask layer (not shown) can be removed. Therefore, the shielding dielectric layer 110 formed on the inner surface of the trench 101 also extends to the exposed surface of the semiconductor substrate 100.

[0062] As an example, the hard mask layer may be a first oxide layer and / or a second oxide layer stacked sequentially, or the hard mask layer may be an ONO stack structure composed of a first oxide layer, a nitride layer and a second oxide layer stacked sequentially.

[0063] See Figure 4 In step S202 above, a wet etching process can be used to etch away a portion of the thickness of the shielding dielectric layer 110 covering the two sidewalls of the upper space of the trench 101 along a direction parallel to the surface of the semiconductor substrate 100. This ensures that the thickness of the remaining shielding dielectric layer 110' on the two sidewalls of the upper space of the trench 101 after etching is 10%-50% of the thickness of the shielding dielectric layer 110 before etching. Specifically, the thickness range of the remaining shielding dielectric layer 110' on the two sidewalls of the upper space of the trench 101 after etching is: That is, specifically as well as arrive Any integer or decimal between any two values ​​will not be elaborated here.

[0064] Simultaneously, in this wet etching process, along a direction perpendicular to the surface of the semiconductor substrate 100, a portion of the shielding dielectric layer 110 on both sides of the shielding gate polysilicon 120 located in the lower space of the trench 101 is removed to expose the shielding gate polysilicon 120 with a height of a first height a and a right angle or acute angle at the top.

[0065] As an example, in order to distinguish the different thicknesses and depths of the shielding dielectric layer in different parts during the wet etching process in step S202 above, in this embodiment of the invention, the shielding dielectric layer that remains after etching along the direction perpendicular to the surface of the semiconductor substrate 100, located on both sides of the shielding gate polysilicon 120 with its top surface lower than the top surface of the shielding gate polysilicon 120, is defined as shielding dielectric layer 110.

[0066] See Figure 5 In step S203 above, a wet etching process or a thinning process can be used to perform a corner-reducing treatment on the exposed top corner of the shielding gate polysilicon 120, which has a right angle or an acute angle, so that the top corner of the exposed shielding gate polysilicon 120 is changed from a right angle or an acute angle to a rounded corner.

[0067] As an example, the embodiments provided in this invention... Figure 4 , Figure 5 In this embodiment, the top corner is exemplarily set to a right angle, while in other embodiments, the top corner may also be set to an acute angle. This example will not be repeated in this embodiment of the invention.

[0068] Continue reading Figure 5After performing corner-removal treatment on the exposed top corner of the shielding gate polysilicon 120, which has a right angle (or acute angle) in step S203, the method for forming the inter-gate oxide layer provided in this embodiment of the invention may further include:

[0069] Step S203.1, along a direction perpendicular to the surface of the semiconductor substrate 100, the height of the shielding gate polysilicon 120 is reduced from a first height a to a second height b, where a>b, and the ratio of b to a is 30%-90%.

[0070] In other embodiments, before performing corner-reducing treatment on the exposed top corner of the shielding gate polysilicon 120, which has a right angle (or acute angle) in step S203, the height of the shielding gate polysilicon 120 can be reduced from a first height a to a second height b along a direction perpendicular to the surface of the semiconductor substrate 100, where a>b, and the ratio of b to a is 30%-90%.

[0071] Obviously, in the method for forming the inter-gate oxide layer provided in the embodiments of the present invention, after or before the corner of the top corner of the shielding gate polysilicon 120 of the first height a is eliminated, the first height a of the shielding gate polysilicon 120 can be thinned, thereby reducing the height of the shielding gate polysilicon 120 exposed for thermal oxidation into the inter-gate oxide layer. That is, by reducing the height of the exposed shielding gate polysilicon 120, the diffusion distance of oxygen atoms (oxygen) in the subsequent oxidation process is further reduced, thereby ensuring that the shielding gate polysilicon 120' exposed after corner elimination can be fully (completely) oxidized, and thus completely transformed into the inter-gate oxide layer.

[0072] See Figure 6 After step S203.1 above, which thins (reduces) the height of the shielding gate polysilicon 120 from the first height a to the second height b, the method for forming the inter-gate oxide layer provided in this embodiment of the invention may further include:

[0073] In step S203.2, P-type or N-type ion implantation is performed on the shielding gate polysilicon 120 with rounded top corners along the depth direction of the trench 101 to dope the shielding gate polysilicon 120, making the shielding polysilicon 120 easier to oxidize.

[0074] See Figure 7 After performing the P-type or N-type ion implantation in step S203.2 above, the method for forming the inter-gate oxide layer provided in this embodiment of the invention may further include:

[0075] Step S203.3, wet etching is used to remove the remaining shielding dielectric layer 110' covering the sidewall of the upper space of the trench 101, so as to expose the semiconductor substrate 100 corresponding to the sidewall of the upper space of the trench 101.

[0076] See Figure 8 In step S204 above, the semiconductor substrate 100 is subjected to a thermal oxidation process to oxidize the shielding gate polysilicon 120 with a preset height and rounded corners to silicon dioxide, and the silicon dioxide is used as the inter-gate oxide layer 130, and the remaining unoxidized shielding gate polysilicon 120 located below the silicon dioxide is used as the shielding gate 140.

[0077] In this embodiment, it is preferred that the preset height of the exposed, rounded-corner shielding gate polysilicon 120 oxidized to silicon dioxide is the same as the second height b. However, in other embodiments, it can be set according to actual design requirements (see C for details). GP The preset height is fixed by parameters such as Qg and Qgs.

[0078] It is understood that in step S204, when the semiconductor substrate 100 is thermally oxidized to oxidize the shielding gate polysilicon 120 at a preset height (second height b) with a rounded angle to silicon dioxide, the semiconductor substrate 100 exposed on the sidewall of the upper space of the trench 101 is also oxidized to form the gate oxide layer 150 of the shielding gate trench device on the sidewall of the upper space of the trench 101.

[0079] See Figure 9 After the gate oxide layer 130 and the gate oxide layer 150 are formed simultaneously by thermal oxidation in step S204, the method for forming the gate oxide layer provided in this embodiment of the invention may further include: filling the remaining space of the trench 101 with polysilicon to form a polysilicon gate 160 of the shielded gate trench device.

[0080] To demonstrate the beneficial effects of the inter-gate oxide layer formation method provided in the embodiments of the present invention, the practicality and outstanding beneficial effects of the formation method provided in the embodiments of the present invention will be described below by comparing the actual SEM images of the inter-gate oxide layer formation method used in the prior art with those of the inter-gate oxide layer formation method provided in the embodiments of the present invention.

[0081] See Figures 10-13 ,in, Figure 10 and Figure 11These are SEM images and magnified views of the inter-gate oxide layer formed using existing inter-gate oxide layer formation methods. Figure 12 and Figure 13 This is to utilize Figure 2 The image shown is a SEM image and a magnified view of the inter-gate oxide layer formed in multiple trenches by the inter-gate oxide layer formation method provided in one embodiment of the present invention.

[0082] Depend on Figure 10 and Figure 11 It is known that in the prior art, there is a certain spatial height difference between the lower shielding gate and the upper polysilicon gate formed in the trench, which leads to the inter-gate oxide layer filling the space between them being connected to the C-shaped structure of the two gates. GP The losses are relatively large, meaning that the switching losses in the switching process are relatively large when using shielded trench type devices formed by existing technology.

[0083] According to Figure 12 and Figure 13 It is evident that the structure formed by the method for forming the inter-gate oxide layer provided in the embodiments of the present invention comprises a polysilicon gate, an inter-gate oxide layer, and a shielding gate, forming the C... GP The switching losses of the device are significantly reduced, thus achieving the goal of effectively reducing the switching losses of the device.

[0084] See Figure 14 Based on the method for forming the inter-gate oxide layer as described above, the present invention also provides a method for forming a shielded gate trench device, comprising:

[0085] Step S1401: Using the method for forming an inter-gate oxide layer as described above, a shielding dielectric layer, a shielding gate, and an inter-gate oxide layer located on the top surface of the shielding gate are formed in a trench in a semiconductor substrate.

[0086] Step S1402: Polysilicon is filled into the upper space of the trench to form a polysilicon gate. The polysilicon gate is isolated from the semiconductor substrate by the gate oxide layer on the sidewall of the trench and from the shielding gate by the inter-gate oxide layer.

[0087] Furthermore, the step of forming trenches within the semiconductor substrate includes:

[0088] A semiconductor substrate is provided, and a hard mask layer is formed on the surface of the semiconductor substrate;

[0089] Using the hard mask layer as a mask, the semiconductor substrate is etched to form at least one of the trenches.

[0090] As an example, the hard mask layer may specifically be a first oxide layer and / or a second oxide layer stacked sequentially, or the hard mask layer may specifically be an ONO stack structure composed of a first oxide layer, a nitride layer and a second oxide layer stacked sequentially.

[0091] In summary, in the method for forming an inter-gate oxide layer provided by the present invention, a shielding medium is first formed on the inner surface of a semiconductor substrate, and a trench filled with shielding polysilicon is formed in the lower space of the trench. Then, using a wet etching process, a portion of the shielding medium layer on both sides of the shielding gate polysilicon in the lower space of the trench is removed along a direction perpendicular to the surface of the semiconductor substrate to expose the shielding gate polysilicon with a height of a first height and a right angle or acute angle at the top. Then, the exposed shielding gate polysilicon with a right angle or acute angle at the top is subjected to a corner-reducing process to change the top corner of the exposed shielding gate polysilicon from the right angle or acute angle to a rounded corner. After that, a thermal oxidation process is performed on the semiconductor substrate to oxidize the exposed shielding gate polysilicon with a rounded corner at a predetermined height into silicon dioxide, and the silicon dioxide is used as the inter-gate oxide layer.

[0092] The method for forming the inter-gate oxide layer provided by this invention, after forming a shielding gate polysilicon with a first height using an etching process, does not directly perform an oxidation process to form the inter-gate oxide layer as in existing technologies. Instead, it first reduces the top corner of the shielding gate polysilicon of the first height from a right angle or acute angle to a rounded corner on both sides. Then, it performs an oxidation process to reduce the diffusion distance of oxygen atoms (oxygen) during subsequent oxidation by reducing the exposed top corner of the shielding gate polysilicon. This ensures that the exposed shielding gate polysilicon after corner reduction can be fully (completely) oxidized, thus converting it entirely into the inter-gate oxide layer. In other words, it ultimately reduces the C-value of the polysilicon gate, inter-gate oxide layer, and shielding gate. GP And to reduce the switching losses of the devices.

[0093] Furthermore, in the forming method provided by the present invention, after or before the corner of the first height of the shielding gate polysilicon is eliminated, the first height of the shielding gate polysilicon can be thinned, thereby reducing the height of the exposed shielding gate polysilicon for thermal oxidation into the inter-gate oxide layer. That is, by reducing the height of the exposed shielding gate polysilicon, the diffusion distance of oxygen atoms (oxygen) in the subsequent oxidation process is further reduced, thereby ensuring that the shielding gate polysilicon exposed after corner elimination can be fully (completely) oxidized, and thus completely transformed into the inter-gate oxide layer.

[0094] Meanwhile, due to the formation method provided by the present invention, the thickness of the shielding medium layer covering the sidewall of the upper space of the trench is reduced. Then, an ion implantation process is performed on the shielding gate polysilicon and the shielding medium layers on both sides of the lower space of the trench after the corner reduction and / or thinning treatment. This achieves the purpose of increasing the ion implantation dose and improving the ion implantation uniformity in the shielding gate polysilicon after the corner reduction and / or thinning treatment.

[0095] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0096] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0097] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and not to limit the scope of the invention. It must be noted that the singular forms “a” and “an” used herein and in the appended claims include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for forming an inter-gate oxide layer, characterized in that, It should include at least the following steps: A semiconductor substrate is provided, wherein at least one trench is formed in the semiconductor substrate, a shielding dielectric layer is covered on the inner surface of the trench, and a shielding gate polysilicon is filled in the lower space of the trench. The shielding dielectric layer is wet-etched, removing at least a portion of the shielding dielectric layer along a direction perpendicular to the surface of the semiconductor substrate, to expose the shielding gate polysilicon with a first height and a right angle or acute angle at the top corner. The exposed top corners of the shielding gate polysilicon, which are either right angles or acute angles, are subjected to corner-reduction treatment so that the top corners of the exposed shielding gate polysilicon are transformed from right angles or acute angles into rounded corners; The semiconductor substrate is subjected to a thermal oxidation process to oxidize the shielding gate polysilicon with a preset height and rounded corners to silicon dioxide, and the silicon dioxide is used as the inter-gate oxide layer, and the remaining unoxidized shielding gate polysilicon located below the silicon dioxide is used as the shielding gate. The method further includes, before or after performing corner-removing treatment on the exposed shielding gate polysilicon with right or acute angles at its top corners, the formation of which involves: thinning the height of the shielding gate polysilicon from a first height to a second height along a direction perpendicular to the surface of the semiconductor substrate; and, in the step of wet etching the shielding dielectric layer, at least in the step of removing a portion of the height of the shielding dielectric layer on both sides of the shielding gate polysilicon along a direction perpendicular to the surface of the semiconductor substrate, simultaneously etching away a portion of the thickness of the shielding dielectric layer covering the sidewalls of the upper space of the trench along a direction parallel to the surface of the semiconductor substrate; and performing corner-removing treatment on the exposed shielding gate polysilicon with right or acute angles at its top corners. Subsequently, the formation method further includes: performing P-type or N-type ion implantation on the shielding gate polysilicon along the depth direction of the trench; after the P-type or N-type ion implantation, the formation method further includes: wet etching to remove the remaining shielding dielectric layer covering the sidewalls of the upper space of the trench, so as to expose the semiconductor substrate corresponding to the sidewalls of the upper space of the trench; in the step of performing a thermal oxidation process on the semiconductor substrate to oxidize the exposed shielding gate polysilicon with a preset height and rounded corners into silicon dioxide, the semiconductor substrate exposed by the sidewalls of the upper space of the trench is also oxidized simultaneously to form a gate oxide layer of the shielding gate trench device on the sidewalls of the upper space of the trench.

2. The method for forming the inter-gate oxide layer as described in claim 1, characterized in that, The ratio of the second height to the first height is 30% to 90%.

3. The method for forming the inter-gate oxide layer as described in claim 1, characterized in that, The thickness of the shielding medium layer covering the inner surface of the trench ranges from 800 Å to 8000 Å.

4. The method for forming the inter-gate oxide layer as described in claim 3, characterized in that, After etching away a portion of the shielding dielectric layer covering the sidewalls of the upper space of the trench along a direction parallel to the surface of the semiconductor substrate, the remaining thickness of the shielding dielectric layer on the sidewalls of the upper space of the trench ranges from 500 Å to 5000 Å.

5. The method for forming an inter-gate oxide layer as described in claim 1, characterized in that, The material of the shielding dielectric layer includes silicon dioxide.

6. The method for forming an inter-gate oxide layer as described in claim 2, characterized in that, In the thermal oxidation process, the shielding gate polysilicon with rounded exposed angles is oxidized to silicon dioxide at a preset height that is the same as the second height.

7. A method for forming a shielded trench type device, characterized in that, include: Using the method for forming an inter-gate oxide layer according to any one of claims 1 to 6, a shielding dielectric layer, a shielding gate, and an inter-gate oxide layer located on the top surface of the shielding gate are formed in a trench within a semiconductor substrate; Polysilicon is filled in the upper space of the trench to form a polysilicon gate. The polysilicon gate is isolated from the semiconductor substrate by a gate oxide layer on the sidewall of the trench and from the shielding gate by an inter-gate oxide layer.

8. The method for forming a shielded trench type device as described in claim 7, characterized in that, The step of forming trenches in the semiconductor substrate includes: A semiconductor substrate is provided, and a hard mask layer is formed on the surface of the semiconductor substrate; Using the hard mask layer as a mask, the semiconductor substrate is etched to form at least one of the trenches.

9. The method for forming a shielded trench type device as described in claim 8, characterized in that, The hard mask layer comprises a first oxide layer and / or a second oxide layer stacked sequentially, or the hard mask layer comprises an ONO stack structure consisting of a first oxide layer, a nitride layer and a second oxide layer stacked sequentially.

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