A high-frequency high-speed semiconductor device structure and a method for manufacturing the same

Abstract

This invention provides a high-frequency, high-speed semiconductor device structure and its fabrication method. The method includes: a first conductive layer and a second conductive layer wrapping the upper and lower surfaces of a dielectric layer to form a core plate; the dielectric layer has a loss factor of less than 0.01 and a dielectric constant of less than 3.5; a laminated bonding sheet contacts the dielectric layer through a patterned third conductive layer; a fifth conductive layer forms an electrical connection with the third conductive layer through the patterned laminated bonding sheet; a patterned solder resist layer contacts the laminated bonding sheet through the patterned fifth conductive layer; and a surface protective layer covers the exposed fifth conductive layer. This invention reduces signal transmission loss in the high-frequency, high-speed semiconductor device structure by using a low-roughness conductive layer, a low-loss-factor dielectric layer, and a solder resist layer; simultaneously, it utilizes low-amount etching solutions in dry film pretreatment and lamination pretreatment to etch the conductive layer, further reducing signal transmission loss in the high-frequency, high-speed semiconductor device structure; additionally, a thin nickel layer is provided as a surface protective layer to further reduce signal transmission loss.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a high-frequency, high-speed semiconductor device structure and its fabrication method. Background Technology

[0002] With industrial upgrading and the continuous advancement of human science and technology, the development of 5G, the Internet of Things, and autonomous driving technologies relies on the transmission of high-frequency, high-speed signals, placing higher demands on signal edge rates and clock rates of digital systems. Currently, electronic system designs generally use high-frequency signals, requiring PCB (Printed Circuit Board) systems and IC (Integrated Circuit) packaging substrates to achieve high-performance system architectures. This leads to the emergence of signal integrity issues such as reflection and crosstalk. Signal integrity refers to the quality of signal transmission from the transmitter to the receiver. The faster the transmission rate, the more severe the signal loss. Reducing signal loss during transmission to ensure signal integrity is a significant challenge in the development of high-frequency, high-speed PCBs and IC packaging substrates.

[0003] Key indicators of signal integrity for high-frequency, high-speed PCBs and IC packaging substrates include transmission line loss, impedance matching, and delay consistency. Transmission line loss can be further divided into dielectric loss, conductor loss, and radiation loss. Dielectric loss mainly depends on the glass fiber and resin of the PCB and IC packaging substrate, while conductor loss is primarily affected by the skin effect and conductor surface roughness. 5G products require higher transmission rates, and signal transmission is increasingly concentrated on the surface of the conductors. Signal transmission over areas with high surface roughness will result in increasingly severe standing waves and reflections, leading to longer signal transmission paths and increased losses.

[0004] Currently, there is an urgent need for a high-frequency, high-speed semiconductor device structure and its fabrication method to reduce signal transmission loss and effectively reduce signal loss during transmission.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a high-frequency, high-speed semiconductor device structure and its fabrication method, so as to solve the problem of high transmission loss in printed circuit boards and IC packaging substrates for high-frequency, high-speed signal transmission in the prior art.

[0007] To achieve the above objectives, the present invention provides a method for fabricating a high-frequency, high-speed semiconductor device structure. The method includes: providing a core plate, wherein the core plate comprises, from bottom to top, a first conductive layer, a dielectric layer, and a second conductive layer, wherein the loss factor of the dielectric layer is less than 0.01, and the dielectric constant of the dielectric layer is less than 3.5.

[0008] A first slot is provided in the core plate, and the first slot passes through the core plate;

[0009] A third conductive layer is disposed in the first hole groove to fill it, and the third conductive layer covers the exposed surface of the core board.

[0010] The second conductive layer and the third conductive layer located above the core board are patterned to expose a portion of the upper surface of the dielectric layer; the first conductive layer and the third conductive layer located below the core board are patterned to expose a portion of the lower surface of the dielectric layer.

[0011] A laminated adhesive sheet is disposed on the third conductive layer. The laminated adhesive sheet fills the patterned first conductive layer, second conductive layer and third conductive layer and covers the surface of the third conductive layer so that the laminated adhesive sheet contacts the exposed surface of the dielectric layer; a fourth conductive layer is disposed on the laminated adhesive sheet.

[0012] A second slot is provided, which penetrates the laminated adhesive sheet and the fourth conductive layer, exposing a portion of the third conductive layer;

[0013] A fifth conductive layer is disposed on the fourth conductive layer, the fifth conductive layer filling the second hole and covering the surface of the fourth conductive layer;

[0014] The fourth and fifth conductive layers above the laminated adhesive sheet are patterned to expose portions of the upper and lower surfaces of the laminated adhesive sheet.

[0015] A patterned solder mask layer is provided on the fifth conductive layer, and the fifth conductive layer exposed by the patterned solder mask layer is a solder pad;

[0016] Configure a graphical surface protector layer such that the surface protector layer only covers the surface of the pads.

[0017] Optionally, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and / or the fifth conductive layer are copper foils, and the roughness of the copper foils is less than 2 micrometers.

[0018] Optionally, the loss factor of the laminated adhesive sheet is less than 0.01 and the dielectric constant is less than 3.5; and / or the loss factor of the solder resist layer is less than 0.01 and the dielectric constant is less than 3.5.

[0019] Optionally, after the third conductive layer is formed, a dry film pretreatment is performed on the third conductive layer. The dry film pretreatment uses a low micro-etching solution, and the micro-etching amount of the dry film pretreatment on the third conductive layer is 0.1 micrometers to 1.0 micrometers.

[0020] Optionally, before setting the laminated adhesive sheet, the third conductive layer is subjected to a pre-lamination treatment. The pre-lamination treatment uses a low micro-etching solution, and the micro-etching amount of the third conductive layer in the pre-lamination treatment is 0.1 micrometers to 1.0 micrometers.

[0021] Optionally, after the fourth conductive layer is formed, a dry film pretreatment is performed on the fourth conductive layer. The dry film pretreatment uses a low micro-etching solution, and the micro-etching amount of the dry film pretreatment on the fourth conductive layer is 0.1 micrometers to 1.0 micrometers.

[0022] Optionally, before setting the solder resist layer, the fifth conductive layer is subjected to a solder resist pretreatment. The solder resist pretreatment uses a low micro-etching solution, and the micro-etching amount of the fifth conductive layer in the solder resist pretreatment is 0.1 micrometers to 1.0 micrometers.

[0023] Optionally, before setting the solder resist layer, the laminated adhesive sheet, the fourth conductive layer, the fifth conductive layer and the second hole groove and patterning between them are repeatedly set to form a laminated stack structure.

[0024] Optionally, the surface protective layer includes a nickel layer with a thickness of less than 3 micrometers.

[0025] The present invention also provides a high-frequency, high-speed semiconductor device structure, which is obtained by any of the above-described fabrication methods.

[0026] As described above, the high-frequency, high-speed semiconductor device structure and its fabrication method of the present invention have the following beneficial effects:

[0027] This invention reduces the transmission loss of the core board, laminated adhesive sheet, and solder resist layer to the high-frequency and high-speed semiconductor device structure by using a low-roughness conductive layer, a low-loss factor dielectric layer, and a solder resist layer.

[0028] This invention utilizes low-volume etching solutions for dry film pretreatment and lamination pretreatment to etch the conductive layer with a low-volume amount, thereby reducing signal transmission loss in high-frequency and high-speed semiconductor device structures.

[0029] This invention uses a thin nickel layer as a surface protective layer to reduce signal transmission loss. Attached Figure Description

[0030] Figure 1 The diagram shown is a schematic representation of the core board provided in step 1 of the fabrication method for the high-frequency, high-speed semiconductor device structure of the present invention.

[0031] Figure 2 The diagram shows the structure of the first slot formed in step 2 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0032] Figure 3 The diagram shown is a schematic representation of the structure presented in step 3 of the optional example of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting the first pre-plating layer.

[0033] Figure 4 The diagram shown is a schematic representation of the structure presented in step 3 of the optional example of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting the first electroplating layer.

[0034] Figure 5 The diagram shown is a schematic representation of the structure after pretreatment of the third conductive layer dry film in an optional example of step 3 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0035] Figure 6 The diagram shown is a schematic representation of the structure presented in step 4 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, where a first resist layer is set.

[0036] Figure 7 The diagram shown is a schematic representation of the structure after the first resist layer is graphically patterned, which is an optional example of step 4 in the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0037] Figure 8 The diagram shown is a schematic representation of the structure after graphically representing the first conductive layer, the second conductive layer, and the third conductive layer in step 4 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0038] Figure 9 The diagram shown is a schematic representation of the structure after removing the first resist layer in step 4 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0039] Figure 10 The diagram shows the structure of the laminated adhesive sheet and the fourth conductive layer in step 5 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0040] Figure 11 The diagram shows the structure of the second slot formed in step 6 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0041] Figure 12The diagram shows a schematic representation of the structure presented in step 7 of the optional example of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting a second pre-plating layer.

[0042] Figure 13 The diagram shown is a schematic representation of the structure presented in step 7 of the optional example of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting a second electroplating layer.

[0043] Figure 14 The diagram shows a schematic representation of the structure presented in step 8 of the optional example of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting a second resist layer.

[0044] Figure 15 The diagram shown is a schematic representation of the structure of the second resist layer in step 8 of the method for fabricating the high-frequency, high-speed semiconductor device structure of the present invention.

[0045] Figure 16 The diagram shown is a schematic representation of the structure of the fifth and fourth conductive layers in step 8 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0046] Figure 17 The diagram shown is a schematic representation of the structure after removing the second resist layer in step 8 of the fabrication method for the high-frequency, high-speed semiconductor device structure of the present invention.

[0047] Figure 18 The diagram shown is a schematic representation of the structure formed in step 9 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention, which involves setting a solder resist layer.

[0048] Figure 19 The diagram shows the structure of the surface protective layer in step 10 of the fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention.

[0049] Component designation explanation

[0050] 11. First conductive layer; 12. Second conductive layer; 2. Dielectric layer; 3. First cavity; 4. First pre-plating layer; 5. First electroplating layer; 6. First anti-corrosion layer; 7. Laminated adhesive sheet; 8. Fourth conductive layer; 9. Second cavity; 100. Second pre-plating layer; 101. Second electroplating layer; 102. Second anti-corrosion layer; 103. Solder resist layer; 104. Surface protective layer. Detailed Implementation

[0051] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0052] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0053] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0054] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Example 1:

[0057] This invention provides a method for fabricating a high-frequency, high-speed semiconductor device structure, the method comprising:

[0058] Step 1: Provide a core board, which includes a first conductive layer 11, a dielectric layer 2 and a second conductive layer 12 from bottom to top. The loss factor of the dielectric layer 2 is less than 0.01 and the dielectric constant of the dielectric layer 2 is less than 3.5.

[0059] Step 2: A first slot 3 is provided in the core board, and the first slot 3 passes through the core board;

[0060] Step 3: A third conductive layer is provided to fill the first hole groove 3, and the third conductive layer covers the exposed surface of the core board;

[0061] Step 4: Pattern the second conductive layer 12 and the third conductive layer located above the core board to expose a portion of the upper surface of the dielectric layer 2; pattern the first conductive layer 11 and the third conductive layer located below the core board to expose a portion of the lower surface of the dielectric layer 2.

[0062] Step 5: A laminated adhesive sheet 7 is disposed on the third conductive layer. The laminated adhesive sheet 7 fills the patterned first conductive layer 11, second conductive layer 12 and third conductive layer and covers the surface of the third conductive layer so that the laminated adhesive sheet 7 contacts the exposed surface of the dielectric layer 2; a fourth conductive layer 8 is disposed on the laminated adhesive sheet 7.

[0063] Step 6: Set a second hole 9, the second hole 9 passing through the laminated adhesive sheet 7 and the fourth conductive layer 8, exposing part of the third conductive layer;

[0064] Step 7: A fifth conductive layer is disposed on the fourth conductive layer 8, the fifth conductive layer filling the second hole 9 and covering the surface of the fourth conductive layer 8;

[0065] Step 8: Pattern the fourth conductive layer 8 and the fifth conductive layer above the laminated adhesive sheet 7 to expose part of the upper and lower surfaces of the laminated adhesive sheet 7;

[0066] Step 9: A patterned solder mask 103 is formed on the fifth conductive layer, and the fifth conductive layer exposed by the patterned solder mask 103 is a solder pad.

[0067] Step 10: Set a graphical surface protector 104 such that the surface protector 104 only covers the surface of the pads.

[0068] The fabrication method of the high-frequency and high-speed semiconductor device structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the fabrication order of the high-frequency and high-speed semiconductor device structure protected by the present invention, and those skilled in the art can make changes according to the actual fabrication steps.

[0069] First, such as Figure 1 As shown, in step 1, a core board is provided. The core board includes a first conductive layer 11, a dielectric layer 2, and a second conductive layer 12 from bottom to top. The loss factor of the dielectric layer 2 is less than 0.01, and the dielectric constant of the dielectric layer 2 is less than 3.5.

[0070] In one embodiment, the loss factor of the dielectric layer 2 is 0.006-0.008, and the dielectric constant of the dielectric layer 2 is 3.45-3.55.

[0071] In one embodiment, the first conductive layer 11 and / or the second conductive layer 12 are copper foils, and the roughness of the copper foils is less than 2 micrometers.

[0072] In one embodiment, the first conductive layer 11 and / or the second conductive layer 12 are copper foils, and the thickness of the copper foils is 1.5 micrometers to 64 micrometers.

[0073] Then, as Figure 2 As shown, in step 2, a first slot 3 is provided in the core board, and the first slot 3 penetrates the core board.

[0074] Next, step 3 is performed, in which a third conductive layer is provided to fill the first hole groove 3, and the third conductive layer covers the exposed surface of the core board.

[0075] In one embodiment, the third conductive layer is a copper foil with a roughness of less than 2 micrometers.

[0076] In one embodiment, the method for fabricating the third conductive layer includes: as follows Figure 3 As shown, a first pre-plating layer 4 is provided on the exposed surface of the core board, and the first pre-plating layer 4 forms a good electrical connection with both the first conductive layer 11 and the second conductive layer 12; as Figure 4 As shown, a first electroplating layer 5 is provided on the surface of the first pre-plating layer 4. The first electroplating layer 5 fills the first hole groove 3 and wraps the first pre-plating layer 4 provided on the surface of the core board. The first pre-plating layer 4 and the first electroplating layer 5 form the third conductive layer.

[0077] In one embodiment, such as Figure 5 As shown, after the third conductive layer is set, a dry film pretreatment is performed on the third conductive layer. The dry film pretreatment uses a low micro-etching solution, and the micro-etching amount of the dry film pretreatment on the third conductive layer is 0.1 micrometers to 1.0 micrometers.

[0078] In one embodiment, the amount of micro-etching of the third conductive layer by the dry film pretreatment is 0.8 micrometers to 1.0 micrometers.

[0079] Specifically, dry film pretreatment is used to enhance the adhesion between the treated layer and the subsequent film lamination process, prevent the subsequently lamination layer from falling off, and avoid affecting the normal operation of subsequent processes or causing the high-frequency and high-speed semiconductor device structure to be scrapped.

[0080] Specifically, before filling the third conductive layer, a desmearing process is performed to reduce surface roughness and improve substrate quality.

[0081] Specifically, the first pre-plating layer 4 can be obtained by chemical copper plating, electroplating copper, etc., and the first electroplating layer 5 can be obtained by electroplating filling, etc.

[0082] Then, in step 4, the second conductive layer 12 and the third conductive layer located above the core board are patterned to expose a portion of the upper surface of the dielectric layer 2; the first conductive layer 11 and the third conductive layer located below the core board are patterned to expose a portion of the lower surface of the dielectric layer 2.

[0083] In one embodiment, a method for patterning the second conductive layer 12 and the third conductive layer above the core board, and the first conductive layer 11 and the third conductive layer below the core board includes: as follows Figure 6 As shown, a first anti-corrosion layer 6 is disposed on the surface of the third conductive layer above and below the core board; as Figure 7 As shown, the first resist layer 6 is graphically illustrated, exposing a portion of the third conductive layer; as Figure 8 As shown, the first conductive layer 11, the second conductive layer 12, and the third conductive layer are further patterned along the exposed third conductive layer; as... Figure 9 As shown, the first anti-corrosion layer 6 is removed.

[0084] In one embodiment, the method of patterning the first resist layer 6 includes exposing and developing or etching the first resist layer 6.

[0085] Next, proceed to step 5, as follows: Figure 10 As shown, a laminated adhesive sheet 7 is disposed on the third conductive layer. The laminated adhesive sheet 7 fills the patterned first conductive layer 11, second conductive layer 12 and third conductive layer and covers the surface of the third conductive layer so that the laminated adhesive sheet 7 contacts the exposed surface of the dielectric layer 2; a fourth conductive layer 8 is disposed on the laminated adhesive sheet 7.

[0086] In one embodiment, the fourth conductive layer 8 is a copper foil with a roughness of less than 2 micrometers.

[0087] In one embodiment, the loss factor of the laminated adhesive sheet 7 is less than 0.01 and the dielectric constant is less than 3.5.

[0088] In one embodiment, the loss factor of the laminated adhesive sheet 7 is 0.006-0.008, and the dielectric constant is 3.45-3.55.

[0089] This invention reduces signal transmission loss in multilayer printed circuit boards and integrated circuit carriers caused by the inherent properties of materials by setting the loss factor and dielectric constant of the dielectric material of the dielectric layer 2 and the laminated adhesive sheet 7 in the high-frequency and high-speed semiconductor device structure.

[0090] In one embodiment, such as Figure 10 As shown, before setting the laminated adhesive sheet 7, the third conductive layer is subjected to a pre-lamination treatment. The pre-lamination treatment uses a low micro-etching solution, and the micro-etching amount of the pre-lamination treatment on the third conductive layer is 0.1 micrometers to 1.0 micrometers.

[0091] In one embodiment, the amount of micro-etching of the third conductive layer during the pre-lamination treatment is 0.8 micrometers to 1.0 micrometers.

[0092] In one embodiment, the laminated adhesive sheet 7 and the dielectric layer 2 are made of one or more of epoxy resin, polyimide, polymaleimide triazine resin, polyphenylene ether, polytetrafluoroethylene, FR-4 or FR-5, in any combination.

[0093] In one embodiment, an organic bonding layer is provided between the fourth conductive layer 8 and the laminated adhesive sheet 7 to improve the bonding strength between the fourth conductive layer 8 and the laminated adhesive sheet 7, thereby reducing signal leakage and improving the electrical performance of the product.

[0094] Specifically, after the fourth conductive layer 8 is set, a desmearing process is performed to reduce surface roughness and improve substrate quality.

[0095] Specifically, the fourth conductive layer 8 can be obtained by chemical copper plating, electroplating copper, or other methods.

[0096] Then, proceed to step 6, as follows: Figure 11 As shown, a second hole 9 is provided, which penetrates the laminated adhesive sheet 7 and the fourth conductive layer 8, exposing a portion of the third conductive layer.

[0097] In one embodiment, before setting the second hole 9, the fourth conductive layer 8 is subjected to a dry film pretreatment. The dry film pretreatment uses a low micro-etching solution, and the micro-etching amount of the dry film pretreatment on the fourth conductive layer 8 is 0.1 micrometers to 1.0 micrometers.

[0098] Next, step 7 is performed, in which a fifth conductive layer is disposed on the fourth conductive layer 8, the fifth conductive layer filling the second hole 9 and covering the surface of the fourth conductive layer 8.

[0099] In one embodiment, the fifth conductive layer is a copper foil with a roughness of less than 2 micrometers.

[0100] This invention reduces signal transmission loss in multilayer printed circuit boards and integrated circuit carriers caused by the skin effect by using conductive layers with low roughness.

[0101] In one embodiment, the first conductive layer 11, the second conductive layer 12, the fourth conductive layer 8 and / or the fifth conductive layer are one of rolled copper foil, electrolytic copper foil, reverse copper foil or carrier copper foil.

[0102] In one embodiment, the method for fabricating the fifth conductive layer includes: as follows Figure 12 As shown, a second pre-plating layer 100 is formed on the surface of the fourth conductive layer 8, the second pre-plating layer 100 covers the surface of the second hole 9, and the second pre-plating layer 100 forms a good electrical connection with the third conductive layer exposed by the second hole 9; as Figure 13 As shown, a second electroplating layer 101 is provided on the surface of the second pre-plating layer 100. The second electroplating layer 101 fills the second hole groove 9 and covers the exposed surface of the fourth conductive layer 8. The second pre-plating layer 100 and the second electroplating layer 101 constitute the fifth conductive layer.

[0103] Then, step 8 is performed to pattern the fourth conductive layer 8 and the fifth conductive layer above the laminated adhesive sheet 7 to expose part of the upper and lower surfaces of the laminated adhesive sheet 7.

[0104] In one embodiment, the method for fabricating the fourth conductive layer 8 and the fifth conductive layer includes: as follows Figure 14 As shown, a second resist layer 102 is provided on the surface of the fifth conductive layer; as Figure 15 As shown, the second resist layer 102 is graphically illustrated, exposing a portion of the fifth conductive layer; as Figure 16 As shown, the fifth conductive layer and the fourth conductive layer 8 are further patterned along the exposed fifth conductive layer to expose a portion of the surface of the laminated adhesive sheet 7; as Figure 17 As shown, the remaining second anti-corrosion layer 102 is removed.

[0105] In one embodiment, the method of patterning the second resist layer 102 includes exposing and developing or etching the second resist layer 102.

[0106] Next, proceed to step 9, as follows: Figure 18 As shown, a patterned solder mask 103 is provided on the fifth conductive layer, and the fifth conductive layer exposed by the patterned solder mask 103 is a solder pad.

[0107] In one embodiment, the loss factor of the solder mask layer 103 is less than 0.01 and the dielectric constant is less than 3.5.

[0108] In one embodiment, the loss factor of the solder mask layer 103 is 0.006-0.008, and the dielectric constant is 3.45-3.55.

[0109] The present invention further reduces signal transmission loss in high-frequency and high-speed semiconductor device structures by setting a low-loss solder mask layer 103.

[0110] In one embodiment, before setting the solder resist layer 103, the fifth conductive layer is subjected to a solder resist pretreatment. The solder resist pretreatment uses a low micro-etching solution, and the micro-etching amount of the solder resist pretreatment on the fifth conductive layer is 0.1 micrometers to 1.0 micrometers.

[0111] In high-frequency, high-speed circuits, a large surface roughness of the conductive layer leads to higher signal loss, thus failing to meet the requirements of high-frequency, high-speed signal transmission. This invention reduces the impact of the etching solution on the surface roughness of the treated layer by using a low-volume etching solution for dry film pretreatment, lamination pretreatment, and solder resist pretreatment, thereby reducing signal transmission loss in multilayer printed circuit boards and integrated circuit substrates caused by the skin effect.

[0112] In one embodiment, before setting the solder mask layer 103, the laminated adhesive sheet 7, the fourth conductive layer 8, the fifth conductive layer and the second hole groove 9 between them are repeatedly set and patterned to form a laminated stack structure.

[0113] Finally, proceed to step 10, as follows: Figure 19 As shown, a graphical surface protection layer 104 is provided so that the surface protection layer 104 only covers the surface of the pad.

[0114] In one embodiment, the surface protective layer 104 includes a nickel layer with a thickness of less than 3 micrometers.

[0115] In one embodiment, the surface protective layer 104 is obtained from a nickel-palladium-gold material, which is a conventional plating material composed of a compound of three metals: nickel, palladium, and gold. It has excellent corrosion resistance and can work in harsh environments, thus protecting the product surface and maintaining its solderability.

[0116] This invention achieves a thinner nickel layer by using a special nickel-palladium-gold solution, thereby reducing the skin effect and helping to reduce signal transmission loss in multilayer printed circuit boards and integrated circuit substrates.

[0117] In one embodiment, in the nickel-palladium-gold material, the thickness of the nickel layer is 2 micrometers to 2.5 micrometers, the thickness of the palladium layer is 0.1 micrometers to 0.2 micrometers, and the thickness of the gold layer is 0.03 micrometers to 0.05 micrometers.

[0118] Specifically, this invention uses a subtractive process to manufacture printed circuit boards, but the same method is also applicable to additive and semi-additive processing techniques.

[0119] The present invention also provides a high-frequency, high-speed semiconductor device structure, wherein the high-frequency, high-speed semiconductor device structure is obtained by any of the above-described methods for fabricating high-frequency, high-speed semiconductor devices.

[0120] In the prior art, the insertion loss of printed circuit boards and IC packaging substrates at a frequency of 30GHz is -1.67dB / inch. However, when the technical solution of the present invention is adopted, the insertion loss is -1.44dB / inch, which is 13.8% better. It can be seen that the present invention has a significant effect on reducing the insertion loss in high-frequency and high-speed semiconductor device structures and can significantly reduce signal transmission loss.

[0121] In summary, the high-frequency and high-speed semiconductor device structure and its fabrication method of the present invention can reduce the transmission loss of the core board, laminated adhesive sheet and solder resist layer to the high-frequency and high-speed semiconductor device structure through the low-roughness conductive layer, low-loss factor dielectric layer and solder resist layer; at the same time, the low-amount etching solution of dry film pretreatment and lamination pretreatment is used to etch the conductive layer to reduce the signal transmission loss of the high-frequency and high-speed semiconductor device structure; in addition, a thin nickel layer is set as a surface protective layer to reduce signal transmission loss.

[0122] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0123] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a high-frequency, high-speed semiconductor device structure, characterized in that, The preparation method includes: A core board is provided, wherein the core board comprises, from bottom to top, a first conductive layer, a dielectric layer and a second conductive layer, wherein the loss factor of the dielectric layer is less than 0.01 and the dielectric constant of the dielectric layer is less than 3.5; A first slot is provided in the core plate, and the first slot passes through the core plate; A third conductive layer is disposed in the first hole groove to fill it, and the third conductive layer covers the exposed surface of the core board. The second conductive layer and the third conductive layer located above the core board are patterned to expose a portion of the upper surface of the dielectric layer; the first conductive layer and the third conductive layer located below the core board are patterned to expose a portion of the lower surface of the dielectric layer. A laminated adhesive sheet is disposed on the third conductive layer. The laminated adhesive sheet fills the patterned first conductive layer, second conductive layer and third conductive layer and covers the surface of the third conductive layer so that the laminated adhesive sheet contacts the exposed surface of the dielectric layer; a fourth conductive layer is disposed on the laminated adhesive sheet. A second slot is provided, which penetrates the laminated adhesive sheet and the fourth conductive layer, exposing a portion of the third conductive layer; A fifth conductive layer is disposed on the fourth conductive layer, the fifth conductive layer filling the second hole and covering the surface of the fourth conductive layer; The fourth and fifth conductive layers above the laminated adhesive sheet are patterned to expose portions of the upper and lower surfaces of the laminated adhesive sheet. A patterned solder mask layer is provided on the fifth conductive layer, and the fifth conductive layer exposed by the patterned solder mask layer is a solder pad; Configure a graphical surface protector layer such that the surface protector layer only covers the surface of the pads.

2. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and / or the fifth conductive layer are copper foils, and the roughness of the copper foils is less than 2 micrometers.

3. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The loss factor of the laminated adhesive sheet is less than 0.01 and the dielectric constant is less than 3.5; and / or the loss factor of the solder resist layer is less than 0.01 and the dielectric constant is less than 3.

5.

4. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: after setting the third conductive layer, performing a dry film pretreatment on the third conductive layer, wherein a low micro-etching solution is used for the dry film pretreatment, and the micro-etching amount of the dry film pretreatment on the third conductive layer is 0.1 micrometers to 1.0 micrometers.

5. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: before setting the laminated adhesive sheet, performing a pre-lamination treatment on the third conductive layer, wherein the pre-lamination treatment uses a low micro-etching solution, and the micro-etching amount of the pre-lamination treatment on the third conductive layer is 0.1 micrometers to 1.0 micrometers.

6. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: after setting the fourth conductive layer, performing a dry film pretreatment on the fourth conductive layer, wherein a low micro-etching solution is used for the dry film pretreatment, and the micro-etching amount of the dry film pretreatment on the fourth conductive layer is 0.1 micrometers to 1.0 micrometers.

7. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: before setting the solder resist layer, performing a solder resist pretreatment on the fifth conductive layer, wherein the solder resist pretreatment uses a low micro-etching solution, and the micro-etching amount of the solder resist pretreatment on the fifth conductive layer is 0.1 micrometers to 1.0 micrometers.

8. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The preparation method further includes: before setting the solder resist layer, repeatedly setting the laminated adhesive sheet, the fourth conductive layer, the fifth conductive layer and the second hole groove and patterning between them to form a laminated stack structure.

9. The method for fabricating the high-frequency, high-speed semiconductor device structure according to claim 1, characterized in that, The surface protective layer includes a nickel layer with a thickness of less than 3 micrometers.

10. A high-frequency, high-speed semiconductor device structure, characterized in that, The high-frequency, high-speed semiconductor device structure is obtained by the preparation method described in any one of claims 1-9.

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