Pvd masking method for n-type photovoltaic cells

Abstract

This invention discloses a PVD masking method for N-type photovoltaic cells. In the fabrication of HJT solar cells, after preparing an N / P-type doped amorphous silicon layer, a sodium chloride layer is first coated onto the side of the silicon wafer. Then, a TCO thin film is deposited using a top-down PVD magnetron sputtering process, followed by washing away the sodium chloride layer with water. In the fabrication of TOPCON solar cells, after preparing a PN junction, a sodium chloride layer is first coated onto the side of the silicon wafer. Then, a tunneling oxide layer is prepared on the back of the silicon wafer, and a phosphorus-doped polycrystalline silicon layer is deposited using a top-down PVD magnetron sputtering process, followed by washing away the sodium chloride layer with water. This method allows for less or no masking on the silicon wafer surface, effectively increasing the light-receiving and usable area of ​​the silicon wafer surface, and significantly improving conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of N-type photovoltaic cell technology, specifically relating to a PVD masking method for N-type photovoltaic cells. Background Technology

[0002] In N-type photovoltaic cells, both HJT and TOPCON cells utilize PVD magnetron sputtering equipment to prepare TCO and phosphorus-doped polycrystalline silicon thin films, respectively. Both HJT's back-side TCO and TOPCON's phosphorus-doped polycrystalline silicon employ a bottom-up deposition method. This means the silicon wafer needs to be placed on a carrier plate, and the overlap between the carrier plate and the wafer forms a mask area. This mask area is obscured by the carrier plate and cannot be deposited, resulting in the following defects:

[0003] (1) The mask area is blocked by the carrier plate and cannot be coated with film, resulting in the mask area of ​​the battery cell not being utilized, reducing the light-receiving area, low battery current and low efficiency.

[0004] (2) Although reducing the mask area can reduce the adverse effects of the mask, it is difficult to keep the lateral distance between the mask area and the edge of the silicon wafer less than 0.8 mm. This is because: a) a small mask edge distance makes it easy to perform over-plating during the coating process, resulting in short circuits between the front and back sides; b) a small mask edge distance makes it difficult to achieve the required accuracy for automated wafer placement, causing the silicon wafer to be placed off-center and move during transport; c) a small mask edge distance makes it difficult to perform mechanical processing.

[0005] To reduce the mask area, the current approach mainly focuses on optimizing the design of the carrier plate. This involves reducing the mask edge distance to decrease the mask area and increase the coating area. However, due to issues such as the precision of wrap-around coating and machining, the mask area has almost reached its limit and cannot be reduced further, resulting in a loss of efficiency.

[0006] If a top-down deposition method is used, the carrier does not shield the silicon wafer. However, for HJT cells, the front and back TCOs will come into contact, forming a short circuit. For TOPCON cells, phosphorus-doped polycrystalline silicon will be deposited on the side of the silicon wafer. In the subsequent annealing and activation process, the phosphorus will diffuse into the silicon wafer below, reducing iVoc.

[0007] Therefore, in order to reduce or even eliminate the adverse effects of the masked area and improve battery efficiency, it is necessary to develop new technologies. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a PVD masking method for N-type photovoltaic cells that can reduce or even eliminate the masking area, increase the light-receiving and usable area of ​​the silicon wafer surface, and improve conversion efficiency.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution.

[0010] A PVD masking method for N-type photovoltaic cells involves the following steps during the fabrication of HJT solar cells: after preparing an N / P-type doped amorphous silicon layer, a sodium chloride layer is first coated on the side of the resulting silicon wafer. Then, a TCO thin film is deposited on the N / P-type doped amorphous silicon layer using a top-down PVD magnetron sputtering process. Finally, the sodium chloride layer on the side of the silicon wafer is washed away with water.

[0011] In the preferred embodiment of the PVD masking method for the above-mentioned N-type photovoltaic cell, the process of coating the side of the silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers are stacked, and then clamped on the upper and lower surfaces of the stacked silicon wafers by a fixture, so that only the side of the silicon wafer is exposed. A spray gun containing sodium chloride powder is used to spray the side of the silicon wafer, while the fixture is rotated horizontally 360° with the silicon wafer to make the sodium chloride powder evenly sprayed on the side of the silicon wafer.

[0012] In the above-described PVD masking method for N-type photovoltaic cells, preferably, the thickness of the sodium chloride layer is 0.2 μm to 200 μm.

[0013] As a general technical concept, the present invention also provides a PVD masking method for N-type photovoltaic cells. In the preparation process of TOPCON solar cells, after the PN junction is prepared, a sodium chloride layer is first coated on the side of the obtained silicon wafer, and then a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the back of the silicon wafer. The phosphorus-doped polycrystalline silicon layer is deposited by a top-down PVD magnetron sputtering process, and then the sodium chloride layer on the side of the silicon wafer is washed away with water.

[0014] In the preferred embodiment of the PVD masking method for the above-mentioned N-type photovoltaic cell, the process of coating the side of the silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers are stacked, and then clamped on the upper and lower surfaces of the stacked silicon wafers by a fixture, so that only the side of the silicon wafer is exposed. A spray gun containing sodium chloride powder is used to spray the side of the silicon wafer, while the fixture is rotated horizontally 360° with the silicon wafer to make the sodium chloride powder evenly sprayed on the side of the silicon wafer.

[0015] In the above-described PVD masking method for N-type photovoltaic cells, preferably, the thickness of the sodium chloride layer is 0.2 μm to 200 μm.

[0016] In existing technologies, magnetron sputtering is widely used in the industrial production of thin films due to its advantages such as lower deposition temperature requirements, stable and controllable deposition rates, good film uniformity and stability, relatively low cost, and ease of large-scale production. In HJT cells, TCO films, as antireflective films, can also enhance charge transport capabilities. In TOPCON cells, doped polycrystalline silicon protects the ultrathin silicon oxide and effectively reduces the recombination rate of charge carriers on the back side. In existing technologies, both TCO films and doped polycrystalline silicon films are prepared using PVD, employing a bottom-up deposition method to prepare TCO and phosphorus-doped polycrystalline silicon films respectively. However, bottom-up deposition requires the silicon wafer to be mounted on a carrier to form a mask, and the mask area has reached its limit and cannot be further reduced, resulting in efficiency loss. This invention proposes a novel masking method. First, halides are sprayed onto the sides of a silicon wafer, followed by PVD coating from top to bottom. Then, the halides are removed by water using a cleaning machine. This significantly reduces the masking area. At the same time, the coating layer on the sides of the silicon wafer will fall off as the halides dissolve, avoiding short circuits between the front and back TCO and the diffusion of phosphorus from phosphorus-doped polycrystalline silicon to crystalline silicon. This increases the coating area and improves the efficiency of the battery.

[0017] Compared with the prior art, the advantages of the present invention are as follows:

[0018] (1) This invention employs a novel masking method that utilizes the high solubility of sodium chloride in water to create a mask before PVD coating and remove the mask after PVD coating, thereby achieving a silicon wafer surface with little or no mask and improving the cell conversion efficiency. This masking method involves first spraying sodium chloride onto the side of the silicon wafer, then performing PVD coating from top to bottom, and finally removing the sodium chloride with water using a cleaning machine to complete the PVD coating with little or no mask.

[0019] (2) In the prior art, during PVD coating, the silicon wafer is placed on a carrier plate, and the overlap between the carrier plate and the silicon wafer forms a mask area. This mask area is blocked by the carrier plate and cannot be coated with a film layer. However, in the method of the present invention, the mask can be made on the side of the silicon wafer, and the surface of the silicon wafer can be completely coated with a film layer, increasing the light-receiving and usable area of ​​the silicon wafer surface and improving the conversion efficiency. Furthermore, in the fabrication process of N-type cells, the present invention can adopt a top-down coating method, which reduces the mask area while avoiding the short circuit between the front and back TCOs in HJT cells and the diffusion of phosphorus elements in phosphorus-doped polycrystalline silicon in TOPCON cells. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the sodium chloride layer coated on the side of the silicon wafer in Embodiments 1 and 2 of the present invention.

[0021] Legend:

[0022] 1. Stacked silicon wafers; 2. Fixture; 3. Spray gun. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention. All materials and instruments used in the following embodiments are commercially available.

[0024] Example 1

[0025] A PVD masking method for an N-type photovoltaic cell according to the present invention involves, during the fabrication of an HJT solar cell, after preparing an N / P-type doped amorphous silicon layer, first coating the side of the obtained silicon wafer with a sodium chloride layer, then depositing a TCO thin film (specifically an ITO thin film) on the N / P-type doped amorphous silicon layer using a top-down PVD magnetron sputtering process, and then washing away the sodium chloride layer on the side of the silicon wafer with water.

[0026] In this embodiment, as Figure 1 As shown, the process of coating the side of a silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers (e.g., 100 wafers) after N / P type doped amorphous silicon layers are stacked (top to bottom). Then, the wafers are clamped on the top and bottom surfaces of the stacked silicon wafers 1 by a clamp 2, so that only the side surfaces of the silicon wafers are exposed. The spray gun 3 containing sodium chloride powder is moved up and down to spray the side surfaces of the silicon wafers. At the same time, the clamp 2 is rotated horizontally 360° with the silicon wafers to make the sodium chloride powder evenly sprayed on the side surfaces of the silicon wafers.

[0027] In this embodiment, the thickness of the sodium chloride layer is 100 μm.

[0028] An application example of this embodiment is to use the method of this embodiment in the fabrication of HJT solar cells. The process flow is as follows:

[0029] (1) First, use the RCA silicon wafer cleaning process to texturize and clean the N-type monocrystalline silicon wafer;

[0030] (2) A 5nm intrinsic amorphous silicon layer was deposited using pure silane as a precursor by PECVD process.

[0031] (3) An 8nm P-type doped amorphous silicon layer (back side) and a 10nm N-type doped amorphous silicon layer (front side) were prepared by PECVD process to obtain an N / P-type doped amorphous silicon layer.

[0032] (4) A sodium chloride layer was coated on the side of the silicon wafer using the spraying process of Example 1;

[0033] (5) An ITO thin film is deposited on an N / P type doped amorphous silicon layer using a top-down PVD magnetron sputtering process;

[0034] (6) The silicon wafer is cleaned in a pure water cleaning machine. After the sodium chloride on the side of the silicon wafer dissolves in the water, the ITO on the side also falls off naturally, completing the masking and preparation of TCO. The N / P side of the silicon wafer is fully covered with TCO, which increases the coating area. There is no TCO on the side, which avoids the TCO short circuit on the N / P side.

[0035] (7) Metallization is performed using screen printing technology to form Ag electrodes.

[0036] The mask width of a conventional coating substrate is 0.8 mm. For every 0.1 mm reduction in mask width, the final cell conversion efficiency can be improved by 0.01%-0.02%. The method of this invention places the mask on the side of the silicon wafer, leaving almost no mask on the wafer surface. Compared with conventional coating masks, the conversion efficiency is improved by more than 0.1%.

[0037] Example 2

[0038] A PVD masking method for an N-type photovoltaic cell according to the present invention, in the fabrication process of TOPCON solar cells, after the PN junction is prepared, a sodium chloride layer is first coated on the side of the obtained silicon wafer, and then a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the back of the silicon wafer. The phosphorus-doped polycrystalline silicon layer is deposited by a top-down PVD magnetron sputtering process, and then the sodium chloride layer on the side of the silicon wafer is washed away with water.

[0039] In this embodiment, as Figure 1 As shown, the process of coating the side of a silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers after N / P type doped amorphous silicon layers are stacked, and then clamped on the upper and lower surfaces of the stacked silicon wafers 1 by a clamp 2, so that only the side of the silicon wafer is exposed. The spray gun 3 containing sodium chloride powder is moved up and down to spray the side of the silicon wafer. At the same time, the clamp 2 is rotated horizontally 360° with the silicon wafer to make the sodium chloride powder evenly sprayed on the side of the silicon wafer.

[0040] In this embodiment, the thickness of the sodium chloride layer is 150 μm.

[0041] An application example of this embodiment is to use the method of this embodiment in the fabrication of TOPCON solar cells. The process flow is as follows:

[0042] (1) After texturing the front side of the N-type silicon wafer, a PN junction is prepared;

[0043] (2) A sodium chloride layer is coated on the side of the silicon wafer using the spraying process of Example 2;

[0044] (3) A tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the back side of the silicon wafer; wherein the tunneling oxide layer is deposited by PECVD and the phosphorus-doped polycrystalline silicon layer is deposited by PVD magnetron sputtering from top to bottom.

[0045] (4) The silicon wafer is cleaned in a pure water cleaning machine. After the sodium chloride on the side of the silicon wafer dissolves in the water, the tunneling oxide layer and the phosphorus-doped polycrystalline silicon layer on it also fall off naturally. The coating area on the back of the silicon wafer is increased, and there is no phosphorus-doped polycrystalline silicon on the side, which avoids phosphorus diffusion into the crystalline silicon;

[0046] (5) Form a front electrode on the PN junction on the front side of the silicon wafer;

[0047] (6) A back electrode is formed on the phosphorus-doped polycrystalline silicon layer on the back side of the silicon wafer.

[0048] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the spirit and technical essence of the present invention. Therefore, any simple modifications, equivalent substitutions, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method of PVD masking of N-type photovoltaic cells, characterized by, In the fabrication process of HJT solar cells, after preparing the N / P type doped amorphous silicon layer, a sodium chloride layer is first coated on the side of the obtained silicon wafer. Then, a TCO thin film is deposited on the N / P type doped amorphous silicon layer using a top-down PVD magnetron sputtering process. Finally, the sodium chloride layer on the side of the silicon wafer is washed away with water.

2. The PVD masking method of an N-type photovoltaic cell according to claim 1, wherein, The process of coating the side of a silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers are stacked together, and then clamped on the upper and lower surfaces of the stacked silicon wafers by a fixture, so that only the side of the silicon wafer is exposed. A spray gun containing sodium chloride powder is used to spray the side of the silicon wafer, while the fixture is rotated horizontally 360° with the silicon wafer to make the sodium chloride powder evenly sprayed on the side of the silicon wafer.

3. The PVD masking method of an N-type photovoltaic cell according to claim 1 or 2, characterized in that, The thickness of the sodium chloride layer is 0.2 μm to 200 μm.

4. A method of PVD masking of an N-type photovoltaic cell, characterized by, In the fabrication process of TOPCON solar cells, after the PN junction is prepared, a sodium chloride layer is first coated on the side of the obtained silicon wafer, and then a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially prepared on the back of the silicon wafer. The phosphorus-doped polycrystalline silicon layer is deposited using a top-down PVD magnetron sputtering process, and then the sodium chloride layer on the side of the silicon wafer is washed away with water.

5. The PVD masking method of an N-type photovoltaic cell according to claim 4, wherein, The process of coating the side of a silicon wafer with a sodium chloride layer is as follows: multiple silicon wafers are stacked together, and then clamped on the upper and lower surfaces of the stacked silicon wafers by a fixture, so that only the side of the silicon wafer is exposed. A spray gun containing sodium chloride powder is used to spray the side of the silicon wafer, while the fixture is rotated horizontally 360° with the silicon wafer to make the sodium chloride powder evenly sprayed on the side of the silicon wafer.

6. The PVD masking method of an N-type photovoltaic cell according to claim 4 or 5, characterized in that, The thickness of the sodium chloride layer is 0.2 μm to 200 μm.

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