A critical mode interleaved pfc circuit and a control method thereof

Abstract

The application discloses a critical mode staggered PFC circuit and a control method thereof, and belongs to the technical field of electronic circuit control, and comprises a first inductor and a second inductor connected to an L pole, wherein the first inductor is externally connected with a first staggered current sampling circuit, the second inductor is externally connected with a second staggered current sampling circuit, the first staggered current sampling circuit is connected with a first transistor and a second transistor, the second staggered current sampling circuit is connected with a third transistor and a fourth transistor, the circuit N pole is connected with a fifth transistor and a sixth transistor, and the outer side of the fifth transistor and the sixth transistor is further connected with an output capacitor. The application introduces two zero-crossing signals through the design of the staggered circuit, so that the two signals are staggered by 180 degrees by designing a control method, thereby solving the problem of low reliability of the original scheme, improving the input THD, reducing the output capacitor temperature rise and pressure, and realizing miniaturization.

Description

Technical Field

[0001] This invention relates to a critical mode interleaved PFC circuit and its control method, belonging to the field of electronic circuit control technology. Background Technology

[0002] Current Critical Continuous Mode (CRM) PFC interleaving uses one zero-crossing detection to control the switching cycle and another prediction to control the switching cycle. However, there is an error between the prediction and the actual switching cycle. Introducing two zero-crossing signals in interleaving mode makes it impossible to achieve 180-degree interleaving between the two signals. Furthermore, the traditional interleaving circuit implementation suffers from low reliability due to the use of only one zero-crossing signal. Therefore, based on the problems existing in the current technology, how to achieve 180-degree interleaving between the two signals to obtain a better interleaving angle, thereby improving the input THD, improving the output capacitor temperature rise, and reducing the pressure, has become an urgent technical problem to be solved. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to provide a critical mode interleaved PFC circuit and its control method, thereby solving the problems encountered in the prior art.

[0004] The present invention discloses a critical mode interleaved PFC circuit, comprising a first inductor and a second inductor connected to the L terminal. A first interleaved current sampling circuit is externally connected to the first inductor, and a second interleaved current sampling circuit is externally connected to the second inductor. The first interleaved current sampling circuit is connected to a first transistor and a second transistor, and the second interleaved current sampling circuit is connected to a third transistor and a fourth transistor. A fifth transistor and a sixth transistor are connected to the N terminal of the circuit. The fifth and sixth transistors are connected to the outer loops of the first and second interleaved current sampling circuits, and an output capacitor is also connected to the outer side of the fifth and sixth transistors.

[0005] As a further technical solution of the present invention, the first interleaved current sampling circuit includes a first comparator. One side of the first comparator is connected to a current sampling point, a fixed negative voltage terminal and the DA output terminal of the controller, and the other end of the first comparator outputs the zero-crossing signal of the first interleaved current sampling circuit.

[0006] As a further technical solution of the present invention, the second interleaved current sampling circuit includes a second comparator. One side of the second comparator is connected to a current sampling point, a fixed negative voltage terminal and the DA output terminal of the controller, and the other end of the second comparator outputs the zero-crossing signal of the second interleaved current sampling circuit.

[0007] As a further technical solution of the present invention, the current sampling point adopts a current transformer.

[0008] As a further technical solution of the present invention, a first resistor and a second resistor are also connected externally to the first comparator.

[0009] As a further technical solution of the present invention, a third resistor and a fourth resistor are also connected externally to the second comparator.

[0010] The present invention provides a critical mode interleaved PFC circuit control method, comprising the following steps:

[0011] S1: Current is sampled through the first interleaved current sampling circuit and the second interleaved current sampling circuit respectively. The controller calculates and outputs a DA signal, which includes the DA signal before compensation and the compensation value.

[0012] S2: Calculate the DA signal V before compensation DA Satisfy the following formula:

[0013]

[0014] Where: L is the inductance value of the first and second inductors, K is the ratio of current to voltage, V- is the fixed negative voltage, Td is the delay effect of the first and second comparators, Vin is the input voltage, and V BUS R1 is the voltage across the output capacitor, Tex is the extension time of the driven transistor, R1 and R2 are the resistance values ​​of the first and second resistors, and R1 = R3, R2 = R4.

[0015] S3: The zero-crossing signals of the first interleaved current sampling circuit and the second interleaved current sampling circuit are obtained as the start signal of the cycle. When the controller obtains the zero-crossing signals of the first interleaved current sampling circuit and the second interleaved current sampling circuit, the internal counter is cleared.

[0016] As a further technical solution of the present invention, the method also includes adjusting the interleaving logic of the first interleaved current sampling circuit and the second interleaved current sampling circuit, specifically including the following steps:

[0017] S11: Determine the first interleaved current sampling circuit as the main circuit. When the input sine wave crosses the positive and negative zero points, the controller will offset the first interleaved current sampling circuit and the second interleaved current sampling circuit by 180 degrees according to the predicted period value of the internal counter. The start of the period is based on the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit.

[0018] S12: Before the input sine wave changes direction, the controller calculates the required compensation value for the first and second interleaved current sampling circuits based on the real-time period value calculated by the first and second interleaved current sampling circuits. Because the frequency changes rapidly when the input voltage is low, the required compensation value cannot be a difference. Simply taking the difference would result in a large difference in the interleaved angle. The controller's DA output signal is compensated as follows: the previous period value is recorded as T1, the current period value as T2, and the next switching period value as Tf is predicted and calculated. If Tf is greater than T... If Tf is larger than T2, the first interleaved current sampling circuit does not perform additional compensation, and the second interleaved current sampling circuit is compensated by half of (Tf-T2) and (T2-T1), that is, the second interleaved current sampling circuit is delayed; if Tf is larger than T2, the second interleaved current sampling circuit does not perform additional compensation, and the first interleaved current sampling circuit is compensated by half of (Tf-T2) and (T2-T1), that is, the first interleaved current sampling circuit is delayed, so as to obtain a better interleaving angle, thereby improving the input THD, improving the output capacitor temperature rise and reducing the pressure.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] This invention discloses a critical mode interleaved PFC circuit and its control method. The critical continuous mode (CRM) operates between continuous (CCM) and discontinuous (DCM) modes. When the input inductor current drops to zero, the switching transistor turns on, achieving partial zero-crossing stability (ZVS). By controlling the slave transistor to delay its turn-off, full-range ZVS is achieved, improving efficiency to a certain extent. Calculating Ton and Toff for CRM control is difficult, and predictions often have errors. Therefore, a current zero-crossing signal is introduced to ensure ZVS. In existing technologies, critical continuous mode (CRM) PFC interleaving uses one zero-crossing detection to control the switching cycle, and another prediction, resulting in prediction errors. This invention introduces two zero-crossing signals through an interleaved circuit, achieving 180-degree interleaving and improving input THD, output capacitor temperature rise, and pressure reduction. This solves the problems existing in the prior art. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a critical mode interleaved PFC circuit according to the present invention.

[0022] Figure 2 This is a circuit diagram of the first interleaved current sampling in a critical mode interleaved PFC circuit of the present invention;

[0023] Figure 3 This is a circuit diagram for sampling the second interleaved current in a critical mode interleaved PFC current according to the present invention.

[0024] Figure 4This is a timing diagram of a critical mode interleaved PFC circuit according to the present invention.

[0025] Figure 5 This is a flowchart illustrating the compensation of the DA output signal of the controller in a critical mode interleaved PFC circuit control method of the present invention.

[0026] In the diagram: L1, first inductor; L2, second inductor; Q1, first transistor; Q2, second transistor; Q3, third transistor; Q4, fourth transistor; Q5, fifth transistor; Q6, sixth transistor; C1, output capacitor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; U1, first comparator; U2, second comparator. Detailed Implementation

[0027] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0028] Example 1:

[0029] like Figure 1 As shown, the critical mode interleaved PFC circuit of the present invention includes a first inductor L1 and a second inductor L2 connected to the L terminal. A first interleaved current sampling circuit is connected to the outside of the first inductor L1, and a second interleaved current sampling circuit is connected to the outside of the second inductor L2. The first interleaved current sampling circuit is connected to a first transistor Q1 and a second transistor Q2. The second interleaved current sampling circuit is connected to a third transistor Q3 and a fourth transistor Q4. A fifth transistor Q5 and a sixth transistor Q6 are connected to the N terminal of the circuit. The fifth transistor Q5 and the sixth transistor Q6 are connected to the outer loops of the first interleaved current sampling circuit and the second interleaved current sampling circuit. An output capacitor C1 is also connected to the outside of the fifth transistor Q5 and the sixth transistor Q6.

[0030] like Figure 2 As shown, the first interleaved current sampling circuit includes a first comparator U1. One side of the first comparator U1 is connected to a current sampling point, a fixed negative voltage terminal and the DA output terminal of the controller. The other end of the first comparator U1 outputs the zero-crossing signal of the first interleaved current sampling circuit.

[0031] like Figure 3 As shown, the second interleaved current sampling circuit includes a second comparator U2. One side of the second comparator U2 is connected to the current sampling point, the fixed negative voltage terminal and the DA output terminal of the controller. The other end of the second comparator U2 outputs the zero-crossing signal of the second interleaved current sampling circuit.

[0032] like Figure 2-3As shown, the first comparator U1 and the second comparator U2 respectively obtain the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit. The DA signal is superimposed with the fixed negative voltage as the reference terminal. The inductor current is compared with the reference terminal to obtain the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit as the start signal of the cycle.

[0033] Current sampling points are achieved using current transformers.

[0034] The first comparator U1 is also externally connected to a first resistor R1 and a second resistor R2.

[0035] The second comparator U2 is also externally connected to a third resistor R3 and a fourth resistor R4.

[0036] The working principle of this embodiment is as follows: the inductance value of the first inductor L1 and the second inductor L2 is L. During the positive half-cycle, Q2 and Q4 are active transistors, and Q1 and Q3 are passive transistors. During the negative half-cycle, Q1 and Q3 are active transistors, and Q2 and Q4 are passive transistors. Current sampling is performed through the CT (interleaved current sampling 1 and interleaved current sampling 2, respectively, and the ratio of current to voltage is K). The secondary side is grounded with the controller. The controller calculates and outputs the DA signal and superimposes it with the fixed negative voltage V- at the negative terminals of comparators U1 and U2. U1 and U2 are comparators used to obtain the zero-crossing signal. Q5 and Q6 are low-frequency transistors, that is, Q6 is turned on and Q5 is turned off during the positive half-cycle of the input voltage; Q5 is turned on and Q6 is turned off during the negative half-cycle.

[0037] Interleaved zero-crossing signals 1 and 2 serve as the start signals of the cycle. When the controller receives interleaved zero-crossing signals 1 and 2, the internal counter is reset, the slave transistor is turned off, and the active transistor is turned on after the dead time. The timing diagram is as follows. Figure 4 As shown.

[0038] Example 2:

[0039] The present invention provides a critical mode interleaved PFC circuit control method, comprising the following steps:

[0040] S1: Current is sampled through the first interleaved current sampling circuit and the second interleaved current sampling circuit respectively. The controller calculates and outputs a DA signal, which includes the DA signal before compensation and the compensation value.

[0041] S2: Calculate the DA signal V before compensation DA Satisfy the following formula:

[0042]

[0043] Where: L is the inductance value of the first and second inductors, K is the ratio of current to voltage, V- is the fixed negative voltage, Td is the delay effect of the first and second comparators, Vin is the input voltage, and V BUS R1 is the voltage across the output capacitor, Tex is the extension time of the driven transistor, R1 and R2 are the resistance values ​​of the first and second resistors, and R1 = R3, R2 = R4.

[0044] S3: The compensated DA signal is superimposed with the fixed negative voltage as the reference terminal. The inductor current is compared with the reference terminal to obtain the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit as the start signal of the cycle. When the controller obtains the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit, the internal counter is cleared.

[0045] like Figure 5 As shown, the interleaving logic of the first and second interleaved current sampling circuits is implemented by adjusting the software interleaving angle at positive and negative zero crossings and the magnitude of the DA signal. Specifically, the steps include:

[0046] S11: Determine the first interleaved circuit sampling circuit as the main circuit. When the input sine wave crosses zero, the controller will offset the first interleaved current sampling circuit and the second interleaved current sampling circuit by 180 degrees according to the predicted period value. The controller will delay the second interleaved circuit internal counter by 1 / 2 of the predicted period value (Ton plus Toff). The start of the period is based on the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit.

[0047] S12: Before the input sine wave changes direction, the controller calculates the required compensation value for the first and second interleaved current sampling circuits based on the period value calculated in real time by the first and second interleaved current sampling circuits. Since the frequency changes rapidly when the input voltage is low, the required compensation value cannot be a difference value. Simply taking the difference value will result in a large difference in the interleaved angle.

[0048] The controller's DA output signal is compensated as follows (based on the DA signal calculation formula in S2): The previous cycle value is recorded as T1, the current cycle value as T2, and the next switching cycle value as Tf is predicted and calculated. If Tf is greater than T2, the first interleaved current sampling circuit does not perform additional compensation, and the second interleaved current sampling circuit takes half of (Tf-T2) and (T2-T1) as compensation, i.e., the second interleaved current sampling circuit is delayed. If Tf is greater than T2, the second interleaved current sampling circuit does not perform additional compensation, and the first interleaved current sampling circuit takes half of Tf-T2 and T2-T1 as compensation, i.e., the first interleaved current sampling circuit is delayed, in order to obtain a better interleaving angle, so that the input THD is improved, the temperature rise of the output capacitor C1 is improved, and the pressure is reduced.

[0049] Traditional interleaved circuit implementation suffers from low reliability due to the use of only one zero-crossing signal. This invention introduces two zero-crossing signals, which solves the problem of low reliability in the original scheme. Due to the reliability issues of the original interleaved circuit, non-interleaved circuits are now more commonly used. Compared to non-interleaved circuits, the interleaved result reduces current ripple, thereby improving input THD, reducing temperature rise and pressure of output capacitor C1.

[0050] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A critical mode interleaved PFC circuit control method, applied to a critical mode interleaved PFC circuit, the circuit including a first inductor (L1) and a second inductor (L2) connected to the L terminal, a first interleaved current sampling circuit externally connected to the first inductor (L1), a second interleaved current sampling circuit externally connected to the second inductor (L2), a first transistor (Q1) and a second transistor (Q2) connected to the first interleaved current sampling circuit, a third transistor (Q3) and a fourth transistor (Q4) connected to the second interleaved current sampling circuit, a fifth transistor (Q5) and a sixth transistor (Q6) connected to the N terminal of the circuit, the fifth transistor (Q5) and the sixth transistor (Q6) connected to the outer loops of the first interleaved current sampling circuit and the second interleaved current sampling circuit, the fifth transistor (Q5) and the sixth transistor (Q6) An output capacitor (C1) is also connected to the outside of the first interleaved current sampling circuit; the first interleaved current sampling circuit includes a first comparator (U1), one side of which is connected to a current sampling point, a fixed negative voltage terminal, and the DA output terminal of the controller, and the other end of the first comparator (U1) outputs the zero-crossing signal of the first interleaved current sampling circuit; the second interleaved current sampling circuit includes a second comparator (U2), one side of which is connected to a current sampling point, a fixed negative voltage terminal, and the DA output terminal of the controller, and the other end of the second comparator (U2) outputs the zero-crossing signal of the second interleaved current sampling circuit; a first resistor (R1) and a second resistor (R2) are also connected to the outside of the first comparator (U1); a third resistor (R3) and a fourth resistor (R4) are also connected to the outside of the second comparator (U2); characterized in that: The method includes the following steps: S1: Current is sampled through the first interleaved current sampling circuit and the second interleaved current sampling circuit respectively. The controller calculates and outputs a DA signal, which includes the DA signal before compensation and the compensation value. S2: Calculate the DA signal V before compensation DA Satisfy the following formula: （1） Where: L is the inductance value of the first inductor (L1) and the second inductor (L2), K is the ratio of current to voltage, V- is the fixed negative voltage, Td is the delay effect of the first comparator (U1) and the second comparator (U2), Vin is the input voltage, V BUS R1 is the voltage across the output capacitor (C1), Tex is the transistor extension time, R1 and R2 are the resistance values ​​of the first resistor (R1) and the second resistor (R2), and R1=R3, R2=R4. S3: The zero-crossing signals of the first interleaved current sampling circuit and the second interleaved current sampling circuit are obtained through the first comparator (U1) and the second comparator (U2) as the start signal of the cycle. When the controller obtains the zero-crossing signals of the first interleaved current sampling circuit and the second interleaved current sampling circuit, the internal counter is cleared.

2. The critical mode interleaved PFC circuit control method according to claim 1, characterized in that: The current sampling points are achieved using current transformers.

3. The critical mode interleaved PFC circuit control method according to claim 1, characterized in that: The method further includes adjusting the interleaving logic of the first interleaved current sampling circuit and the second interleaved current sampling circuit, specifically including the following steps: S11: Determine the first interleaved current sampling circuit as the main circuit. When the input sine wave crosses the positive and negative zero points, the controller will offset the first interleaved current sampling circuit and the second interleaved current sampling circuit by 180 degrees according to the predicted period value of the internal counter. The start of the period is based on the zero-crossing signal of the first interleaved current sampling circuit and the zero-crossing signal of the second interleaved current sampling circuit. S12: The controller calculates the required compensation value for the first and second interleaved current sampling circuits based on the period value calculated in real time from the first and second interleaved current sampling circuits. This value is then used to calculate the DA signal V obtained in step S2. DA Make compensation and calculate the compensation value.

4. The critical mode interleaved PFC circuit control method according to claim 3, characterized in that: In step S12, the controller controls the DA signal V. DA The compensation process includes the following steps: record the previous cycle value as T1, the current cycle value as T2, and predict and calculate the next switching cycle value as Tf. If Tf is greater than T2, the first interleaved current sampling circuit does not perform additional compensation, and the second interleaved current sampling circuit performs compensation of 1 / 2 of (Tf-T2) and (T2-T1), i.e., the second interleaved current sampling circuit is delayed. If Tf is greater than T2, the second interleaved current sampling circuit does not perform additional compensation, and the first interleaved current sampling circuit performs compensation of 1 / 2 of (Tf-T2) and (T2-T1), i.e., the first interleaved current sampling circuit is delayed, in order to obtain a better interleaving angle.

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